1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_OBJECT_H__ 29 #define __AMDGPU_OBJECT_H__ 30 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 34 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX 35 36 /** 37 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type 38 * @mem_type: ttm memory type 39 * 40 * Returns corresponding domain of the ttm mem_type 41 */ 42 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 43 { 44 switch (mem_type) { 45 case TTM_PL_VRAM: 46 return AMDGPU_GEM_DOMAIN_VRAM; 47 case TTM_PL_TT: 48 return AMDGPU_GEM_DOMAIN_GTT; 49 case TTM_PL_SYSTEM: 50 return AMDGPU_GEM_DOMAIN_CPU; 51 case AMDGPU_PL_GDS: 52 return AMDGPU_GEM_DOMAIN_GDS; 53 case AMDGPU_PL_GWS: 54 return AMDGPU_GEM_DOMAIN_GWS; 55 case AMDGPU_PL_OA: 56 return AMDGPU_GEM_DOMAIN_OA; 57 default: 58 break; 59 } 60 return 0; 61 } 62 63 /** 64 * amdgpu_bo_reserve - reserve bo 65 * @bo: bo structure 66 * @no_intr: don't return -ERESTARTSYS on pending signal 67 * 68 * Returns: 69 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 70 * a signal. Release all buffer reservations and return to user-space. 71 */ 72 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) 73 { 74 int r; 75 76 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 77 if (unlikely(r != 0)) { 78 if (r != -ERESTARTSYS) 79 dev_err(bo->adev->dev, "%p reserve failed\n", bo); 80 return r; 81 } 82 return 0; 83 } 84 85 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) 86 { 87 ttm_bo_unreserve(&bo->tbo); 88 } 89 90 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) 91 { 92 return bo->tbo.num_pages << PAGE_SHIFT; 93 } 94 95 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) 96 { 97 return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 98 } 99 100 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) 101 { 102 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 103 } 104 105 /** 106 * amdgpu_bo_mmap_offset - return mmap offset of bo 107 * @bo: amdgpu object for which we query the offset 108 * 109 * Returns mmap offset of the object. 110 */ 111 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) 112 { 113 return drm_vma_node_offset_addr(&bo->tbo.vma_node); 114 } 115 116 int amdgpu_bo_create(struct amdgpu_device *adev, 117 unsigned long size, int byte_align, 118 bool kernel, u32 domain, u64 flags, 119 struct sg_table *sg, 120 struct reservation_object *resv, 121 struct amdgpu_bo **bo_ptr); 122 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 123 unsigned long size, int byte_align, 124 bool kernel, u32 domain, u64 flags, 125 struct sg_table *sg, 126 struct ttm_placement *placement, 127 struct reservation_object *resv, 128 struct amdgpu_bo **bo_ptr); 129 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 130 unsigned long size, int align, 131 u32 domain, struct amdgpu_bo **bo_ptr, 132 u64 *gpu_addr, void **cpu_addr); 133 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 134 void **cpu_addr); 135 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); 136 void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 137 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 138 void amdgpu_bo_unref(struct amdgpu_bo **bo); 139 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr); 140 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 141 u64 min_offset, u64 max_offset, 142 u64 *gpu_addr); 143 int amdgpu_bo_unpin(struct amdgpu_bo *bo); 144 int amdgpu_bo_evict_vram(struct amdgpu_device *adev); 145 int amdgpu_bo_init(struct amdgpu_device *adev); 146 void amdgpu_bo_fini(struct amdgpu_device *adev); 147 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 148 struct vm_area_struct *vma); 149 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 150 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); 151 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 152 uint32_t metadata_size, uint64_t flags); 153 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 154 size_t buffer_size, uint32_t *metadata_size, 155 uint64_t *flags); 156 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 157 struct ttm_mem_reg *new_mem); 158 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 159 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, 160 bool shared); 161 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); 162 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 163 struct amdgpu_ring *ring, 164 struct amdgpu_bo *bo, 165 struct reservation_object *resv, 166 struct fence **fence, bool direct); 167 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 168 struct amdgpu_ring *ring, 169 struct amdgpu_bo *bo, 170 struct reservation_object *resv, 171 struct fence **fence, 172 bool direct); 173 174 175 /* 176 * sub allocation 177 */ 178 179 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) 180 { 181 return sa_bo->manager->gpu_addr + sa_bo->soffset; 182 } 183 184 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) 185 { 186 return sa_bo->manager->cpu_ptr + sa_bo->soffset; 187 } 188 189 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 190 struct amdgpu_sa_manager *sa_manager, 191 unsigned size, u32 align, u32 domain); 192 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, 193 struct amdgpu_sa_manager *sa_manager); 194 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, 195 struct amdgpu_sa_manager *sa_manager); 196 int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, 197 struct amdgpu_sa_manager *sa_manager); 198 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 199 struct amdgpu_sa_bo **sa_bo, 200 unsigned size, unsigned align); 201 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 202 struct amdgpu_sa_bo **sa_bo, 203 struct fence *fence); 204 #if defined(CONFIG_DEBUG_FS) 205 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 206 struct seq_file *m); 207 #endif 208 209 210 #endif 211