1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __AMDGPU_OBJECT_H__
29 #define __AMDGPU_OBJECT_H__
30 
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 #include "amdgpu_res_cursor.h"
34 
35 #ifdef CONFIG_MMU_NOTIFIER
36 #include <linux/mmu_notifier.h>
37 #endif
38 
39 #define AMDGPU_BO_INVALID_OFFSET	LONG_MAX
40 #define AMDGPU_BO_MAX_PLACEMENTS	3
41 
42 /* BO flag to indicate a KFD userptr BO */
43 #define AMDGPU_AMDKFD_CREATE_USERPTR_BO	(1ULL << 63)
44 
45 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
46 #define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
47 
48 struct amdgpu_bo_param {
49 	unsigned long			size;
50 	int				byte_align;
51 	u32				bo_ptr_size;
52 	u32				domain;
53 	u32				preferred_domain;
54 	u64				flags;
55 	enum ttm_bo_type		type;
56 	bool				no_wait_gpu;
57 	struct dma_resv			*resv;
58 	void				(*destroy)(struct ttm_buffer_object *bo);
59 	/* xcp partition number plus 1, 0 means any partition */
60 	int8_t				xcp_id_plus1;
61 };
62 
63 /* bo virtual addresses in a vm */
64 struct amdgpu_bo_va_mapping {
65 	struct amdgpu_bo_va		*bo_va;
66 	struct list_head		list;
67 	struct rb_node			rb;
68 	uint64_t			start;
69 	uint64_t			last;
70 	uint64_t			__subtree_last;
71 	uint64_t			offset;
72 	uint64_t			flags;
73 };
74 
75 /* User space allocated BO in a VM */
76 struct amdgpu_bo_va {
77 	struct amdgpu_vm_bo_base	base;
78 
79 	/* protected by bo being reserved */
80 	unsigned			ref_count;
81 
82 	/* all other members protected by the VM PD being reserved */
83 	struct dma_fence	        *last_pt_update;
84 
85 	/* mappings for this bo_va */
86 	struct list_head		invalids;
87 	struct list_head		valids;
88 
89 	/* If the mappings are cleared or filled */
90 	bool				cleared;
91 
92 	bool				is_xgmi;
93 };
94 
95 struct amdgpu_bo {
96 	/* Protected by tbo.reserved */
97 	u32				preferred_domains;
98 	u32				allowed_domains;
99 	struct ttm_place		placements[AMDGPU_BO_MAX_PLACEMENTS];
100 	struct ttm_placement		placement;
101 	struct ttm_buffer_object	tbo;
102 	struct ttm_bo_kmap_obj		kmap;
103 	u64				flags;
104 	/* per VM structure for page tables and with virtual addresses */
105 	struct amdgpu_vm_bo_base	*vm_bo;
106 	/* Constant after initialization */
107 	struct amdgpu_bo		*parent;
108 
109 #ifdef CONFIG_MMU_NOTIFIER
110 	struct mmu_interval_notifier	notifier;
111 #endif
112 	struct kgd_mem                  *kfd_bo;
113 
114 	/*
115 	 * For GPUs with spatial partitioning, xcp partition number, -1 means
116 	 * any partition. For other ASICs without spatial partition, always 0
117 	 * for memory accounting.
118 	 */
119 	int8_t				xcp_id;
120 };
121 
122 struct amdgpu_bo_user {
123 	struct amdgpu_bo		bo;
124 	u64				tiling_flags;
125 	u64				metadata_flags;
126 	void				*metadata;
127 	u32				metadata_size;
128 
129 };
130 
131 struct amdgpu_bo_vm {
132 	struct amdgpu_bo		bo;
133 	struct amdgpu_bo		*shadow;
134 	struct list_head		shadow_list;
135 	struct amdgpu_vm_bo_base        entries[];
136 };
137 
138 struct amdgpu_mem_stats {
139 	/* current VRAM usage, includes visible VRAM */
140 	uint64_t vram;
141 	/* current shared VRAM usage, includes visible VRAM */
142 	uint64_t vram_shared;
143 	/* current visible VRAM usage */
144 	uint64_t visible_vram;
145 	/* current GTT usage */
146 	uint64_t gtt;
147 	/* current shared GTT usage */
148 	uint64_t gtt_shared;
149 	/* current system memory usage */
150 	uint64_t cpu;
151 	/* current shared system memory usage */
152 	uint64_t cpu_shared;
153 	/* sum of evicted buffers, includes visible VRAM */
154 	uint64_t evicted_vram;
155 	/* sum of evicted buffers due to CPU access */
156 	uint64_t evicted_visible_vram;
157 	/* how much userspace asked for, includes vis.VRAM */
158 	uint64_t requested_vram;
159 	/* how much userspace asked for */
160 	uint64_t requested_visible_vram;
161 	/* how much userspace asked for */
162 	uint64_t requested_gtt;
163 };
164 
165 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
166 {
167 	return container_of(tbo, struct amdgpu_bo, tbo);
168 }
169 
170 /**
171  * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
172  * @mem_type:	ttm memory type
173  *
174  * Returns corresponding domain of the ttm mem_type
175  */
176 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
177 {
178 	switch (mem_type) {
179 	case TTM_PL_VRAM:
180 		return AMDGPU_GEM_DOMAIN_VRAM;
181 	case TTM_PL_TT:
182 		return AMDGPU_GEM_DOMAIN_GTT;
183 	case TTM_PL_SYSTEM:
184 		return AMDGPU_GEM_DOMAIN_CPU;
185 	case AMDGPU_PL_GDS:
186 		return AMDGPU_GEM_DOMAIN_GDS;
187 	case AMDGPU_PL_GWS:
188 		return AMDGPU_GEM_DOMAIN_GWS;
189 	case AMDGPU_PL_OA:
190 		return AMDGPU_GEM_DOMAIN_OA;
191 	case AMDGPU_PL_DOORBELL:
192 		return AMDGPU_GEM_DOMAIN_DOORBELL;
193 	default:
194 		break;
195 	}
196 	return 0;
197 }
198 
199 /**
200  * amdgpu_bo_reserve - reserve bo
201  * @bo:		bo structure
202  * @no_intr:	don't return -ERESTARTSYS on pending signal
203  *
204  * Returns:
205  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
206  * a signal. Release all buffer reservations and return to user-space.
207  */
208 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
209 {
210 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
211 	int r;
212 
213 	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
214 	if (unlikely(r != 0)) {
215 		if (r != -ERESTARTSYS)
216 			dev_err(adev->dev, "%p reserve failed\n", bo);
217 		return r;
218 	}
219 	return 0;
220 }
221 
222 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
223 {
224 	ttm_bo_unreserve(&bo->tbo);
225 }
226 
227 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
228 {
229 	return bo->tbo.base.size;
230 }
231 
232 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
233 {
234 	return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
235 }
236 
237 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
238 {
239 	return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
240 }
241 
242 /**
243  * amdgpu_bo_mmap_offset - return mmap offset of bo
244  * @bo:	amdgpu object for which we query the offset
245  *
246  * Returns mmap offset of the object.
247  */
248 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
249 {
250 	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
251 }
252 
253 /**
254  * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
255  */
256 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
257 {
258 	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
259 }
260 
261 /**
262  * amdgpu_bo_encrypted - test if the BO is encrypted
263  * @bo: pointer to a buffer object
264  *
265  * Return true if the buffer object is encrypted, false otherwise.
266  */
267 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
268 {
269 	return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
270 }
271 
272 /**
273  * amdgpu_bo_shadowed - check if the BO is shadowed
274  *
275  * @bo: BO to be tested.
276  *
277  * Returns:
278  * NULL if not shadowed or else return a BO pointer.
279  */
280 static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo)
281 {
282 	if (bo->tbo.type == ttm_bo_type_kernel)
283 		return to_amdgpu_bo_vm(bo)->shadow;
284 
285 	return NULL;
286 }
287 
288 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
289 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
290 
291 int amdgpu_bo_create(struct amdgpu_device *adev,
292 		     struct amdgpu_bo_param *bp,
293 		     struct amdgpu_bo **bo_ptr);
294 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
295 			      unsigned long size, int align,
296 			      u32 domain, struct amdgpu_bo **bo_ptr,
297 			      u64 *gpu_addr, void **cpu_addr);
298 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
299 			    unsigned long size, int align,
300 			    u32 domain, struct amdgpu_bo **bo_ptr,
301 			    u64 *gpu_addr, void **cpu_addr);
302 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
303 			       uint64_t offset, uint64_t size,
304 			       struct amdgpu_bo **bo_ptr, void **cpu_addr);
305 int amdgpu_bo_create_user(struct amdgpu_device *adev,
306 			  struct amdgpu_bo_param *bp,
307 			  struct amdgpu_bo_user **ubo_ptr);
308 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
309 			struct amdgpu_bo_param *bp,
310 			struct amdgpu_bo_vm **ubo_ptr);
311 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
312 			   void **cpu_addr);
313 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
314 void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
315 void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
316 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
317 void amdgpu_bo_unref(struct amdgpu_bo **bo);
318 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
319 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
320 			     u64 min_offset, u64 max_offset);
321 void amdgpu_bo_unpin(struct amdgpu_bo *bo);
322 int amdgpu_bo_init(struct amdgpu_device *adev);
323 void amdgpu_bo_fini(struct amdgpu_device *adev);
324 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
325 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
326 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
327 			    uint32_t metadata_size, uint64_t flags);
328 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
329 			   size_t buffer_size, uint32_t *metadata_size,
330 			   uint64_t *flags);
331 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);
332 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
333 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
334 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
335 		     bool shared);
336 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
337 			     enum amdgpu_sync_mode sync_mode, void *owner,
338 			     bool intr);
339 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
340 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
341 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
342 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
343 			  struct amdgpu_mem_stats *stats);
344 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo);
345 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
346 			     struct dma_fence **fence);
347 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
348 					    uint32_t domain);
349 
350 /*
351  * sub allocation
352  */
353 static inline struct amdgpu_sa_manager *
354 to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
355 {
356 	return container_of(manager, struct amdgpu_sa_manager, base);
357 }
358 
359 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
360 {
361 	return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
362 		drm_suballoc_soffset(sa_bo);
363 }
364 
365 static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
366 {
367 	return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
368 		drm_suballoc_soffset(sa_bo);
369 }
370 
371 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
372 				     struct amdgpu_sa_manager *sa_manager,
373 				     unsigned size, u32 align, u32 domain);
374 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
375 				      struct amdgpu_sa_manager *sa_manager);
376 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
377 				      struct amdgpu_sa_manager *sa_manager);
378 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
379 		     struct drm_suballoc **sa_bo,
380 		     unsigned int size);
381 void amdgpu_sa_bo_free(struct amdgpu_device *adev,
382 		       struct drm_suballoc **sa_bo,
383 		       struct dma_fence *fence);
384 #if defined(CONFIG_DEBUG_FS)
385 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
386 					 struct seq_file *m);
387 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
388 #endif
389 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
390 
391 bool amdgpu_bo_support_uswc(u64 bo_flags);
392 
393 
394 #endif
395