1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 40 41 42 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, 43 struct ttm_mem_reg *mem) 44 { 45 if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size) 46 return 0; 47 48 return ((mem->start << PAGE_SHIFT) + mem->size) > 49 adev->mc.visible_vram_size ? 50 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : 51 mem->size; 52 } 53 54 static void amdgpu_update_memory_usage(struct amdgpu_device *adev, 55 struct ttm_mem_reg *old_mem, 56 struct ttm_mem_reg *new_mem) 57 { 58 u64 vis_size; 59 if (!adev) 60 return; 61 62 if (new_mem) { 63 switch (new_mem->mem_type) { 64 case TTM_PL_TT: 65 atomic64_add(new_mem->size, &adev->gtt_usage); 66 break; 67 case TTM_PL_VRAM: 68 atomic64_add(new_mem->size, &adev->vram_usage); 69 vis_size = amdgpu_get_vis_part_size(adev, new_mem); 70 atomic64_add(vis_size, &adev->vram_vis_usage); 71 break; 72 } 73 } 74 75 if (old_mem) { 76 switch (old_mem->mem_type) { 77 case TTM_PL_TT: 78 atomic64_sub(old_mem->size, &adev->gtt_usage); 79 break; 80 case TTM_PL_VRAM: 81 atomic64_sub(old_mem->size, &adev->vram_usage); 82 vis_size = amdgpu_get_vis_part_size(adev, old_mem); 83 atomic64_sub(vis_size, &adev->vram_vis_usage); 84 break; 85 } 86 } 87 } 88 89 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 90 { 91 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 92 struct amdgpu_bo *bo; 93 94 bo = container_of(tbo, struct amdgpu_bo, tbo); 95 96 amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL); 97 98 drm_gem_object_release(&bo->gem_base); 99 amdgpu_bo_unref(&bo->parent); 100 if (!list_empty(&bo->shadow_list)) { 101 mutex_lock(&adev->shadow_list_lock); 102 list_del_init(&bo->shadow_list); 103 mutex_unlock(&adev->shadow_list_lock); 104 } 105 kfree(bo->metadata); 106 kfree(bo); 107 } 108 109 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 110 { 111 if (bo->destroy == &amdgpu_ttm_bo_destroy) 112 return true; 113 return false; 114 } 115 116 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 117 struct ttm_placement *placement, 118 struct ttm_place *places, 119 u32 domain, u64 flags) 120 { 121 u32 c = 0; 122 123 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 124 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 125 unsigned lpfn = 0; 126 127 /* This forces a reallocation if the flag wasn't set before */ 128 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 129 lpfn = adev->mc.real_vram_size >> PAGE_SHIFT; 130 131 places[c].fpfn = 0; 132 places[c].lpfn = lpfn; 133 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 134 TTM_PL_FLAG_VRAM; 135 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 136 places[c].lpfn = visible_pfn; 137 else 138 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 139 c++; 140 } 141 142 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 143 places[c].fpfn = 0; 144 places[c].lpfn = 0; 145 places[c].flags = TTM_PL_FLAG_TT; 146 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 147 places[c].flags |= TTM_PL_FLAG_WC | 148 TTM_PL_FLAG_UNCACHED; 149 else 150 places[c].flags |= TTM_PL_FLAG_CACHED; 151 c++; 152 } 153 154 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 155 places[c].fpfn = 0; 156 places[c].lpfn = 0; 157 places[c].flags = TTM_PL_FLAG_SYSTEM; 158 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 159 places[c].flags |= TTM_PL_FLAG_WC | 160 TTM_PL_FLAG_UNCACHED; 161 else 162 places[c].flags |= TTM_PL_FLAG_CACHED; 163 c++; 164 } 165 166 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 167 places[c].fpfn = 0; 168 places[c].lpfn = 0; 169 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 170 c++; 171 } 172 173 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 174 places[c].fpfn = 0; 175 places[c].lpfn = 0; 176 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 177 c++; 178 } 179 180 if (domain & AMDGPU_GEM_DOMAIN_OA) { 181 places[c].fpfn = 0; 182 places[c].lpfn = 0; 183 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 184 c++; 185 } 186 187 if (!c) { 188 places[c].fpfn = 0; 189 places[c].lpfn = 0; 190 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 191 c++; 192 } 193 194 placement->num_placement = c; 195 placement->placement = places; 196 197 placement->num_busy_placement = c; 198 placement->busy_placement = places; 199 } 200 201 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 202 { 203 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 204 205 amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements, 206 domain, abo->flags); 207 } 208 209 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 210 struct ttm_placement *placement) 211 { 212 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 213 214 memcpy(bo->placements, placement->placement, 215 placement->num_placement * sizeof(struct ttm_place)); 216 bo->placement.num_placement = placement->num_placement; 217 bo->placement.num_busy_placement = placement->num_busy_placement; 218 bo->placement.placement = bo->placements; 219 bo->placement.busy_placement = bo->placements; 220 } 221 222 /** 223 * amdgpu_bo_create_kernel - create BO for kernel use 224 * 225 * @adev: amdgpu device object 226 * @size: size for the new BO 227 * @align: alignment for the new BO 228 * @domain: where to place it 229 * @bo_ptr: resulting BO 230 * @gpu_addr: GPU addr of the pinned BO 231 * @cpu_addr: optional CPU address mapping 232 * 233 * Allocates and pins a BO for kernel internal use. 234 * 235 * Returns 0 on success, negative error code otherwise. 236 */ 237 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 238 unsigned long size, int align, 239 u32 domain, struct amdgpu_bo **bo_ptr, 240 u64 *gpu_addr, void **cpu_addr) 241 { 242 int r; 243 244 r = amdgpu_bo_create(adev, size, align, true, domain, 245 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 246 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 247 NULL, NULL, bo_ptr); 248 if (r) { 249 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r); 250 return r; 251 } 252 253 r = amdgpu_bo_reserve(*bo_ptr, false); 254 if (r) { 255 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 256 goto error_free; 257 } 258 259 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr); 260 if (r) { 261 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 262 goto error_unreserve; 263 } 264 265 if (cpu_addr) { 266 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 267 if (r) { 268 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 269 goto error_unreserve; 270 } 271 } 272 273 amdgpu_bo_unreserve(*bo_ptr); 274 275 return 0; 276 277 error_unreserve: 278 amdgpu_bo_unreserve(*bo_ptr); 279 280 error_free: 281 amdgpu_bo_unref(bo_ptr); 282 283 return r; 284 } 285 286 /** 287 * amdgpu_bo_free_kernel - free BO for kernel use 288 * 289 * @bo: amdgpu BO to free 290 * 291 * unmaps and unpin a BO for kernel internal use. 292 */ 293 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 294 void **cpu_addr) 295 { 296 if (*bo == NULL) 297 return; 298 299 if (likely(amdgpu_bo_reserve(*bo, false) == 0)) { 300 if (cpu_addr) 301 amdgpu_bo_kunmap(*bo); 302 303 amdgpu_bo_unpin(*bo); 304 amdgpu_bo_unreserve(*bo); 305 } 306 amdgpu_bo_unref(bo); 307 308 if (gpu_addr) 309 *gpu_addr = 0; 310 311 if (cpu_addr) 312 *cpu_addr = NULL; 313 } 314 315 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 316 unsigned long size, int byte_align, 317 bool kernel, u32 domain, u64 flags, 318 struct sg_table *sg, 319 struct ttm_placement *placement, 320 struct reservation_object *resv, 321 struct amdgpu_bo **bo_ptr) 322 { 323 struct amdgpu_bo *bo; 324 enum ttm_bo_type type; 325 unsigned long page_align; 326 u64 initial_bytes_moved; 327 size_t acc_size; 328 int r; 329 330 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 331 size = ALIGN(size, PAGE_SIZE); 332 333 if (kernel) { 334 type = ttm_bo_type_kernel; 335 } else if (sg) { 336 type = ttm_bo_type_sg; 337 } else { 338 type = ttm_bo_type_device; 339 } 340 *bo_ptr = NULL; 341 342 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 343 sizeof(struct amdgpu_bo)); 344 345 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 346 if (bo == NULL) 347 return -ENOMEM; 348 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 349 if (unlikely(r)) { 350 kfree(bo); 351 return r; 352 } 353 INIT_LIST_HEAD(&bo->shadow_list); 354 INIT_LIST_HEAD(&bo->va); 355 bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | 356 AMDGPU_GEM_DOMAIN_GTT | 357 AMDGPU_GEM_DOMAIN_CPU | 358 AMDGPU_GEM_DOMAIN_GDS | 359 AMDGPU_GEM_DOMAIN_GWS | 360 AMDGPU_GEM_DOMAIN_OA); 361 bo->allowed_domains = bo->prefered_domains; 362 if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 363 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 364 365 bo->flags = flags; 366 367 #ifdef CONFIG_X86_32 368 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 369 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 370 */ 371 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 372 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 373 /* Don't try to enable write-combining when it can't work, or things 374 * may be slow 375 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 376 */ 377 378 #ifndef CONFIG_COMPILE_TEST 379 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 380 thanks to write-combining 381 #endif 382 383 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 384 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 385 "better performance thanks to write-combining\n"); 386 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 387 #else 388 /* For architectures that don't support WC memory, 389 * mask out the WC flag from the BO 390 */ 391 if (!drm_arch_can_wc_memory()) 392 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 393 #endif 394 395 amdgpu_fill_placement_to_bo(bo, placement); 396 /* Kernel allocation are uninterruptible */ 397 398 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); 399 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, 400 &bo->placement, page_align, !kernel, NULL, 401 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 402 amdgpu_cs_report_moved_bytes(adev, 403 atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved); 404 405 if (unlikely(r != 0)) 406 return r; 407 408 bo->tbo.priority = ilog2(bo->tbo.num_pages); 409 if (kernel) 410 bo->tbo.priority *= 2; 411 bo->tbo.priority = min(bo->tbo.priority, (unsigned)(TTM_MAX_BO_PRIORITY - 1)); 412 413 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 414 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 415 struct dma_fence *fence; 416 417 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); 418 if (unlikely(r)) 419 goto fail_unreserve; 420 421 amdgpu_bo_fence(bo, fence, false); 422 dma_fence_put(bo->tbo.moving); 423 bo->tbo.moving = dma_fence_get(fence); 424 dma_fence_put(fence); 425 } 426 if (!resv) 427 amdgpu_bo_unreserve(bo); 428 *bo_ptr = bo; 429 430 trace_amdgpu_bo_create(bo); 431 432 return 0; 433 434 fail_unreserve: 435 if (!resv) 436 ww_mutex_unlock(&bo->tbo.resv->lock); 437 amdgpu_bo_unref(&bo); 438 return r; 439 } 440 441 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 442 unsigned long size, int byte_align, 443 struct amdgpu_bo *bo) 444 { 445 struct ttm_placement placement = {0}; 446 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 447 int r; 448 449 if (bo->shadow) 450 return 0; 451 452 bo->flags |= AMDGPU_GEM_CREATE_SHADOW; 453 memset(&placements, 0, 454 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 455 456 amdgpu_ttm_placement_init(adev, &placement, 457 placements, AMDGPU_GEM_DOMAIN_GTT, 458 AMDGPU_GEM_CREATE_CPU_GTT_USWC); 459 460 r = amdgpu_bo_create_restricted(adev, size, byte_align, true, 461 AMDGPU_GEM_DOMAIN_GTT, 462 AMDGPU_GEM_CREATE_CPU_GTT_USWC, 463 NULL, &placement, 464 bo->tbo.resv, 465 &bo->shadow); 466 if (!r) { 467 bo->shadow->parent = amdgpu_bo_ref(bo); 468 mutex_lock(&adev->shadow_list_lock); 469 list_add_tail(&bo->shadow_list, &adev->shadow_list); 470 mutex_unlock(&adev->shadow_list_lock); 471 } 472 473 return r; 474 } 475 476 int amdgpu_bo_create(struct amdgpu_device *adev, 477 unsigned long size, int byte_align, 478 bool kernel, u32 domain, u64 flags, 479 struct sg_table *sg, 480 struct reservation_object *resv, 481 struct amdgpu_bo **bo_ptr) 482 { 483 struct ttm_placement placement = {0}; 484 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 485 int r; 486 487 memset(&placements, 0, 488 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 489 490 amdgpu_ttm_placement_init(adev, &placement, 491 placements, domain, flags); 492 493 r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, 494 domain, flags, sg, &placement, 495 resv, bo_ptr); 496 if (r) 497 return r; 498 499 if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) { 500 if (!resv) { 501 r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL); 502 WARN_ON(r != 0); 503 } 504 505 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr)); 506 507 if (!resv) 508 ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock); 509 510 if (r) 511 amdgpu_bo_unref(bo_ptr); 512 } 513 514 return r; 515 } 516 517 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 518 struct amdgpu_ring *ring, 519 struct amdgpu_bo *bo, 520 struct reservation_object *resv, 521 struct dma_fence **fence, 522 bool direct) 523 524 { 525 struct amdgpu_bo *shadow = bo->shadow; 526 uint64_t bo_addr, shadow_addr; 527 int r; 528 529 if (!shadow) 530 return -EINVAL; 531 532 bo_addr = amdgpu_bo_gpu_offset(bo); 533 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 534 535 r = reservation_object_reserve_shared(bo->tbo.resv); 536 if (r) 537 goto err; 538 539 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr, 540 amdgpu_bo_size(bo), resv, fence, 541 direct); 542 if (!r) 543 amdgpu_bo_fence(bo, *fence, true); 544 545 err: 546 return r; 547 } 548 549 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 550 struct amdgpu_ring *ring, 551 struct amdgpu_bo *bo, 552 struct reservation_object *resv, 553 struct dma_fence **fence, 554 bool direct) 555 556 { 557 struct amdgpu_bo *shadow = bo->shadow; 558 uint64_t bo_addr, shadow_addr; 559 int r; 560 561 if (!shadow) 562 return -EINVAL; 563 564 bo_addr = amdgpu_bo_gpu_offset(bo); 565 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 566 567 r = reservation_object_reserve_shared(bo->tbo.resv); 568 if (r) 569 goto err; 570 571 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr, 572 amdgpu_bo_size(bo), resv, fence, 573 direct); 574 if (!r) 575 amdgpu_bo_fence(bo, *fence, true); 576 577 err: 578 return r; 579 } 580 581 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 582 { 583 bool is_iomem; 584 long r; 585 586 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 587 return -EPERM; 588 589 if (bo->kptr) { 590 if (ptr) { 591 *ptr = bo->kptr; 592 } 593 return 0; 594 } 595 596 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 597 MAX_SCHEDULE_TIMEOUT); 598 if (r < 0) 599 return r; 600 601 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 602 if (r) 603 return r; 604 605 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 606 if (ptr) 607 *ptr = bo->kptr; 608 609 return 0; 610 } 611 612 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 613 { 614 if (bo->kptr == NULL) 615 return; 616 bo->kptr = NULL; 617 ttm_bo_kunmap(&bo->kmap); 618 } 619 620 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 621 { 622 if (bo == NULL) 623 return NULL; 624 625 ttm_bo_reference(&bo->tbo); 626 return bo; 627 } 628 629 void amdgpu_bo_unref(struct amdgpu_bo **bo) 630 { 631 struct ttm_buffer_object *tbo; 632 633 if ((*bo) == NULL) 634 return; 635 636 tbo = &((*bo)->tbo); 637 ttm_bo_unref(&tbo); 638 if (tbo == NULL) 639 *bo = NULL; 640 } 641 642 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 643 u64 min_offset, u64 max_offset, 644 u64 *gpu_addr) 645 { 646 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 647 int r, i; 648 unsigned fpfn, lpfn; 649 650 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 651 return -EPERM; 652 653 if (WARN_ON_ONCE(min_offset > max_offset)) 654 return -EINVAL; 655 656 if (bo->pin_count) { 657 uint32_t mem_type = bo->tbo.mem.mem_type; 658 659 if (domain != amdgpu_mem_type_to_domain(mem_type)) 660 return -EINVAL; 661 662 bo->pin_count++; 663 if (gpu_addr) 664 *gpu_addr = amdgpu_bo_gpu_offset(bo); 665 666 if (max_offset != 0) { 667 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 668 WARN_ON_ONCE(max_offset < 669 (amdgpu_bo_gpu_offset(bo) - domain_start)); 670 } 671 672 return 0; 673 } 674 675 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 676 amdgpu_ttm_placement_from_domain(bo, domain); 677 for (i = 0; i < bo->placement.num_placement; i++) { 678 /* force to pin into visible video ram */ 679 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 680 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 681 (!max_offset || max_offset > 682 adev->mc.visible_vram_size)) { 683 if (WARN_ON_ONCE(min_offset > 684 adev->mc.visible_vram_size)) 685 return -EINVAL; 686 fpfn = min_offset >> PAGE_SHIFT; 687 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 688 } else { 689 fpfn = min_offset >> PAGE_SHIFT; 690 lpfn = max_offset >> PAGE_SHIFT; 691 } 692 if (fpfn > bo->placements[i].fpfn) 693 bo->placements[i].fpfn = fpfn; 694 if (!bo->placements[i].lpfn || 695 (lpfn && lpfn < bo->placements[i].lpfn)) 696 bo->placements[i].lpfn = lpfn; 697 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 698 } 699 700 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 701 if (unlikely(r)) { 702 dev_err(adev->dev, "%p pin failed\n", bo); 703 goto error; 704 } 705 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); 706 if (unlikely(r)) { 707 dev_err(adev->dev, "%p bind failed\n", bo); 708 goto error; 709 } 710 711 bo->pin_count = 1; 712 if (gpu_addr != NULL) 713 *gpu_addr = amdgpu_bo_gpu_offset(bo); 714 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 715 adev->vram_pin_size += amdgpu_bo_size(bo); 716 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 717 adev->invisible_pin_size += amdgpu_bo_size(bo); 718 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 719 adev->gart_pin_size += amdgpu_bo_size(bo); 720 } 721 722 error: 723 return r; 724 } 725 726 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 727 { 728 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 729 } 730 731 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 732 { 733 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 734 int r, i; 735 736 if (!bo->pin_count) { 737 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 738 return 0; 739 } 740 bo->pin_count--; 741 if (bo->pin_count) 742 return 0; 743 for (i = 0; i < bo->placement.num_placement; i++) { 744 bo->placements[i].lpfn = 0; 745 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 746 } 747 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 748 if (unlikely(r)) { 749 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 750 goto error; 751 } 752 753 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 754 adev->vram_pin_size -= amdgpu_bo_size(bo); 755 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 756 adev->invisible_pin_size -= amdgpu_bo_size(bo); 757 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 758 adev->gart_pin_size -= amdgpu_bo_size(bo); 759 } 760 761 error: 762 return r; 763 } 764 765 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 766 { 767 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 768 if (0 && (adev->flags & AMD_IS_APU)) { 769 /* Useless to evict on IGP chips */ 770 return 0; 771 } 772 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 773 } 774 775 static const char *amdgpu_vram_names[] = { 776 "UNKNOWN", 777 "GDDR1", 778 "DDR2", 779 "GDDR3", 780 "GDDR4", 781 "GDDR5", 782 "HBM", 783 "DDR3" 784 }; 785 786 int amdgpu_bo_init(struct amdgpu_device *adev) 787 { 788 /* reserve PAT memory space to WC for VRAM */ 789 arch_io_reserve_memtype_wc(adev->mc.aper_base, 790 adev->mc.aper_size); 791 792 /* Add an MTRR for the VRAM */ 793 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 794 adev->mc.aper_size); 795 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 796 adev->mc.mc_vram_size >> 20, 797 (unsigned long long)adev->mc.aper_size >> 20); 798 DRM_INFO("RAM width %dbits %s\n", 799 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); 800 return amdgpu_ttm_init(adev); 801 } 802 803 void amdgpu_bo_fini(struct amdgpu_device *adev) 804 { 805 amdgpu_ttm_fini(adev); 806 arch_phys_wc_del(adev->mc.vram_mtrr); 807 arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size); 808 } 809 810 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 811 struct vm_area_struct *vma) 812 { 813 return ttm_fbdev_mmap(vma, &bo->tbo); 814 } 815 816 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 817 { 818 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 819 820 if (adev->family <= AMDGPU_FAMILY_CZ && 821 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 822 return -EINVAL; 823 824 bo->tiling_flags = tiling_flags; 825 return 0; 826 } 827 828 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 829 { 830 lockdep_assert_held(&bo->tbo.resv->lock.base); 831 832 if (tiling_flags) 833 *tiling_flags = bo->tiling_flags; 834 } 835 836 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 837 uint32_t metadata_size, uint64_t flags) 838 { 839 void *buffer; 840 841 if (!metadata_size) { 842 if (bo->metadata_size) { 843 kfree(bo->metadata); 844 bo->metadata = NULL; 845 bo->metadata_size = 0; 846 } 847 return 0; 848 } 849 850 if (metadata == NULL) 851 return -EINVAL; 852 853 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 854 if (buffer == NULL) 855 return -ENOMEM; 856 857 kfree(bo->metadata); 858 bo->metadata_flags = flags; 859 bo->metadata = buffer; 860 bo->metadata_size = metadata_size; 861 862 return 0; 863 } 864 865 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 866 size_t buffer_size, uint32_t *metadata_size, 867 uint64_t *flags) 868 { 869 if (!buffer && !metadata_size) 870 return -EINVAL; 871 872 if (buffer) { 873 if (buffer_size < bo->metadata_size) 874 return -EINVAL; 875 876 if (bo->metadata_size) 877 memcpy(buffer, bo->metadata, bo->metadata_size); 878 } 879 880 if (metadata_size) 881 *metadata_size = bo->metadata_size; 882 if (flags) 883 *flags = bo->metadata_flags; 884 885 return 0; 886 } 887 888 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 889 bool evict, 890 struct ttm_mem_reg *new_mem) 891 { 892 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 893 struct amdgpu_bo *abo; 894 struct ttm_mem_reg *old_mem = &bo->mem; 895 896 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 897 return; 898 899 abo = container_of(bo, struct amdgpu_bo, tbo); 900 amdgpu_vm_bo_invalidate(adev, abo); 901 902 /* remember the eviction */ 903 if (evict) 904 atomic64_inc(&adev->num_evictions); 905 906 /* update statistics */ 907 if (!new_mem) 908 return; 909 910 /* move_notify is called before move happens */ 911 amdgpu_update_memory_usage(adev, &bo->mem, new_mem); 912 913 trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 914 } 915 916 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 917 { 918 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 919 struct amdgpu_bo *abo; 920 unsigned long offset, size, lpfn; 921 int i, r; 922 923 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 924 return 0; 925 926 abo = container_of(bo, struct amdgpu_bo, tbo); 927 if (bo->mem.mem_type != TTM_PL_VRAM) 928 return 0; 929 930 size = bo->mem.num_pages << PAGE_SHIFT; 931 offset = bo->mem.start << PAGE_SHIFT; 932 /* TODO: figure out how to map scattered VRAM to the CPU */ 933 if ((offset + size) <= adev->mc.visible_vram_size && 934 (abo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) 935 return 0; 936 937 /* Can't move a pinned BO to visible VRAM */ 938 if (abo->pin_count > 0) 939 return -EINVAL; 940 941 /* hurrah the memory is not visible ! */ 942 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 943 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); 944 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 945 for (i = 0; i < abo->placement.num_placement; i++) { 946 /* Force into visible VRAM */ 947 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && 948 (!abo->placements[i].lpfn || 949 abo->placements[i].lpfn > lpfn)) 950 abo->placements[i].lpfn = lpfn; 951 } 952 r = ttm_bo_validate(bo, &abo->placement, false, false); 953 if (unlikely(r == -ENOMEM)) { 954 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 955 return ttm_bo_validate(bo, &abo->placement, false, false); 956 } else if (unlikely(r != 0)) { 957 return r; 958 } 959 960 offset = bo->mem.start << PAGE_SHIFT; 961 /* this should never happen */ 962 if ((offset + size) > adev->mc.visible_vram_size) 963 return -EINVAL; 964 965 return 0; 966 } 967 968 /** 969 * amdgpu_bo_fence - add fence to buffer object 970 * 971 * @bo: buffer object in question 972 * @fence: fence to add 973 * @shared: true if fence should be added shared 974 * 975 */ 976 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 977 bool shared) 978 { 979 struct reservation_object *resv = bo->tbo.resv; 980 981 if (shared) 982 reservation_object_add_shared_fence(resv, fence); 983 else 984 reservation_object_add_excl_fence(resv, fence); 985 } 986 987 /** 988 * amdgpu_bo_gpu_offset - return GPU offset of bo 989 * @bo: amdgpu object for which we query the offset 990 * 991 * Returns current GPU offset of the object. 992 * 993 * Note: object should either be pinned or reserved when calling this 994 * function, it might be useful to add check for this for debugging. 995 */ 996 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 997 { 998 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 999 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && 1000 !amdgpu_ttm_is_bound(bo->tbo.ttm)); 1001 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 1002 !bo->pin_count); 1003 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1004 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1005 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1006 1007 return bo->tbo.offset; 1008 } 1009