1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 40 41 42 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, 43 struct ttm_mem_reg *mem) 44 { 45 if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size) 46 return 0; 47 48 return ((mem->start << PAGE_SHIFT) + mem->size) > 49 adev->mc.visible_vram_size ? 50 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : 51 mem->size; 52 } 53 54 static void amdgpu_update_memory_usage(struct amdgpu_device *adev, 55 struct ttm_mem_reg *old_mem, 56 struct ttm_mem_reg *new_mem) 57 { 58 u64 vis_size; 59 if (!adev) 60 return; 61 62 if (new_mem) { 63 switch (new_mem->mem_type) { 64 case TTM_PL_TT: 65 atomic64_add(new_mem->size, &adev->gtt_usage); 66 break; 67 case TTM_PL_VRAM: 68 atomic64_add(new_mem->size, &adev->vram_usage); 69 vis_size = amdgpu_get_vis_part_size(adev, new_mem); 70 atomic64_add(vis_size, &adev->vram_vis_usage); 71 break; 72 } 73 } 74 75 if (old_mem) { 76 switch (old_mem->mem_type) { 77 case TTM_PL_TT: 78 atomic64_sub(old_mem->size, &adev->gtt_usage); 79 break; 80 case TTM_PL_VRAM: 81 atomic64_sub(old_mem->size, &adev->vram_usage); 82 vis_size = amdgpu_get_vis_part_size(adev, old_mem); 83 atomic64_sub(vis_size, &adev->vram_vis_usage); 84 break; 85 } 86 } 87 } 88 89 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 90 { 91 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 92 struct amdgpu_bo *bo; 93 94 bo = container_of(tbo, struct amdgpu_bo, tbo); 95 96 amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL); 97 98 drm_gem_object_release(&bo->gem_base); 99 amdgpu_bo_unref(&bo->parent); 100 if (!list_empty(&bo->shadow_list)) { 101 mutex_lock(&adev->shadow_list_lock); 102 list_del_init(&bo->shadow_list); 103 mutex_unlock(&adev->shadow_list_lock); 104 } 105 kfree(bo->metadata); 106 kfree(bo); 107 } 108 109 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 110 { 111 if (bo->destroy == &amdgpu_ttm_bo_destroy) 112 return true; 113 return false; 114 } 115 116 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 117 struct ttm_placement *placement, 118 struct ttm_place *places, 119 u32 domain, u64 flags) 120 { 121 u32 c = 0; 122 123 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 124 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 125 unsigned lpfn = 0; 126 127 /* This forces a reallocation if the flag wasn't set before */ 128 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 129 lpfn = adev->mc.real_vram_size >> PAGE_SHIFT; 130 131 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && 132 !(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 133 adev->mc.visible_vram_size < adev->mc.real_vram_size) { 134 places[c].fpfn = visible_pfn; 135 places[c].lpfn = lpfn; 136 places[c].flags = TTM_PL_FLAG_WC | 137 TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM | 138 TTM_PL_FLAG_TOPDOWN; 139 c++; 140 } 141 142 places[c].fpfn = 0; 143 places[c].lpfn = lpfn; 144 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 145 TTM_PL_FLAG_VRAM; 146 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 147 places[c].lpfn = visible_pfn; 148 else 149 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 150 c++; 151 } 152 153 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 154 places[c].fpfn = 0; 155 places[c].lpfn = 0; 156 places[c].flags = TTM_PL_FLAG_TT; 157 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 158 places[c].flags |= TTM_PL_FLAG_WC | 159 TTM_PL_FLAG_UNCACHED; 160 else 161 places[c].flags |= TTM_PL_FLAG_CACHED; 162 c++; 163 } 164 165 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 166 places[c].fpfn = 0; 167 places[c].lpfn = 0; 168 places[c].flags = TTM_PL_FLAG_SYSTEM; 169 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 170 places[c].flags |= TTM_PL_FLAG_WC | 171 TTM_PL_FLAG_UNCACHED; 172 else 173 places[c].flags |= TTM_PL_FLAG_CACHED; 174 c++; 175 } 176 177 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 178 places[c].fpfn = 0; 179 places[c].lpfn = 0; 180 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 181 c++; 182 } 183 184 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 185 places[c].fpfn = 0; 186 places[c].lpfn = 0; 187 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 188 c++; 189 } 190 191 if (domain & AMDGPU_GEM_DOMAIN_OA) { 192 places[c].fpfn = 0; 193 places[c].lpfn = 0; 194 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 195 c++; 196 } 197 198 if (!c) { 199 places[c].fpfn = 0; 200 places[c].lpfn = 0; 201 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 202 c++; 203 } 204 205 placement->num_placement = c; 206 placement->placement = places; 207 208 placement->num_busy_placement = c; 209 placement->busy_placement = places; 210 } 211 212 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 213 { 214 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 215 216 amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements, 217 domain, abo->flags); 218 } 219 220 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 221 struct ttm_placement *placement) 222 { 223 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 224 225 memcpy(bo->placements, placement->placement, 226 placement->num_placement * sizeof(struct ttm_place)); 227 bo->placement.num_placement = placement->num_placement; 228 bo->placement.num_busy_placement = placement->num_busy_placement; 229 bo->placement.placement = bo->placements; 230 bo->placement.busy_placement = bo->placements; 231 } 232 233 /** 234 * amdgpu_bo_create_kernel - create BO for kernel use 235 * 236 * @adev: amdgpu device object 237 * @size: size for the new BO 238 * @align: alignment for the new BO 239 * @domain: where to place it 240 * @bo_ptr: resulting BO 241 * @gpu_addr: GPU addr of the pinned BO 242 * @cpu_addr: optional CPU address mapping 243 * 244 * Allocates and pins a BO for kernel internal use. 245 * 246 * Returns 0 on success, negative error code otherwise. 247 */ 248 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 249 unsigned long size, int align, 250 u32 domain, struct amdgpu_bo **bo_ptr, 251 u64 *gpu_addr, void **cpu_addr) 252 { 253 int r; 254 255 r = amdgpu_bo_create(adev, size, align, true, domain, 256 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 257 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 258 NULL, NULL, bo_ptr); 259 if (r) { 260 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r); 261 return r; 262 } 263 264 r = amdgpu_bo_reserve(*bo_ptr, false); 265 if (r) { 266 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 267 goto error_free; 268 } 269 270 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr); 271 if (r) { 272 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 273 goto error_unreserve; 274 } 275 276 if (cpu_addr) { 277 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 278 if (r) { 279 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 280 goto error_unreserve; 281 } 282 } 283 284 amdgpu_bo_unreserve(*bo_ptr); 285 286 return 0; 287 288 error_unreserve: 289 amdgpu_bo_unreserve(*bo_ptr); 290 291 error_free: 292 amdgpu_bo_unref(bo_ptr); 293 294 return r; 295 } 296 297 /** 298 * amdgpu_bo_free_kernel - free BO for kernel use 299 * 300 * @bo: amdgpu BO to free 301 * 302 * unmaps and unpin a BO for kernel internal use. 303 */ 304 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 305 void **cpu_addr) 306 { 307 if (*bo == NULL) 308 return; 309 310 if (likely(amdgpu_bo_reserve(*bo, false) == 0)) { 311 if (cpu_addr) 312 amdgpu_bo_kunmap(*bo); 313 314 amdgpu_bo_unpin(*bo); 315 amdgpu_bo_unreserve(*bo); 316 } 317 amdgpu_bo_unref(bo); 318 319 if (gpu_addr) 320 *gpu_addr = 0; 321 322 if (cpu_addr) 323 *cpu_addr = NULL; 324 } 325 326 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 327 unsigned long size, int byte_align, 328 bool kernel, u32 domain, u64 flags, 329 struct sg_table *sg, 330 struct ttm_placement *placement, 331 struct reservation_object *resv, 332 struct amdgpu_bo **bo_ptr) 333 { 334 struct amdgpu_bo *bo; 335 enum ttm_bo_type type; 336 unsigned long page_align; 337 size_t acc_size; 338 int r; 339 340 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 341 size = ALIGN(size, PAGE_SIZE); 342 343 if (kernel) { 344 type = ttm_bo_type_kernel; 345 } else if (sg) { 346 type = ttm_bo_type_sg; 347 } else { 348 type = ttm_bo_type_device; 349 } 350 *bo_ptr = NULL; 351 352 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 353 sizeof(struct amdgpu_bo)); 354 355 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 356 if (bo == NULL) 357 return -ENOMEM; 358 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 359 if (unlikely(r)) { 360 kfree(bo); 361 return r; 362 } 363 INIT_LIST_HEAD(&bo->shadow_list); 364 INIT_LIST_HEAD(&bo->va); 365 bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | 366 AMDGPU_GEM_DOMAIN_GTT | 367 AMDGPU_GEM_DOMAIN_CPU | 368 AMDGPU_GEM_DOMAIN_GDS | 369 AMDGPU_GEM_DOMAIN_GWS | 370 AMDGPU_GEM_DOMAIN_OA); 371 bo->allowed_domains = bo->prefered_domains; 372 if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 373 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 374 375 bo->flags = flags; 376 377 /* For architectures that don't support WC memory, 378 * mask out the WC flag from the BO 379 */ 380 if (!drm_arch_can_wc_memory()) 381 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 382 383 amdgpu_fill_placement_to_bo(bo, placement); 384 /* Kernel allocation are uninterruptible */ 385 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 386 &bo->placement, page_align, !kernel, NULL, 387 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 388 if (unlikely(r != 0)) { 389 return r; 390 } 391 392 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 393 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 394 struct dma_fence *fence; 395 396 if (adev->mman.buffer_funcs_ring == NULL || 397 !adev->mman.buffer_funcs_ring->ready) { 398 r = -EBUSY; 399 goto fail_free; 400 } 401 402 r = amdgpu_bo_reserve(bo, false); 403 if (unlikely(r != 0)) 404 goto fail_free; 405 406 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 407 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 408 if (unlikely(r != 0)) 409 goto fail_unreserve; 410 411 amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); 412 amdgpu_bo_fence(bo, fence, false); 413 amdgpu_bo_unreserve(bo); 414 dma_fence_put(bo->tbo.moving); 415 bo->tbo.moving = dma_fence_get(fence); 416 dma_fence_put(fence); 417 } 418 *bo_ptr = bo; 419 420 trace_amdgpu_bo_create(bo); 421 422 return 0; 423 424 fail_unreserve: 425 amdgpu_bo_unreserve(bo); 426 fail_free: 427 amdgpu_bo_unref(&bo); 428 return r; 429 } 430 431 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 432 unsigned long size, int byte_align, 433 struct amdgpu_bo *bo) 434 { 435 struct ttm_placement placement = {0}; 436 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 437 int r; 438 439 if (bo->shadow) 440 return 0; 441 442 bo->flags |= AMDGPU_GEM_CREATE_SHADOW; 443 memset(&placements, 0, 444 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 445 446 amdgpu_ttm_placement_init(adev, &placement, 447 placements, AMDGPU_GEM_DOMAIN_GTT, 448 AMDGPU_GEM_CREATE_CPU_GTT_USWC); 449 450 r = amdgpu_bo_create_restricted(adev, size, byte_align, true, 451 AMDGPU_GEM_DOMAIN_GTT, 452 AMDGPU_GEM_CREATE_CPU_GTT_USWC, 453 NULL, &placement, 454 bo->tbo.resv, 455 &bo->shadow); 456 if (!r) { 457 bo->shadow->parent = amdgpu_bo_ref(bo); 458 mutex_lock(&adev->shadow_list_lock); 459 list_add_tail(&bo->shadow_list, &adev->shadow_list); 460 mutex_unlock(&adev->shadow_list_lock); 461 } 462 463 return r; 464 } 465 466 int amdgpu_bo_create(struct amdgpu_device *adev, 467 unsigned long size, int byte_align, 468 bool kernel, u32 domain, u64 flags, 469 struct sg_table *sg, 470 struct reservation_object *resv, 471 struct amdgpu_bo **bo_ptr) 472 { 473 struct ttm_placement placement = {0}; 474 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 475 int r; 476 477 memset(&placements, 0, 478 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 479 480 amdgpu_ttm_placement_init(adev, &placement, 481 placements, domain, flags); 482 483 r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, 484 domain, flags, sg, &placement, 485 resv, bo_ptr); 486 if (r) 487 return r; 488 489 if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) { 490 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr)); 491 if (r) 492 amdgpu_bo_unref(bo_ptr); 493 } 494 495 return r; 496 } 497 498 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 499 struct amdgpu_ring *ring, 500 struct amdgpu_bo *bo, 501 struct reservation_object *resv, 502 struct dma_fence **fence, 503 bool direct) 504 505 { 506 struct amdgpu_bo *shadow = bo->shadow; 507 uint64_t bo_addr, shadow_addr; 508 int r; 509 510 if (!shadow) 511 return -EINVAL; 512 513 bo_addr = amdgpu_bo_gpu_offset(bo); 514 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 515 516 r = reservation_object_reserve_shared(bo->tbo.resv); 517 if (r) 518 goto err; 519 520 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr, 521 amdgpu_bo_size(bo), resv, fence, 522 direct); 523 if (!r) 524 amdgpu_bo_fence(bo, *fence, true); 525 526 err: 527 return r; 528 } 529 530 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 531 struct amdgpu_ring *ring, 532 struct amdgpu_bo *bo, 533 struct reservation_object *resv, 534 struct dma_fence **fence, 535 bool direct) 536 537 { 538 struct amdgpu_bo *shadow = bo->shadow; 539 uint64_t bo_addr, shadow_addr; 540 int r; 541 542 if (!shadow) 543 return -EINVAL; 544 545 bo_addr = amdgpu_bo_gpu_offset(bo); 546 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 547 548 r = reservation_object_reserve_shared(bo->tbo.resv); 549 if (r) 550 goto err; 551 552 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr, 553 amdgpu_bo_size(bo), resv, fence, 554 direct); 555 if (!r) 556 amdgpu_bo_fence(bo, *fence, true); 557 558 err: 559 return r; 560 } 561 562 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 563 { 564 bool is_iomem; 565 long r; 566 567 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 568 return -EPERM; 569 570 if (bo->kptr) { 571 if (ptr) { 572 *ptr = bo->kptr; 573 } 574 return 0; 575 } 576 577 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 578 MAX_SCHEDULE_TIMEOUT); 579 if (r < 0) 580 return r; 581 582 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 583 if (r) 584 return r; 585 586 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 587 if (ptr) 588 *ptr = bo->kptr; 589 590 return 0; 591 } 592 593 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 594 { 595 if (bo->kptr == NULL) 596 return; 597 bo->kptr = NULL; 598 ttm_bo_kunmap(&bo->kmap); 599 } 600 601 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 602 { 603 if (bo == NULL) 604 return NULL; 605 606 ttm_bo_reference(&bo->tbo); 607 return bo; 608 } 609 610 void amdgpu_bo_unref(struct amdgpu_bo **bo) 611 { 612 struct ttm_buffer_object *tbo; 613 614 if ((*bo) == NULL) 615 return; 616 617 tbo = &((*bo)->tbo); 618 ttm_bo_unref(&tbo); 619 if (tbo == NULL) 620 *bo = NULL; 621 } 622 623 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 624 u64 min_offset, u64 max_offset, 625 u64 *gpu_addr) 626 { 627 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 628 int r, i; 629 unsigned fpfn, lpfn; 630 631 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 632 return -EPERM; 633 634 if (WARN_ON_ONCE(min_offset > max_offset)) 635 return -EINVAL; 636 637 if (bo->pin_count) { 638 uint32_t mem_type = bo->tbo.mem.mem_type; 639 640 if (domain != amdgpu_mem_type_to_domain(mem_type)) 641 return -EINVAL; 642 643 bo->pin_count++; 644 if (gpu_addr) 645 *gpu_addr = amdgpu_bo_gpu_offset(bo); 646 647 if (max_offset != 0) { 648 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 649 WARN_ON_ONCE(max_offset < 650 (amdgpu_bo_gpu_offset(bo) - domain_start)); 651 } 652 653 return 0; 654 } 655 656 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 657 amdgpu_ttm_placement_from_domain(bo, domain); 658 for (i = 0; i < bo->placement.num_placement; i++) { 659 /* force to pin into visible video ram */ 660 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 661 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 662 (!max_offset || max_offset > 663 adev->mc.visible_vram_size)) { 664 if (WARN_ON_ONCE(min_offset > 665 adev->mc.visible_vram_size)) 666 return -EINVAL; 667 fpfn = min_offset >> PAGE_SHIFT; 668 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 669 } else { 670 fpfn = min_offset >> PAGE_SHIFT; 671 lpfn = max_offset >> PAGE_SHIFT; 672 } 673 if (fpfn > bo->placements[i].fpfn) 674 bo->placements[i].fpfn = fpfn; 675 if (!bo->placements[i].lpfn || 676 (lpfn && lpfn < bo->placements[i].lpfn)) 677 bo->placements[i].lpfn = lpfn; 678 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 679 } 680 681 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 682 if (unlikely(r)) { 683 dev_err(adev->dev, "%p pin failed\n", bo); 684 goto error; 685 } 686 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); 687 if (unlikely(r)) { 688 dev_err(adev->dev, "%p bind failed\n", bo); 689 goto error; 690 } 691 692 bo->pin_count = 1; 693 if (gpu_addr != NULL) 694 *gpu_addr = amdgpu_bo_gpu_offset(bo); 695 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 696 adev->vram_pin_size += amdgpu_bo_size(bo); 697 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 698 adev->invisible_pin_size += amdgpu_bo_size(bo); 699 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 700 adev->gart_pin_size += amdgpu_bo_size(bo); 701 } 702 703 error: 704 return r; 705 } 706 707 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 708 { 709 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 710 } 711 712 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 713 { 714 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 715 int r, i; 716 717 if (!bo->pin_count) { 718 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 719 return 0; 720 } 721 bo->pin_count--; 722 if (bo->pin_count) 723 return 0; 724 for (i = 0; i < bo->placement.num_placement; i++) { 725 bo->placements[i].lpfn = 0; 726 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 727 } 728 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 729 if (unlikely(r)) { 730 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 731 goto error; 732 } 733 734 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 735 adev->vram_pin_size -= amdgpu_bo_size(bo); 736 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 737 adev->invisible_pin_size -= amdgpu_bo_size(bo); 738 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 739 adev->gart_pin_size -= amdgpu_bo_size(bo); 740 } 741 742 error: 743 return r; 744 } 745 746 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 747 { 748 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 749 if (0 && (adev->flags & AMD_IS_APU)) { 750 /* Useless to evict on IGP chips */ 751 return 0; 752 } 753 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 754 } 755 756 static const char *amdgpu_vram_names[] = { 757 "UNKNOWN", 758 "GDDR1", 759 "DDR2", 760 "GDDR3", 761 "GDDR4", 762 "GDDR5", 763 "HBM", 764 "DDR3" 765 }; 766 767 int amdgpu_bo_init(struct amdgpu_device *adev) 768 { 769 /* reserve PAT memory space to WC for VRAM */ 770 arch_io_reserve_memtype_wc(adev->mc.aper_base, 771 adev->mc.aper_size); 772 773 /* Add an MTRR for the VRAM */ 774 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 775 adev->mc.aper_size); 776 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 777 adev->mc.mc_vram_size >> 20, 778 (unsigned long long)adev->mc.aper_size >> 20); 779 DRM_INFO("RAM width %dbits %s\n", 780 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); 781 return amdgpu_ttm_init(adev); 782 } 783 784 void amdgpu_bo_fini(struct amdgpu_device *adev) 785 { 786 amdgpu_ttm_fini(adev); 787 arch_phys_wc_del(adev->mc.vram_mtrr); 788 arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size); 789 } 790 791 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 792 struct vm_area_struct *vma) 793 { 794 return ttm_fbdev_mmap(vma, &bo->tbo); 795 } 796 797 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 798 { 799 if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 800 return -EINVAL; 801 802 bo->tiling_flags = tiling_flags; 803 return 0; 804 } 805 806 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 807 { 808 lockdep_assert_held(&bo->tbo.resv->lock.base); 809 810 if (tiling_flags) 811 *tiling_flags = bo->tiling_flags; 812 } 813 814 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 815 uint32_t metadata_size, uint64_t flags) 816 { 817 void *buffer; 818 819 if (!metadata_size) { 820 if (bo->metadata_size) { 821 kfree(bo->metadata); 822 bo->metadata = NULL; 823 bo->metadata_size = 0; 824 } 825 return 0; 826 } 827 828 if (metadata == NULL) 829 return -EINVAL; 830 831 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 832 if (buffer == NULL) 833 return -ENOMEM; 834 835 kfree(bo->metadata); 836 bo->metadata_flags = flags; 837 bo->metadata = buffer; 838 bo->metadata_size = metadata_size; 839 840 return 0; 841 } 842 843 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 844 size_t buffer_size, uint32_t *metadata_size, 845 uint64_t *flags) 846 { 847 if (!buffer && !metadata_size) 848 return -EINVAL; 849 850 if (buffer) { 851 if (buffer_size < bo->metadata_size) 852 return -EINVAL; 853 854 if (bo->metadata_size) 855 memcpy(buffer, bo->metadata, bo->metadata_size); 856 } 857 858 if (metadata_size) 859 *metadata_size = bo->metadata_size; 860 if (flags) 861 *flags = bo->metadata_flags; 862 863 return 0; 864 } 865 866 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 867 struct ttm_mem_reg *new_mem) 868 { 869 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 870 struct amdgpu_bo *abo; 871 struct ttm_mem_reg *old_mem = &bo->mem; 872 873 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 874 return; 875 876 abo = container_of(bo, struct amdgpu_bo, tbo); 877 amdgpu_vm_bo_invalidate(adev, abo); 878 879 /* update statistics */ 880 if (!new_mem) 881 return; 882 883 /* move_notify is called before move happens */ 884 amdgpu_update_memory_usage(adev, &bo->mem, new_mem); 885 886 trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 887 } 888 889 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 890 { 891 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 892 struct amdgpu_bo *abo; 893 unsigned long offset, size, lpfn; 894 int i, r; 895 896 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 897 return 0; 898 899 abo = container_of(bo, struct amdgpu_bo, tbo); 900 if (bo->mem.mem_type != TTM_PL_VRAM) 901 return 0; 902 903 size = bo->mem.num_pages << PAGE_SHIFT; 904 offset = bo->mem.start << PAGE_SHIFT; 905 /* TODO: figure out how to map scattered VRAM to the CPU */ 906 if ((offset + size) <= adev->mc.visible_vram_size && 907 (abo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) 908 return 0; 909 910 /* Can't move a pinned BO to visible VRAM */ 911 if (abo->pin_count > 0) 912 return -EINVAL; 913 914 /* hurrah the memory is not visible ! */ 915 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 916 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); 917 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 918 for (i = 0; i < abo->placement.num_placement; i++) { 919 /* Force into visible VRAM */ 920 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && 921 (!abo->placements[i].lpfn || 922 abo->placements[i].lpfn > lpfn)) 923 abo->placements[i].lpfn = lpfn; 924 } 925 r = ttm_bo_validate(bo, &abo->placement, false, false); 926 if (unlikely(r == -ENOMEM)) { 927 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 928 return ttm_bo_validate(bo, &abo->placement, false, false); 929 } else if (unlikely(r != 0)) { 930 return r; 931 } 932 933 offset = bo->mem.start << PAGE_SHIFT; 934 /* this should never happen */ 935 if ((offset + size) > adev->mc.visible_vram_size) 936 return -EINVAL; 937 938 return 0; 939 } 940 941 /** 942 * amdgpu_bo_fence - add fence to buffer object 943 * 944 * @bo: buffer object in question 945 * @fence: fence to add 946 * @shared: true if fence should be added shared 947 * 948 */ 949 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 950 bool shared) 951 { 952 struct reservation_object *resv = bo->tbo.resv; 953 954 if (shared) 955 reservation_object_add_shared_fence(resv, fence); 956 else 957 reservation_object_add_excl_fence(resv, fence); 958 } 959 960 /** 961 * amdgpu_bo_gpu_offset - return GPU offset of bo 962 * @bo: amdgpu object for which we query the offset 963 * 964 * Returns current GPU offset of the object. 965 * 966 * Note: object should either be pinned or reserved when calling this 967 * function, it might be useful to add check for this for debugging. 968 */ 969 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 970 { 971 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 972 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && 973 !amdgpu_ttm_is_bound(bo->tbo.ttm)); 974 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 975 !bo->pin_count); 976 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 977 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 978 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 979 980 return bo->tbo.offset; 981 } 982