1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/amdgpu_drm.h> 37 #include <drm/drm_cache.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 #include "amdgpu_amdkfd.h" 41 42 /** 43 * DOC: amdgpu_object 44 * 45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 46 * represents memory used by driver (VRAM, system memory, etc.). The driver 47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 48 * to create/destroy/set buffer object which are then managed by the kernel TTM 49 * memory manager. 50 * The interfaces are also used internally by kernel clients, including gfx, 51 * uvd, etc. for kernel managed allocations used by the GPU. 52 * 53 */ 54 55 /** 56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 57 * 58 * @bo: &amdgpu_bo buffer object 59 * 60 * This function is called when a BO stops being pinned, and updates the 61 * &amdgpu_device pin_size values accordingly. 62 */ 63 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 64 { 65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 66 67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 70 &adev->visible_pin_size); 71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 73 } 74 } 75 76 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 77 { 78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 80 81 if (bo->tbo.pin_count > 0) 82 amdgpu_bo_subtract_pin_size(bo); 83 84 amdgpu_bo_kunmap(bo); 85 86 if (bo->tbo.base.import_attach) 87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 88 drm_gem_object_release(&bo->tbo.base); 89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 90 if (!list_empty(&bo->shadow_list)) { 91 mutex_lock(&adev->shadow_list_lock); 92 list_del_init(&bo->shadow_list); 93 mutex_unlock(&adev->shadow_list_lock); 94 } 95 amdgpu_bo_unref(&bo->parent); 96 97 kfree(bo->metadata); 98 kfree(bo); 99 } 100 101 /** 102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 103 * @bo: buffer object to be checked 104 * 105 * Uses destroy function associated with the object to determine if this is 106 * an &amdgpu_bo. 107 * 108 * Returns: 109 * true if the object belongs to &amdgpu_bo, false if not. 110 */ 111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 112 { 113 if (bo->destroy == &amdgpu_bo_destroy) 114 return true; 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 137 places[c].fpfn = 0; 138 places[c].lpfn = 0; 139 places[c].mem_type = TTM_PL_VRAM; 140 places[c].flags = 0; 141 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 places[c].lpfn = visible_pfn; 144 else 145 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 146 147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 149 c++; 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 places[c].fpfn = 0; 154 places[c].lpfn = 0; 155 places[c].mem_type = TTM_PL_TT; 156 places[c].flags = 0; 157 c++; 158 } 159 160 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 161 places[c].fpfn = 0; 162 places[c].lpfn = 0; 163 places[c].mem_type = TTM_PL_SYSTEM; 164 places[c].flags = 0; 165 c++; 166 } 167 168 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 169 places[c].fpfn = 0; 170 places[c].lpfn = 0; 171 places[c].mem_type = AMDGPU_PL_GDS; 172 places[c].flags = 0; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].mem_type = AMDGPU_PL_GWS; 180 places[c].flags = 0; 181 c++; 182 } 183 184 if (domain & AMDGPU_GEM_DOMAIN_OA) { 185 places[c].fpfn = 0; 186 places[c].lpfn = 0; 187 places[c].mem_type = AMDGPU_PL_OA; 188 places[c].flags = 0; 189 c++; 190 } 191 192 if (!c) { 193 places[c].fpfn = 0; 194 places[c].lpfn = 0; 195 places[c].mem_type = TTM_PL_SYSTEM; 196 places[c].flags = 0; 197 c++; 198 } 199 200 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 201 202 placement->num_placement = c; 203 placement->placement = places; 204 205 placement->num_busy_placement = c; 206 placement->busy_placement = places; 207 } 208 209 /** 210 * amdgpu_bo_create_reserved - create reserved BO for kernel use 211 * 212 * @adev: amdgpu device object 213 * @size: size for the new BO 214 * @align: alignment for the new BO 215 * @domain: where to place it 216 * @bo_ptr: used to initialize BOs in structures 217 * @gpu_addr: GPU addr of the pinned BO 218 * @cpu_addr: optional CPU address mapping 219 * 220 * Allocates and pins a BO for kernel internal use, and returns it still 221 * reserved. 222 * 223 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 224 * 225 * Returns: 226 * 0 on success, negative error code otherwise. 227 */ 228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 229 unsigned long size, int align, 230 u32 domain, struct amdgpu_bo **bo_ptr, 231 u64 *gpu_addr, void **cpu_addr) 232 { 233 struct amdgpu_bo_param bp; 234 bool free = false; 235 int r; 236 237 if (!size) { 238 amdgpu_bo_unref(bo_ptr); 239 return 0; 240 } 241 242 memset(&bp, 0, sizeof(bp)); 243 bp.size = size; 244 bp.byte_align = align; 245 bp.domain = domain; 246 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 247 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 248 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 249 bp.type = ttm_bo_type_kernel; 250 bp.resv = NULL; 251 252 if (!*bo_ptr) { 253 r = amdgpu_bo_create(adev, &bp, bo_ptr); 254 if (r) { 255 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 256 r); 257 return r; 258 } 259 free = true; 260 } 261 262 r = amdgpu_bo_reserve(*bo_ptr, false); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 265 goto error_free; 266 } 267 268 r = amdgpu_bo_pin(*bo_ptr, domain); 269 if (r) { 270 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 271 goto error_unreserve; 272 } 273 274 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 275 if (r) { 276 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 277 goto error_unpin; 278 } 279 280 if (gpu_addr) 281 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 282 283 if (cpu_addr) { 284 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 285 if (r) { 286 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 287 goto error_unpin; 288 } 289 } 290 291 return 0; 292 293 error_unpin: 294 amdgpu_bo_unpin(*bo_ptr); 295 error_unreserve: 296 amdgpu_bo_unreserve(*bo_ptr); 297 298 error_free: 299 if (free) 300 amdgpu_bo_unref(bo_ptr); 301 302 return r; 303 } 304 305 /** 306 * amdgpu_bo_create_kernel - create BO for kernel use 307 * 308 * @adev: amdgpu device object 309 * @size: size for the new BO 310 * @align: alignment for the new BO 311 * @domain: where to place it 312 * @bo_ptr: used to initialize BOs in structures 313 * @gpu_addr: GPU addr of the pinned BO 314 * @cpu_addr: optional CPU address mapping 315 * 316 * Allocates and pins a BO for kernel internal use. 317 * 318 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 319 * 320 * Returns: 321 * 0 on success, negative error code otherwise. 322 */ 323 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 324 unsigned long size, int align, 325 u32 domain, struct amdgpu_bo **bo_ptr, 326 u64 *gpu_addr, void **cpu_addr) 327 { 328 int r; 329 330 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 331 gpu_addr, cpu_addr); 332 333 if (r) 334 return r; 335 336 if (*bo_ptr) 337 amdgpu_bo_unreserve(*bo_ptr); 338 339 return 0; 340 } 341 342 /** 343 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 344 * 345 * @adev: amdgpu device object 346 * @offset: offset of the BO 347 * @size: size of the BO 348 * @domain: where to place it 349 * @bo_ptr: used to initialize BOs in structures 350 * @cpu_addr: optional CPU address mapping 351 * 352 * Creates a kernel BO at a specific offset in the address space of the domain. 353 * 354 * Returns: 355 * 0 on success, negative error code otherwise. 356 */ 357 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 358 uint64_t offset, uint64_t size, uint32_t domain, 359 struct amdgpu_bo **bo_ptr, void **cpu_addr) 360 { 361 struct ttm_operation_ctx ctx = { false, false }; 362 unsigned int i; 363 int r; 364 365 offset &= PAGE_MASK; 366 size = ALIGN(size, PAGE_SIZE); 367 368 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 369 NULL, cpu_addr); 370 if (r) 371 return r; 372 373 if ((*bo_ptr) == NULL) 374 return 0; 375 376 /* 377 * Remove the original mem node and create a new one at the request 378 * position. 379 */ 380 if (cpu_addr) 381 amdgpu_bo_kunmap(*bo_ptr); 382 383 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); 384 385 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 386 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 387 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 388 } 389 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 390 &(*bo_ptr)->tbo.mem, &ctx); 391 if (r) 392 goto error; 393 394 if (cpu_addr) { 395 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 396 if (r) 397 goto error; 398 } 399 400 amdgpu_bo_unreserve(*bo_ptr); 401 return 0; 402 403 error: 404 amdgpu_bo_unreserve(*bo_ptr); 405 amdgpu_bo_unref(bo_ptr); 406 return r; 407 } 408 409 /** 410 * amdgpu_bo_free_kernel - free BO for kernel use 411 * 412 * @bo: amdgpu BO to free 413 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 414 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 415 * 416 * unmaps and unpin a BO for kernel internal use. 417 */ 418 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 419 void **cpu_addr) 420 { 421 if (*bo == NULL) 422 return; 423 424 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 425 if (cpu_addr) 426 amdgpu_bo_kunmap(*bo); 427 428 amdgpu_bo_unpin(*bo); 429 amdgpu_bo_unreserve(*bo); 430 } 431 amdgpu_bo_unref(bo); 432 433 if (gpu_addr) 434 *gpu_addr = 0; 435 436 if (cpu_addr) 437 *cpu_addr = NULL; 438 } 439 440 /* Validate bo size is bit bigger then the request domain */ 441 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 442 unsigned long size, u32 domain) 443 { 444 struct ttm_resource_manager *man = NULL; 445 446 /* 447 * If GTT is part of requested domains the check must succeed to 448 * allow fall back to GTT 449 */ 450 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 451 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 452 453 if (size < (man->size << PAGE_SHIFT)) 454 return true; 455 else 456 goto fail; 457 } 458 459 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 460 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 461 462 if (size < (man->size << PAGE_SHIFT)) 463 return true; 464 else 465 goto fail; 466 } 467 468 469 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 470 return true; 471 472 fail: 473 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 474 man->size << PAGE_SHIFT); 475 return false; 476 } 477 478 bool amdgpu_bo_support_uswc(u64 bo_flags) 479 { 480 481 #ifdef CONFIG_X86_32 482 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 483 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 484 */ 485 return false; 486 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 487 /* Don't try to enable write-combining when it can't work, or things 488 * may be slow 489 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 490 */ 491 492 #ifndef CONFIG_COMPILE_TEST 493 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 494 thanks to write-combining 495 #endif 496 497 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 498 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 499 "better performance thanks to write-combining\n"); 500 return false; 501 #else 502 /* For architectures that don't support WC memory, 503 * mask out the WC flag from the BO 504 */ 505 if (!drm_arch_can_wc_memory()) 506 return false; 507 508 return true; 509 #endif 510 } 511 512 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 513 struct amdgpu_bo_param *bp, 514 struct amdgpu_bo **bo_ptr) 515 { 516 struct ttm_operation_ctx ctx = { 517 .interruptible = (bp->type != ttm_bo_type_kernel), 518 .no_wait_gpu = bp->no_wait_gpu, 519 /* We opt to avoid OOM on system pages allocations */ 520 .gfp_retry_mayfail = true, 521 .allow_res_evict = bp->type != ttm_bo_type_kernel, 522 .resv = bp->resv 523 }; 524 struct amdgpu_bo *bo; 525 unsigned long page_align, size = bp->size; 526 size_t acc_size; 527 int r; 528 529 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 530 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 531 /* GWS and OA don't need any alignment. */ 532 page_align = bp->byte_align; 533 size <<= PAGE_SHIFT; 534 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 535 /* Both size and alignment must be a multiple of 4. */ 536 page_align = ALIGN(bp->byte_align, 4); 537 size = ALIGN(size, 4) << PAGE_SHIFT; 538 } else { 539 /* Memory should be aligned at least to a page size. */ 540 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 541 size = ALIGN(size, PAGE_SIZE); 542 } 543 544 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 545 return -ENOMEM; 546 547 *bo_ptr = NULL; 548 549 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 550 sizeof(struct amdgpu_bo)); 551 552 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 553 if (bo == NULL) 554 return -ENOMEM; 555 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 556 INIT_LIST_HEAD(&bo->shadow_list); 557 bo->vm_bo = NULL; 558 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 559 bp->domain; 560 bo->allowed_domains = bo->preferred_domains; 561 if (bp->type != ttm_bo_type_kernel && 562 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 563 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 564 565 bo->flags = bp->flags; 566 567 if (!amdgpu_bo_support_uswc(bo->flags)) 568 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 569 570 bo->tbo.bdev = &adev->mman.bdev; 571 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 572 AMDGPU_GEM_DOMAIN_GDS)) 573 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 574 else 575 amdgpu_bo_placement_from_domain(bo, bp->domain); 576 if (bp->type == ttm_bo_type_kernel) 577 bo->tbo.priority = 1; 578 579 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 580 &bo->placement, page_align, &ctx, acc_size, 581 NULL, bp->resv, &amdgpu_bo_destroy); 582 if (unlikely(r != 0)) 583 return r; 584 585 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 586 bo->tbo.mem.mem_type == TTM_PL_VRAM && 587 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 588 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 589 ctx.bytes_moved); 590 else 591 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 592 593 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 594 bo->tbo.mem.mem_type == TTM_PL_VRAM) { 595 struct dma_fence *fence; 596 597 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 598 if (unlikely(r)) 599 goto fail_unreserve; 600 601 amdgpu_bo_fence(bo, fence, false); 602 dma_fence_put(bo->tbo.moving); 603 bo->tbo.moving = dma_fence_get(fence); 604 dma_fence_put(fence); 605 } 606 if (!bp->resv) 607 amdgpu_bo_unreserve(bo); 608 *bo_ptr = bo; 609 610 trace_amdgpu_bo_create(bo); 611 612 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 613 if (bp->type == ttm_bo_type_device) 614 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 615 616 return 0; 617 618 fail_unreserve: 619 if (!bp->resv) 620 dma_resv_unlock(bo->tbo.base.resv); 621 amdgpu_bo_unref(&bo); 622 return r; 623 } 624 625 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 626 unsigned long size, 627 struct amdgpu_bo *bo) 628 { 629 struct amdgpu_bo_param bp; 630 int r; 631 632 if (bo->shadow) 633 return 0; 634 635 memset(&bp, 0, sizeof(bp)); 636 bp.size = size; 637 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 638 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 639 AMDGPU_GEM_CREATE_SHADOW; 640 bp.type = ttm_bo_type_kernel; 641 bp.resv = bo->tbo.base.resv; 642 643 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 644 if (!r) { 645 bo->shadow->parent = amdgpu_bo_ref(bo); 646 mutex_lock(&adev->shadow_list_lock); 647 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 648 mutex_unlock(&adev->shadow_list_lock); 649 } 650 651 return r; 652 } 653 654 /** 655 * amdgpu_bo_create - create an &amdgpu_bo buffer object 656 * @adev: amdgpu device object 657 * @bp: parameters to be used for the buffer object 658 * @bo_ptr: pointer to the buffer object pointer 659 * 660 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 661 * shadow object. 662 * Shadow object is used to backup the original buffer object, and is always 663 * in GTT. 664 * 665 * Returns: 666 * 0 for success or a negative error code on failure. 667 */ 668 int amdgpu_bo_create(struct amdgpu_device *adev, 669 struct amdgpu_bo_param *bp, 670 struct amdgpu_bo **bo_ptr) 671 { 672 u64 flags = bp->flags; 673 int r; 674 675 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 676 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 677 if (r) 678 return r; 679 680 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 681 if (!bp->resv) 682 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 683 NULL)); 684 685 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 686 687 if (!bp->resv) 688 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 689 690 if (r) 691 amdgpu_bo_unref(bo_ptr); 692 } 693 694 return r; 695 } 696 697 /** 698 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 699 * @bo: pointer to the buffer object 700 * 701 * Sets placement according to domain; and changes placement and caching 702 * policy of the buffer object according to the placement. 703 * This is used for validating shadow bos. It calls ttm_bo_validate() to 704 * make sure the buffer is resident where it needs to be. 705 * 706 * Returns: 707 * 0 for success or a negative error code on failure. 708 */ 709 int amdgpu_bo_validate(struct amdgpu_bo *bo) 710 { 711 struct ttm_operation_ctx ctx = { false, false }; 712 uint32_t domain; 713 int r; 714 715 if (bo->tbo.pin_count) 716 return 0; 717 718 domain = bo->preferred_domains; 719 720 retry: 721 amdgpu_bo_placement_from_domain(bo, domain); 722 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 723 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 724 domain = bo->allowed_domains; 725 goto retry; 726 } 727 728 return r; 729 } 730 731 /** 732 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 733 * 734 * @shadow: &amdgpu_bo shadow to be restored 735 * @fence: dma_fence associated with the operation 736 * 737 * Copies a buffer object's shadow content back to the object. 738 * This is used for recovering a buffer from its shadow in case of a gpu 739 * reset where vram context may be lost. 740 * 741 * Returns: 742 * 0 for success or a negative error code on failure. 743 */ 744 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 745 746 { 747 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 748 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 749 uint64_t shadow_addr, parent_addr; 750 751 shadow_addr = amdgpu_bo_gpu_offset(shadow); 752 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 753 754 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 755 amdgpu_bo_size(shadow), NULL, fence, 756 true, false, false); 757 } 758 759 /** 760 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 761 * @bo: &amdgpu_bo buffer object to be mapped 762 * @ptr: kernel virtual address to be returned 763 * 764 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 765 * amdgpu_bo_kptr() to get the kernel virtual address. 766 * 767 * Returns: 768 * 0 for success or a negative error code on failure. 769 */ 770 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 771 { 772 void *kptr; 773 long r; 774 775 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 776 return -EPERM; 777 778 kptr = amdgpu_bo_kptr(bo); 779 if (kptr) { 780 if (ptr) 781 *ptr = kptr; 782 return 0; 783 } 784 785 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 786 MAX_SCHEDULE_TIMEOUT); 787 if (r < 0) 788 return r; 789 790 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 791 if (r) 792 return r; 793 794 if (ptr) 795 *ptr = amdgpu_bo_kptr(bo); 796 797 return 0; 798 } 799 800 /** 801 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 802 * @bo: &amdgpu_bo buffer object 803 * 804 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 805 * 806 * Returns: 807 * the virtual address of a buffer object area. 808 */ 809 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 810 { 811 bool is_iomem; 812 813 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 814 } 815 816 /** 817 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 818 * @bo: &amdgpu_bo buffer object to be unmapped 819 * 820 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 821 */ 822 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 823 { 824 if (bo->kmap.bo) 825 ttm_bo_kunmap(&bo->kmap); 826 } 827 828 /** 829 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 830 * @bo: &amdgpu_bo buffer object 831 * 832 * References the contained &ttm_buffer_object. 833 * 834 * Returns: 835 * a refcounted pointer to the &amdgpu_bo buffer object. 836 */ 837 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 838 { 839 if (bo == NULL) 840 return NULL; 841 842 ttm_bo_get(&bo->tbo); 843 return bo; 844 } 845 846 /** 847 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 848 * @bo: &amdgpu_bo buffer object 849 * 850 * Unreferences the contained &ttm_buffer_object and clear the pointer 851 */ 852 void amdgpu_bo_unref(struct amdgpu_bo **bo) 853 { 854 struct ttm_buffer_object *tbo; 855 856 if ((*bo) == NULL) 857 return; 858 859 tbo = &((*bo)->tbo); 860 ttm_bo_put(tbo); 861 *bo = NULL; 862 } 863 864 /** 865 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 866 * @bo: &amdgpu_bo buffer object to be pinned 867 * @domain: domain to be pinned to 868 * @min_offset: the start of requested address range 869 * @max_offset: the end of requested address range 870 * 871 * Pins the buffer object according to requested domain and address range. If 872 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 873 * pin_count and pin_size accordingly. 874 * 875 * Pinning means to lock pages in memory along with keeping them at a fixed 876 * offset. It is required when a buffer can not be moved, for example, when 877 * a display buffer is being scanned out. 878 * 879 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 880 * where to pin a buffer if there are specific restrictions on where a buffer 881 * must be located. 882 * 883 * Returns: 884 * 0 for success or a negative error code on failure. 885 */ 886 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 887 u64 min_offset, u64 max_offset) 888 { 889 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 890 struct ttm_operation_ctx ctx = { false, false }; 891 int r, i; 892 893 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 894 return -EPERM; 895 896 if (WARN_ON_ONCE(min_offset > max_offset)) 897 return -EINVAL; 898 899 /* A shared bo cannot be migrated to VRAM */ 900 if (bo->prime_shared_count) { 901 if (domain & AMDGPU_GEM_DOMAIN_GTT) 902 domain = AMDGPU_GEM_DOMAIN_GTT; 903 else 904 return -EINVAL; 905 } 906 907 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 908 * See function amdgpu_display_supported_domains() 909 */ 910 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 911 912 if (bo->tbo.pin_count) { 913 uint32_t mem_type = bo->tbo.mem.mem_type; 914 915 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 916 return -EINVAL; 917 918 ttm_bo_pin(&bo->tbo); 919 920 if (max_offset != 0) { 921 u64 domain_start = amdgpu_ttm_domain_start(adev, 922 mem_type); 923 WARN_ON_ONCE(max_offset < 924 (amdgpu_bo_gpu_offset(bo) - domain_start)); 925 } 926 927 return 0; 928 } 929 930 if (bo->tbo.base.import_attach) 931 dma_buf_pin(bo->tbo.base.import_attach); 932 933 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 934 /* force to pin into visible video ram */ 935 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 936 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 937 amdgpu_bo_placement_from_domain(bo, domain); 938 for (i = 0; i < bo->placement.num_placement; i++) { 939 unsigned fpfn, lpfn; 940 941 fpfn = min_offset >> PAGE_SHIFT; 942 lpfn = max_offset >> PAGE_SHIFT; 943 944 if (fpfn > bo->placements[i].fpfn) 945 bo->placements[i].fpfn = fpfn; 946 if (!bo->placements[i].lpfn || 947 (lpfn && lpfn < bo->placements[i].lpfn)) 948 bo->placements[i].lpfn = lpfn; 949 } 950 951 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 952 if (unlikely(r)) { 953 dev_err(adev->dev, "%p pin failed\n", bo); 954 goto error; 955 } 956 957 ttm_bo_pin(&bo->tbo); 958 959 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 960 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 961 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 962 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 963 &adev->visible_pin_size); 964 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 965 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 966 } 967 968 error: 969 return r; 970 } 971 972 /** 973 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 974 * @bo: &amdgpu_bo buffer object to be pinned 975 * @domain: domain to be pinned to 976 * 977 * A simple wrapper to amdgpu_bo_pin_restricted(). 978 * Provides a simpler API for buffers that do not have any strict restrictions 979 * on where a buffer must be located. 980 * 981 * Returns: 982 * 0 for success or a negative error code on failure. 983 */ 984 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 985 { 986 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 987 } 988 989 /** 990 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 991 * @bo: &amdgpu_bo buffer object to be unpinned 992 * 993 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 994 * Changes placement and pin size accordingly. 995 * 996 * Returns: 997 * 0 for success or a negative error code on failure. 998 */ 999 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1000 { 1001 ttm_bo_unpin(&bo->tbo); 1002 if (bo->tbo.pin_count) 1003 return; 1004 1005 amdgpu_bo_subtract_pin_size(bo); 1006 1007 if (bo->tbo.base.import_attach) 1008 dma_buf_unpin(bo->tbo.base.import_attach); 1009 } 1010 1011 /** 1012 * amdgpu_bo_evict_vram - evict VRAM buffers 1013 * @adev: amdgpu device object 1014 * 1015 * Evicts all VRAM buffers on the lru list of the memory type. 1016 * Mainly used for evicting vram at suspend time. 1017 * 1018 * Returns: 1019 * 0 for success or a negative error code on failure. 1020 */ 1021 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1022 { 1023 struct ttm_resource_manager *man; 1024 1025 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1026 #ifndef CONFIG_HIBERNATION 1027 if (adev->flags & AMD_IS_APU) { 1028 /* Useless to evict on IGP chips */ 1029 return 0; 1030 } 1031 #endif 1032 1033 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1034 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 1035 } 1036 1037 static const char *amdgpu_vram_names[] = { 1038 "UNKNOWN", 1039 "GDDR1", 1040 "DDR2", 1041 "GDDR3", 1042 "GDDR4", 1043 "GDDR5", 1044 "HBM", 1045 "DDR3", 1046 "DDR4", 1047 "GDDR6", 1048 }; 1049 1050 /** 1051 * amdgpu_bo_init - initialize memory manager 1052 * @adev: amdgpu device object 1053 * 1054 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1055 * 1056 * Returns: 1057 * 0 for success or a negative error code on failure. 1058 */ 1059 int amdgpu_bo_init(struct amdgpu_device *adev) 1060 { 1061 /* reserve PAT memory space to WC for VRAM */ 1062 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1063 adev->gmc.aper_size); 1064 1065 /* Add an MTRR for the VRAM */ 1066 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1067 adev->gmc.aper_size); 1068 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1069 adev->gmc.mc_vram_size >> 20, 1070 (unsigned long long)adev->gmc.aper_size >> 20); 1071 DRM_INFO("RAM width %dbits %s\n", 1072 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1073 return amdgpu_ttm_init(adev); 1074 } 1075 1076 /** 1077 * amdgpu_bo_late_init - late init 1078 * @adev: amdgpu device object 1079 * 1080 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1081 * initialization. 1082 * 1083 * Returns: 1084 * 0 for success or a negative error code on failure. 1085 */ 1086 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1087 { 1088 amdgpu_ttm_late_init(adev); 1089 1090 return 0; 1091 } 1092 1093 /** 1094 * amdgpu_bo_fini - tear down memory manager 1095 * @adev: amdgpu device object 1096 * 1097 * Reverses amdgpu_bo_init() to tear down memory manager. 1098 */ 1099 void amdgpu_bo_fini(struct amdgpu_device *adev) 1100 { 1101 amdgpu_ttm_fini(adev); 1102 arch_phys_wc_del(adev->gmc.vram_mtrr); 1103 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1104 } 1105 1106 /** 1107 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1108 * @bo: &amdgpu_bo buffer object 1109 * @vma: vma as input from the fbdev mmap method 1110 * 1111 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1112 * 1113 * Returns: 1114 * 0 for success or a negative error code on failure. 1115 */ 1116 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1117 struct vm_area_struct *vma) 1118 { 1119 if (vma->vm_pgoff != 0) 1120 return -EACCES; 1121 1122 return ttm_bo_mmap_obj(vma, &bo->tbo); 1123 } 1124 1125 /** 1126 * amdgpu_bo_set_tiling_flags - set tiling flags 1127 * @bo: &amdgpu_bo buffer object 1128 * @tiling_flags: new flags 1129 * 1130 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1131 * kernel driver to set the tiling flags on a buffer. 1132 * 1133 * Returns: 1134 * 0 for success or a negative error code on failure. 1135 */ 1136 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1137 { 1138 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1139 1140 if (adev->family <= AMDGPU_FAMILY_CZ && 1141 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1142 return -EINVAL; 1143 1144 bo->tiling_flags = tiling_flags; 1145 return 0; 1146 } 1147 1148 /** 1149 * amdgpu_bo_get_tiling_flags - get tiling flags 1150 * @bo: &amdgpu_bo buffer object 1151 * @tiling_flags: returned flags 1152 * 1153 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1154 * set the tiling flags on a buffer. 1155 */ 1156 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1157 { 1158 dma_resv_assert_held(bo->tbo.base.resv); 1159 1160 if (tiling_flags) 1161 *tiling_flags = bo->tiling_flags; 1162 } 1163 1164 /** 1165 * amdgpu_bo_set_metadata - set metadata 1166 * @bo: &amdgpu_bo buffer object 1167 * @metadata: new metadata 1168 * @metadata_size: size of the new metadata 1169 * @flags: flags of the new metadata 1170 * 1171 * Sets buffer object's metadata, its size and flags. 1172 * Used via GEM ioctl. 1173 * 1174 * Returns: 1175 * 0 for success or a negative error code on failure. 1176 */ 1177 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1178 uint32_t metadata_size, uint64_t flags) 1179 { 1180 void *buffer; 1181 1182 if (!metadata_size) { 1183 if (bo->metadata_size) { 1184 kfree(bo->metadata); 1185 bo->metadata = NULL; 1186 bo->metadata_size = 0; 1187 } 1188 return 0; 1189 } 1190 1191 if (metadata == NULL) 1192 return -EINVAL; 1193 1194 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1195 if (buffer == NULL) 1196 return -ENOMEM; 1197 1198 kfree(bo->metadata); 1199 bo->metadata_flags = flags; 1200 bo->metadata = buffer; 1201 bo->metadata_size = metadata_size; 1202 1203 return 0; 1204 } 1205 1206 /** 1207 * amdgpu_bo_get_metadata - get metadata 1208 * @bo: &amdgpu_bo buffer object 1209 * @buffer: returned metadata 1210 * @buffer_size: size of the buffer 1211 * @metadata_size: size of the returned metadata 1212 * @flags: flags of the returned metadata 1213 * 1214 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1215 * less than metadata_size. 1216 * Used via GEM ioctl. 1217 * 1218 * Returns: 1219 * 0 for success or a negative error code on failure. 1220 */ 1221 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1222 size_t buffer_size, uint32_t *metadata_size, 1223 uint64_t *flags) 1224 { 1225 if (!buffer && !metadata_size) 1226 return -EINVAL; 1227 1228 if (buffer) { 1229 if (buffer_size < bo->metadata_size) 1230 return -EINVAL; 1231 1232 if (bo->metadata_size) 1233 memcpy(buffer, bo->metadata, bo->metadata_size); 1234 } 1235 1236 if (metadata_size) 1237 *metadata_size = bo->metadata_size; 1238 if (flags) 1239 *flags = bo->metadata_flags; 1240 1241 return 0; 1242 } 1243 1244 /** 1245 * amdgpu_bo_move_notify - notification about a memory move 1246 * @bo: pointer to a buffer object 1247 * @evict: if this move is evicting the buffer from the graphics address space 1248 * @new_mem: new information of the bufer object 1249 * 1250 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1251 * bookkeeping. 1252 * TTM driver callback which is called when ttm moves a buffer. 1253 */ 1254 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1255 bool evict, 1256 struct ttm_resource *new_mem) 1257 { 1258 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1259 struct amdgpu_bo *abo; 1260 struct ttm_resource *old_mem = &bo->mem; 1261 1262 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1263 return; 1264 1265 abo = ttm_to_amdgpu_bo(bo); 1266 amdgpu_vm_bo_invalidate(adev, abo, evict); 1267 1268 amdgpu_bo_kunmap(abo); 1269 1270 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1271 bo->mem.mem_type != TTM_PL_SYSTEM) 1272 dma_buf_move_notify(abo->tbo.base.dma_buf); 1273 1274 /* remember the eviction */ 1275 if (evict) 1276 atomic64_inc(&adev->num_evictions); 1277 1278 /* update statistics */ 1279 if (!new_mem) 1280 return; 1281 1282 /* move_notify is called before move happens */ 1283 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1284 } 1285 1286 /** 1287 * amdgpu_bo_release_notify - notification about a BO being released 1288 * @bo: pointer to a buffer object 1289 * 1290 * Wipes VRAM buffers whose contents should not be leaked before the 1291 * memory is released. 1292 */ 1293 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1294 { 1295 struct dma_fence *fence = NULL; 1296 struct amdgpu_bo *abo; 1297 int r; 1298 1299 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1300 return; 1301 1302 abo = ttm_to_amdgpu_bo(bo); 1303 1304 if (abo->kfd_bo) 1305 amdgpu_amdkfd_unreserve_memory_limit(abo); 1306 1307 /* We only remove the fence if the resv has individualized. */ 1308 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1309 && bo->base.resv != &bo->base._resv); 1310 if (bo->base.resv == &bo->base._resv) 1311 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1312 1313 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1314 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1315 return; 1316 1317 dma_resv_lock(bo->base.resv, NULL); 1318 1319 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1320 if (!WARN_ON(r)) { 1321 amdgpu_bo_fence(abo, fence, false); 1322 dma_fence_put(fence); 1323 } 1324 1325 dma_resv_unlock(bo->base.resv); 1326 } 1327 1328 /** 1329 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1330 * @bo: pointer to a buffer object 1331 * 1332 * Notifies the driver we are taking a fault on this BO and have reserved it, 1333 * also performs bookkeeping. 1334 * TTM driver callback for dealing with vm faults. 1335 * 1336 * Returns: 1337 * 0 for success or a negative error code on failure. 1338 */ 1339 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1340 { 1341 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1342 struct ttm_operation_ctx ctx = { false, false }; 1343 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1344 unsigned long offset, size; 1345 int r; 1346 1347 /* Remember that this BO was accessed by the CPU */ 1348 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1349 1350 if (bo->mem.mem_type != TTM_PL_VRAM) 1351 return 0; 1352 1353 size = bo->mem.num_pages << PAGE_SHIFT; 1354 offset = bo->mem.start << PAGE_SHIFT; 1355 if ((offset + size) <= adev->gmc.visible_vram_size) 1356 return 0; 1357 1358 /* Can't move a pinned BO to visible VRAM */ 1359 if (abo->tbo.pin_count > 0) 1360 return VM_FAULT_SIGBUS; 1361 1362 /* hurrah the memory is not visible ! */ 1363 atomic64_inc(&adev->num_vram_cpu_page_faults); 1364 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1365 AMDGPU_GEM_DOMAIN_GTT); 1366 1367 /* Avoid costly evictions; only set GTT as a busy placement */ 1368 abo->placement.num_busy_placement = 1; 1369 abo->placement.busy_placement = &abo->placements[1]; 1370 1371 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1372 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1373 return VM_FAULT_NOPAGE; 1374 else if (unlikely(r)) 1375 return VM_FAULT_SIGBUS; 1376 1377 offset = bo->mem.start << PAGE_SHIFT; 1378 /* this should never happen */ 1379 if (bo->mem.mem_type == TTM_PL_VRAM && 1380 (offset + size) > adev->gmc.visible_vram_size) 1381 return VM_FAULT_SIGBUS; 1382 1383 ttm_bo_move_to_lru_tail_unlocked(bo); 1384 return 0; 1385 } 1386 1387 /** 1388 * amdgpu_bo_fence - add fence to buffer object 1389 * 1390 * @bo: buffer object in question 1391 * @fence: fence to add 1392 * @shared: true if fence should be added shared 1393 * 1394 */ 1395 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1396 bool shared) 1397 { 1398 struct dma_resv *resv = bo->tbo.base.resv; 1399 1400 if (shared) 1401 dma_resv_add_shared_fence(resv, fence); 1402 else 1403 dma_resv_add_excl_fence(resv, fence); 1404 } 1405 1406 /** 1407 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1408 * 1409 * @adev: amdgpu device pointer 1410 * @resv: reservation object to sync to 1411 * @sync_mode: synchronization mode 1412 * @owner: fence owner 1413 * @intr: Whether the wait is interruptible 1414 * 1415 * Extract the fences from the reservation object and waits for them to finish. 1416 * 1417 * Returns: 1418 * 0 on success, errno otherwise. 1419 */ 1420 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1421 enum amdgpu_sync_mode sync_mode, void *owner, 1422 bool intr) 1423 { 1424 struct amdgpu_sync sync; 1425 int r; 1426 1427 amdgpu_sync_create(&sync); 1428 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1429 r = amdgpu_sync_wait(&sync, intr); 1430 amdgpu_sync_free(&sync); 1431 return r; 1432 } 1433 1434 /** 1435 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1436 * @bo: buffer object to wait for 1437 * @owner: fence owner 1438 * @intr: Whether the wait is interruptible 1439 * 1440 * Wrapper to wait for fences in a BO. 1441 * Returns: 1442 * 0 on success, errno otherwise. 1443 */ 1444 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1445 { 1446 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1447 1448 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1449 AMDGPU_SYNC_NE_OWNER, owner, intr); 1450 } 1451 1452 /** 1453 * amdgpu_bo_gpu_offset - return GPU offset of bo 1454 * @bo: amdgpu object for which we query the offset 1455 * 1456 * Note: object should either be pinned or reserved when calling this 1457 * function, it might be useful to add check for this for debugging. 1458 * 1459 * Returns: 1460 * current GPU offset of the object. 1461 */ 1462 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1463 { 1464 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1465 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1466 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1467 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1468 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1469 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1470 1471 return amdgpu_bo_gpu_offset_no_check(bo); 1472 } 1473 1474 /** 1475 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1476 * @bo: amdgpu object for which we query the offset 1477 * 1478 * Returns: 1479 * current GPU offset of the object without raising warnings. 1480 */ 1481 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1482 { 1483 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1484 uint64_t offset; 1485 1486 offset = (bo->tbo.mem.start << PAGE_SHIFT) + 1487 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 1488 1489 return amdgpu_gmc_sign_extend(offset); 1490 } 1491 1492 /** 1493 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1494 * @adev: amdgpu device object 1495 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1496 * 1497 * Returns: 1498 * Which of the allowed domains is preferred for pinning the BO for scanout. 1499 */ 1500 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1501 uint32_t domain) 1502 { 1503 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1504 domain = AMDGPU_GEM_DOMAIN_VRAM; 1505 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1506 domain = AMDGPU_GEM_DOMAIN_GTT; 1507 } 1508 return domain; 1509 } 1510