1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * DOC: amdgpu_object 43 * 44 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 45 * represents memory used by driver (VRAM, system memory, etc.). The driver 46 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 47 * to create/destroy/set buffer object which are then managed by the kernel TTM 48 * memory manager. 49 * The interfaces are also used internally by kernel clients, including gfx, 50 * uvd, etc. for kernel managed allocations used by the GPU. 51 * 52 */ 53 54 /** 55 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 56 * 57 * @bo: &amdgpu_bo buffer object 58 * 59 * This function is called when a BO stops being pinned, and updates the 60 * &amdgpu_device pin_size values accordingly. 61 */ 62 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 63 { 64 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 65 66 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 67 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 68 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 69 &adev->visible_pin_size); 70 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 71 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 72 } 73 } 74 75 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 76 { 77 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 78 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 79 80 if (bo->pin_count > 0) 81 amdgpu_bo_subtract_pin_size(bo); 82 83 amdgpu_bo_kunmap(bo); 84 85 if (bo->tbo.base.import_attach) 86 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 87 drm_gem_object_release(&bo->tbo.base); 88 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 89 if (!list_empty(&bo->shadow_list)) { 90 mutex_lock(&adev->shadow_list_lock); 91 list_del_init(&bo->shadow_list); 92 mutex_unlock(&adev->shadow_list_lock); 93 } 94 amdgpu_bo_unref(&bo->parent); 95 96 kfree(bo->metadata); 97 kfree(bo); 98 } 99 100 /** 101 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 102 * @bo: buffer object to be checked 103 * 104 * Uses destroy function associated with the object to determine if this is 105 * an &amdgpu_bo. 106 * 107 * Returns: 108 * true if the object belongs to &amdgpu_bo, false if not. 109 */ 110 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 111 { 112 if (bo->destroy == &amdgpu_bo_destroy) 113 return true; 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 136 places[c].fpfn = 0; 137 places[c].lpfn = 0; 138 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 139 TTM_PL_FLAG_VRAM; 140 141 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 142 places[c].lpfn = visible_pfn; 143 else 144 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 145 146 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 147 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 148 c++; 149 } 150 151 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 152 places[c].fpfn = 0; 153 places[c].lpfn = 0; 154 places[c].flags = TTM_PL_FLAG_TT; 155 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 156 places[c].flags |= TTM_PL_FLAG_WC | 157 TTM_PL_FLAG_UNCACHED; 158 else 159 places[c].flags |= TTM_PL_FLAG_CACHED; 160 c++; 161 } 162 163 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 164 places[c].fpfn = 0; 165 places[c].lpfn = 0; 166 places[c].flags = TTM_PL_FLAG_SYSTEM; 167 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 168 places[c].flags |= TTM_PL_FLAG_WC | 169 TTM_PL_FLAG_UNCACHED; 170 else 171 places[c].flags |= TTM_PL_FLAG_CACHED; 172 c++; 173 } 174 175 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 176 places[c].fpfn = 0; 177 places[c].lpfn = 0; 178 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 179 c++; 180 } 181 182 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 183 places[c].fpfn = 0; 184 places[c].lpfn = 0; 185 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 186 c++; 187 } 188 189 if (domain & AMDGPU_GEM_DOMAIN_OA) { 190 places[c].fpfn = 0; 191 places[c].lpfn = 0; 192 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 193 c++; 194 } 195 196 if (!c) { 197 places[c].fpfn = 0; 198 places[c].lpfn = 0; 199 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 200 c++; 201 } 202 203 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 204 205 placement->num_placement = c; 206 placement->placement = places; 207 208 placement->num_busy_placement = c; 209 placement->busy_placement = places; 210 } 211 212 /** 213 * amdgpu_bo_create_reserved - create reserved BO for kernel use 214 * 215 * @adev: amdgpu device object 216 * @size: size for the new BO 217 * @align: alignment for the new BO 218 * @domain: where to place it 219 * @bo_ptr: used to initialize BOs in structures 220 * @gpu_addr: GPU addr of the pinned BO 221 * @cpu_addr: optional CPU address mapping 222 * 223 * Allocates and pins a BO for kernel internal use, and returns it still 224 * reserved. 225 * 226 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 227 * 228 * Returns: 229 * 0 on success, negative error code otherwise. 230 */ 231 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 232 unsigned long size, int align, 233 u32 domain, struct amdgpu_bo **bo_ptr, 234 u64 *gpu_addr, void **cpu_addr) 235 { 236 struct amdgpu_bo_param bp; 237 bool free = false; 238 int r; 239 240 if (!size) { 241 amdgpu_bo_unref(bo_ptr); 242 return 0; 243 } 244 245 memset(&bp, 0, sizeof(bp)); 246 bp.size = size; 247 bp.byte_align = align; 248 bp.domain = domain; 249 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 250 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 251 bp.type = ttm_bo_type_kernel; 252 bp.resv = NULL; 253 254 if (!*bo_ptr) { 255 r = amdgpu_bo_create(adev, &bp, bo_ptr); 256 if (r) { 257 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 258 r); 259 return r; 260 } 261 free = true; 262 } 263 264 r = amdgpu_bo_reserve(*bo_ptr, false); 265 if (r) { 266 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 267 goto error_free; 268 } 269 270 r = amdgpu_bo_pin(*bo_ptr, domain); 271 if (r) { 272 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 273 goto error_unreserve; 274 } 275 276 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 277 if (r) { 278 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 279 goto error_unpin; 280 } 281 282 if (gpu_addr) 283 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 284 285 if (cpu_addr) { 286 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 287 if (r) { 288 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 289 goto error_unpin; 290 } 291 } 292 293 return 0; 294 295 error_unpin: 296 amdgpu_bo_unpin(*bo_ptr); 297 error_unreserve: 298 amdgpu_bo_unreserve(*bo_ptr); 299 300 error_free: 301 if (free) 302 amdgpu_bo_unref(bo_ptr); 303 304 return r; 305 } 306 307 /** 308 * amdgpu_bo_create_kernel - create BO for kernel use 309 * 310 * @adev: amdgpu device object 311 * @size: size for the new BO 312 * @align: alignment for the new BO 313 * @domain: where to place it 314 * @bo_ptr: used to initialize BOs in structures 315 * @gpu_addr: GPU addr of the pinned BO 316 * @cpu_addr: optional CPU address mapping 317 * 318 * Allocates and pins a BO for kernel internal use. 319 * 320 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 321 * 322 * Returns: 323 * 0 on success, negative error code otherwise. 324 */ 325 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 326 unsigned long size, int align, 327 u32 domain, struct amdgpu_bo **bo_ptr, 328 u64 *gpu_addr, void **cpu_addr) 329 { 330 int r; 331 332 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 333 gpu_addr, cpu_addr); 334 335 if (r) 336 return r; 337 338 if (*bo_ptr) 339 amdgpu_bo_unreserve(*bo_ptr); 340 341 return 0; 342 } 343 344 /** 345 * amdgpu_bo_free_kernel - free BO for kernel use 346 * 347 * @bo: amdgpu BO to free 348 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 349 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 350 * 351 * unmaps and unpin a BO for kernel internal use. 352 */ 353 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 354 void **cpu_addr) 355 { 356 if (*bo == NULL) 357 return; 358 359 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 360 if (cpu_addr) 361 amdgpu_bo_kunmap(*bo); 362 363 amdgpu_bo_unpin(*bo); 364 amdgpu_bo_unreserve(*bo); 365 } 366 amdgpu_bo_unref(bo); 367 368 if (gpu_addr) 369 *gpu_addr = 0; 370 371 if (cpu_addr) 372 *cpu_addr = NULL; 373 } 374 375 /* Validate bo size is bit bigger then the request domain */ 376 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 377 unsigned long size, u32 domain) 378 { 379 struct ttm_mem_type_manager *man = NULL; 380 381 /* 382 * If GTT is part of requested domains the check must succeed to 383 * allow fall back to GTT 384 */ 385 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 386 man = &adev->mman.bdev.man[TTM_PL_TT]; 387 388 if (size < (man->size << PAGE_SHIFT)) 389 return true; 390 else 391 goto fail; 392 } 393 394 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 395 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 396 397 if (size < (man->size << PAGE_SHIFT)) 398 return true; 399 else 400 goto fail; 401 } 402 403 404 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 405 return true; 406 407 fail: 408 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 409 man->size << PAGE_SHIFT); 410 return false; 411 } 412 413 bool amdgpu_bo_support_uswc(u64 bo_flags) 414 { 415 416 #ifdef CONFIG_X86_32 417 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 418 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 419 */ 420 return false; 421 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 422 /* Don't try to enable write-combining when it can't work, or things 423 * may be slow 424 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 425 */ 426 427 #ifndef CONFIG_COMPILE_TEST 428 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 429 thanks to write-combining 430 #endif 431 432 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 433 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 434 "better performance thanks to write-combining\n"); 435 return false; 436 #else 437 /* For architectures that don't support WC memory, 438 * mask out the WC flag from the BO 439 */ 440 if (!drm_arch_can_wc_memory()) 441 return false; 442 443 return true; 444 #endif 445 } 446 447 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 448 struct amdgpu_bo_param *bp, 449 struct amdgpu_bo **bo_ptr) 450 { 451 struct ttm_operation_ctx ctx = { 452 .interruptible = (bp->type != ttm_bo_type_kernel), 453 .no_wait_gpu = false, 454 .resv = bp->resv, 455 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT 456 }; 457 struct amdgpu_bo *bo; 458 unsigned long page_align, size = bp->size; 459 size_t acc_size; 460 int r; 461 462 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 463 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 464 /* GWS and OA don't need any alignment. */ 465 page_align = bp->byte_align; 466 size <<= PAGE_SHIFT; 467 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 468 /* Both size and alignment must be a multiple of 4. */ 469 page_align = ALIGN(bp->byte_align, 4); 470 size = ALIGN(size, 4) << PAGE_SHIFT; 471 } else { 472 /* Memory should be aligned at least to a page size. */ 473 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 474 size = ALIGN(size, PAGE_SIZE); 475 } 476 477 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 478 return -ENOMEM; 479 480 *bo_ptr = NULL; 481 482 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 483 sizeof(struct amdgpu_bo)); 484 485 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 486 if (bo == NULL) 487 return -ENOMEM; 488 drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size); 489 INIT_LIST_HEAD(&bo->shadow_list); 490 bo->vm_bo = NULL; 491 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 492 bp->domain; 493 bo->allowed_domains = bo->preferred_domains; 494 if (bp->type != ttm_bo_type_kernel && 495 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 496 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 497 498 bo->flags = bp->flags; 499 500 if (!amdgpu_bo_support_uswc(bo->flags)) 501 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 502 503 bo->tbo.bdev = &adev->mman.bdev; 504 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 505 AMDGPU_GEM_DOMAIN_GDS)) 506 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 507 else 508 amdgpu_bo_placement_from_domain(bo, bp->domain); 509 if (bp->type == ttm_bo_type_kernel) 510 bo->tbo.priority = 1; 511 512 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 513 &bo->placement, page_align, &ctx, acc_size, 514 NULL, bp->resv, &amdgpu_bo_destroy); 515 if (unlikely(r != 0)) 516 return r; 517 518 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 519 bo->tbo.mem.mem_type == TTM_PL_VRAM && 520 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 521 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 522 ctx.bytes_moved); 523 else 524 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 525 526 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 527 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 528 struct dma_fence *fence; 529 530 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 531 if (unlikely(r)) 532 goto fail_unreserve; 533 534 amdgpu_bo_fence(bo, fence, false); 535 dma_fence_put(bo->tbo.moving); 536 bo->tbo.moving = dma_fence_get(fence); 537 dma_fence_put(fence); 538 } 539 if (!bp->resv) 540 amdgpu_bo_unreserve(bo); 541 *bo_ptr = bo; 542 543 trace_amdgpu_bo_create(bo); 544 545 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 546 if (bp->type == ttm_bo_type_device) 547 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 548 549 return 0; 550 551 fail_unreserve: 552 if (!bp->resv) 553 reservation_object_unlock(bo->tbo.base.resv); 554 amdgpu_bo_unref(&bo); 555 return r; 556 } 557 558 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 559 unsigned long size, 560 struct amdgpu_bo *bo) 561 { 562 struct amdgpu_bo_param bp; 563 int r; 564 565 if (bo->shadow) 566 return 0; 567 568 memset(&bp, 0, sizeof(bp)); 569 bp.size = size; 570 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 571 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 572 AMDGPU_GEM_CREATE_SHADOW; 573 bp.type = ttm_bo_type_kernel; 574 bp.resv = bo->tbo.base.resv; 575 576 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 577 if (!r) { 578 bo->shadow->parent = amdgpu_bo_ref(bo); 579 mutex_lock(&adev->shadow_list_lock); 580 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 581 mutex_unlock(&adev->shadow_list_lock); 582 } 583 584 return r; 585 } 586 587 /** 588 * amdgpu_bo_create - create an &amdgpu_bo buffer object 589 * @adev: amdgpu device object 590 * @bp: parameters to be used for the buffer object 591 * @bo_ptr: pointer to the buffer object pointer 592 * 593 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 594 * shadow object. 595 * Shadow object is used to backup the original buffer object, and is always 596 * in GTT. 597 * 598 * Returns: 599 * 0 for success or a negative error code on failure. 600 */ 601 int amdgpu_bo_create(struct amdgpu_device *adev, 602 struct amdgpu_bo_param *bp, 603 struct amdgpu_bo **bo_ptr) 604 { 605 u64 flags = bp->flags; 606 int r; 607 608 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 609 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 610 if (r) 611 return r; 612 613 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 614 if (!bp->resv) 615 WARN_ON(reservation_object_lock((*bo_ptr)->tbo.base.resv, 616 NULL)); 617 618 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 619 620 if (!bp->resv) 621 reservation_object_unlock((*bo_ptr)->tbo.base.resv); 622 623 if (r) 624 amdgpu_bo_unref(bo_ptr); 625 } 626 627 return r; 628 } 629 630 /** 631 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 632 * @bo: pointer to the buffer object 633 * 634 * Sets placement according to domain; and changes placement and caching 635 * policy of the buffer object according to the placement. 636 * This is used for validating shadow bos. It calls ttm_bo_validate() to 637 * make sure the buffer is resident where it needs to be. 638 * 639 * Returns: 640 * 0 for success or a negative error code on failure. 641 */ 642 int amdgpu_bo_validate(struct amdgpu_bo *bo) 643 { 644 struct ttm_operation_ctx ctx = { false, false }; 645 uint32_t domain; 646 int r; 647 648 if (bo->pin_count) 649 return 0; 650 651 domain = bo->preferred_domains; 652 653 retry: 654 amdgpu_bo_placement_from_domain(bo, domain); 655 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 656 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 657 domain = bo->allowed_domains; 658 goto retry; 659 } 660 661 return r; 662 } 663 664 /** 665 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 666 * 667 * @shadow: &amdgpu_bo shadow to be restored 668 * @fence: dma_fence associated with the operation 669 * 670 * Copies a buffer object's shadow content back to the object. 671 * This is used for recovering a buffer from its shadow in case of a gpu 672 * reset where vram context may be lost. 673 * 674 * Returns: 675 * 0 for success or a negative error code on failure. 676 */ 677 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 678 679 { 680 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 681 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 682 uint64_t shadow_addr, parent_addr; 683 684 shadow_addr = amdgpu_bo_gpu_offset(shadow); 685 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 686 687 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 688 amdgpu_bo_size(shadow), NULL, fence, 689 true, false); 690 } 691 692 /** 693 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 694 * @bo: &amdgpu_bo buffer object to be mapped 695 * @ptr: kernel virtual address to be returned 696 * 697 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 698 * amdgpu_bo_kptr() to get the kernel virtual address. 699 * 700 * Returns: 701 * 0 for success or a negative error code on failure. 702 */ 703 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 704 { 705 void *kptr; 706 long r; 707 708 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 709 return -EPERM; 710 711 kptr = amdgpu_bo_kptr(bo); 712 if (kptr) { 713 if (ptr) 714 *ptr = kptr; 715 return 0; 716 } 717 718 r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv, false, false, 719 MAX_SCHEDULE_TIMEOUT); 720 if (r < 0) 721 return r; 722 723 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 724 if (r) 725 return r; 726 727 if (ptr) 728 *ptr = amdgpu_bo_kptr(bo); 729 730 return 0; 731 } 732 733 /** 734 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 735 * @bo: &amdgpu_bo buffer object 736 * 737 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 738 * 739 * Returns: 740 * the virtual address of a buffer object area. 741 */ 742 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 743 { 744 bool is_iomem; 745 746 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 747 } 748 749 /** 750 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 751 * @bo: &amdgpu_bo buffer object to be unmapped 752 * 753 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 754 */ 755 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 756 { 757 if (bo->kmap.bo) 758 ttm_bo_kunmap(&bo->kmap); 759 } 760 761 /** 762 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 763 * @bo: &amdgpu_bo buffer object 764 * 765 * References the contained &ttm_buffer_object. 766 * 767 * Returns: 768 * a refcounted pointer to the &amdgpu_bo buffer object. 769 */ 770 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 771 { 772 if (bo == NULL) 773 return NULL; 774 775 ttm_bo_get(&bo->tbo); 776 return bo; 777 } 778 779 /** 780 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 781 * @bo: &amdgpu_bo buffer object 782 * 783 * Unreferences the contained &ttm_buffer_object and clear the pointer 784 */ 785 void amdgpu_bo_unref(struct amdgpu_bo **bo) 786 { 787 struct ttm_buffer_object *tbo; 788 789 if ((*bo) == NULL) 790 return; 791 792 tbo = &((*bo)->tbo); 793 ttm_bo_put(tbo); 794 *bo = NULL; 795 } 796 797 /** 798 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 799 * @bo: &amdgpu_bo buffer object to be pinned 800 * @domain: domain to be pinned to 801 * @min_offset: the start of requested address range 802 * @max_offset: the end of requested address range 803 * 804 * Pins the buffer object according to requested domain and address range. If 805 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 806 * pin_count and pin_size accordingly. 807 * 808 * Pinning means to lock pages in memory along with keeping them at a fixed 809 * offset. It is required when a buffer can not be moved, for example, when 810 * a display buffer is being scanned out. 811 * 812 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 813 * where to pin a buffer if there are specific restrictions on where a buffer 814 * must be located. 815 * 816 * Returns: 817 * 0 for success or a negative error code on failure. 818 */ 819 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 820 u64 min_offset, u64 max_offset) 821 { 822 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 823 struct ttm_operation_ctx ctx = { false, false }; 824 int r, i; 825 826 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 827 return -EPERM; 828 829 if (WARN_ON_ONCE(min_offset > max_offset)) 830 return -EINVAL; 831 832 /* A shared bo cannot be migrated to VRAM */ 833 if (bo->prime_shared_count) { 834 if (domain & AMDGPU_GEM_DOMAIN_GTT) 835 domain = AMDGPU_GEM_DOMAIN_GTT; 836 else 837 return -EINVAL; 838 } 839 840 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 841 * See function amdgpu_display_supported_domains() 842 */ 843 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 844 845 if (bo->pin_count) { 846 uint32_t mem_type = bo->tbo.mem.mem_type; 847 848 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 849 return -EINVAL; 850 851 bo->pin_count++; 852 853 if (max_offset != 0) { 854 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 855 WARN_ON_ONCE(max_offset < 856 (amdgpu_bo_gpu_offset(bo) - domain_start)); 857 } 858 859 return 0; 860 } 861 862 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 863 /* force to pin into visible video ram */ 864 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 865 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 866 amdgpu_bo_placement_from_domain(bo, domain); 867 for (i = 0; i < bo->placement.num_placement; i++) { 868 unsigned fpfn, lpfn; 869 870 fpfn = min_offset >> PAGE_SHIFT; 871 lpfn = max_offset >> PAGE_SHIFT; 872 873 if (fpfn > bo->placements[i].fpfn) 874 bo->placements[i].fpfn = fpfn; 875 if (!bo->placements[i].lpfn || 876 (lpfn && lpfn < bo->placements[i].lpfn)) 877 bo->placements[i].lpfn = lpfn; 878 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 879 } 880 881 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 882 if (unlikely(r)) { 883 dev_err(adev->dev, "%p pin failed\n", bo); 884 goto error; 885 } 886 887 bo->pin_count = 1; 888 889 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 890 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 891 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 892 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 893 &adev->visible_pin_size); 894 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 895 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 896 } 897 898 error: 899 return r; 900 } 901 902 /** 903 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 904 * @bo: &amdgpu_bo buffer object to be pinned 905 * @domain: domain to be pinned to 906 * 907 * A simple wrapper to amdgpu_bo_pin_restricted(). 908 * Provides a simpler API for buffers that do not have any strict restrictions 909 * on where a buffer must be located. 910 * 911 * Returns: 912 * 0 for success or a negative error code on failure. 913 */ 914 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 915 { 916 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 917 } 918 919 /** 920 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 921 * @bo: &amdgpu_bo buffer object to be unpinned 922 * 923 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 924 * Changes placement and pin size accordingly. 925 * 926 * Returns: 927 * 0 for success or a negative error code on failure. 928 */ 929 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 930 { 931 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 932 struct ttm_operation_ctx ctx = { false, false }; 933 int r, i; 934 935 if (WARN_ON_ONCE(!bo->pin_count)) { 936 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 937 return 0; 938 } 939 bo->pin_count--; 940 if (bo->pin_count) 941 return 0; 942 943 amdgpu_bo_subtract_pin_size(bo); 944 945 for (i = 0; i < bo->placement.num_placement; i++) { 946 bo->placements[i].lpfn = 0; 947 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 948 } 949 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 950 if (unlikely(r)) 951 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 952 953 return r; 954 } 955 956 /** 957 * amdgpu_bo_evict_vram - evict VRAM buffers 958 * @adev: amdgpu device object 959 * 960 * Evicts all VRAM buffers on the lru list of the memory type. 961 * Mainly used for evicting vram at suspend time. 962 * 963 * Returns: 964 * 0 for success or a negative error code on failure. 965 */ 966 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 967 { 968 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 969 #ifndef CONFIG_HIBERNATION 970 if (adev->flags & AMD_IS_APU) { 971 /* Useless to evict on IGP chips */ 972 return 0; 973 } 974 #endif 975 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 976 } 977 978 static const char *amdgpu_vram_names[] = { 979 "UNKNOWN", 980 "GDDR1", 981 "DDR2", 982 "GDDR3", 983 "GDDR4", 984 "GDDR5", 985 "HBM", 986 "DDR3", 987 "DDR4", 988 "GDDR6", 989 }; 990 991 /** 992 * amdgpu_bo_init - initialize memory manager 993 * @adev: amdgpu device object 994 * 995 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 996 * 997 * Returns: 998 * 0 for success or a negative error code on failure. 999 */ 1000 int amdgpu_bo_init(struct amdgpu_device *adev) 1001 { 1002 /* reserve PAT memory space to WC for VRAM */ 1003 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1004 adev->gmc.aper_size); 1005 1006 /* Add an MTRR for the VRAM */ 1007 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1008 adev->gmc.aper_size); 1009 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1010 adev->gmc.mc_vram_size >> 20, 1011 (unsigned long long)adev->gmc.aper_size >> 20); 1012 DRM_INFO("RAM width %dbits %s\n", 1013 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1014 return amdgpu_ttm_init(adev); 1015 } 1016 1017 /** 1018 * amdgpu_bo_late_init - late init 1019 * @adev: amdgpu device object 1020 * 1021 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1022 * initialization. 1023 * 1024 * Returns: 1025 * 0 for success or a negative error code on failure. 1026 */ 1027 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1028 { 1029 amdgpu_ttm_late_init(adev); 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * amdgpu_bo_fini - tear down memory manager 1036 * @adev: amdgpu device object 1037 * 1038 * Reverses amdgpu_bo_init() to tear down memory manager. 1039 */ 1040 void amdgpu_bo_fini(struct amdgpu_device *adev) 1041 { 1042 amdgpu_ttm_fini(adev); 1043 arch_phys_wc_del(adev->gmc.vram_mtrr); 1044 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1045 } 1046 1047 /** 1048 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1049 * @bo: &amdgpu_bo buffer object 1050 * @vma: vma as input from the fbdev mmap method 1051 * 1052 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1053 * 1054 * Returns: 1055 * 0 for success or a negative error code on failure. 1056 */ 1057 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1058 struct vm_area_struct *vma) 1059 { 1060 return ttm_fbdev_mmap(vma, &bo->tbo); 1061 } 1062 1063 /** 1064 * amdgpu_bo_set_tiling_flags - set tiling flags 1065 * @bo: &amdgpu_bo buffer object 1066 * @tiling_flags: new flags 1067 * 1068 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1069 * kernel driver to set the tiling flags on a buffer. 1070 * 1071 * Returns: 1072 * 0 for success or a negative error code on failure. 1073 */ 1074 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1075 { 1076 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1077 1078 if (adev->family <= AMDGPU_FAMILY_CZ && 1079 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1080 return -EINVAL; 1081 1082 bo->tiling_flags = tiling_flags; 1083 return 0; 1084 } 1085 1086 /** 1087 * amdgpu_bo_get_tiling_flags - get tiling flags 1088 * @bo: &amdgpu_bo buffer object 1089 * @tiling_flags: returned flags 1090 * 1091 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1092 * set the tiling flags on a buffer. 1093 */ 1094 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1095 { 1096 reservation_object_assert_held(bo->tbo.base.resv); 1097 1098 if (tiling_flags) 1099 *tiling_flags = bo->tiling_flags; 1100 } 1101 1102 /** 1103 * amdgpu_bo_set_metadata - set metadata 1104 * @bo: &amdgpu_bo buffer object 1105 * @metadata: new metadata 1106 * @metadata_size: size of the new metadata 1107 * @flags: flags of the new metadata 1108 * 1109 * Sets buffer object's metadata, its size and flags. 1110 * Used via GEM ioctl. 1111 * 1112 * Returns: 1113 * 0 for success or a negative error code on failure. 1114 */ 1115 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1116 uint32_t metadata_size, uint64_t flags) 1117 { 1118 void *buffer; 1119 1120 if (!metadata_size) { 1121 if (bo->metadata_size) { 1122 kfree(bo->metadata); 1123 bo->metadata = NULL; 1124 bo->metadata_size = 0; 1125 } 1126 return 0; 1127 } 1128 1129 if (metadata == NULL) 1130 return -EINVAL; 1131 1132 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1133 if (buffer == NULL) 1134 return -ENOMEM; 1135 1136 kfree(bo->metadata); 1137 bo->metadata_flags = flags; 1138 bo->metadata = buffer; 1139 bo->metadata_size = metadata_size; 1140 1141 return 0; 1142 } 1143 1144 /** 1145 * amdgpu_bo_get_metadata - get metadata 1146 * @bo: &amdgpu_bo buffer object 1147 * @buffer: returned metadata 1148 * @buffer_size: size of the buffer 1149 * @metadata_size: size of the returned metadata 1150 * @flags: flags of the returned metadata 1151 * 1152 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1153 * less than metadata_size. 1154 * Used via GEM ioctl. 1155 * 1156 * Returns: 1157 * 0 for success or a negative error code on failure. 1158 */ 1159 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1160 size_t buffer_size, uint32_t *metadata_size, 1161 uint64_t *flags) 1162 { 1163 if (!buffer && !metadata_size) 1164 return -EINVAL; 1165 1166 if (buffer) { 1167 if (buffer_size < bo->metadata_size) 1168 return -EINVAL; 1169 1170 if (bo->metadata_size) 1171 memcpy(buffer, bo->metadata, bo->metadata_size); 1172 } 1173 1174 if (metadata_size) 1175 *metadata_size = bo->metadata_size; 1176 if (flags) 1177 *flags = bo->metadata_flags; 1178 1179 return 0; 1180 } 1181 1182 /** 1183 * amdgpu_bo_move_notify - notification about a memory move 1184 * @bo: pointer to a buffer object 1185 * @evict: if this move is evicting the buffer from the graphics address space 1186 * @new_mem: new information of the bufer object 1187 * 1188 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1189 * bookkeeping. 1190 * TTM driver callback which is called when ttm moves a buffer. 1191 */ 1192 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1193 bool evict, 1194 struct ttm_mem_reg *new_mem) 1195 { 1196 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1197 struct amdgpu_bo *abo; 1198 struct ttm_mem_reg *old_mem = &bo->mem; 1199 1200 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1201 return; 1202 1203 abo = ttm_to_amdgpu_bo(bo); 1204 amdgpu_vm_bo_invalidate(adev, abo, evict); 1205 1206 amdgpu_bo_kunmap(abo); 1207 1208 /* remember the eviction */ 1209 if (evict) 1210 atomic64_inc(&adev->num_evictions); 1211 1212 /* update statistics */ 1213 if (!new_mem) 1214 return; 1215 1216 /* move_notify is called before move happens */ 1217 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1218 } 1219 1220 /** 1221 * amdgpu_bo_move_notify - notification about a BO being released 1222 * @bo: pointer to a buffer object 1223 * 1224 * Wipes VRAM buffers whose contents should not be leaked before the 1225 * memory is released. 1226 */ 1227 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1228 { 1229 struct dma_fence *fence = NULL; 1230 struct amdgpu_bo *abo; 1231 int r; 1232 1233 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1234 return; 1235 1236 abo = ttm_to_amdgpu_bo(bo); 1237 1238 if (abo->kfd_bo) 1239 amdgpu_amdkfd_unreserve_memory_limit(abo); 1240 1241 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1242 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1243 return; 1244 1245 reservation_object_lock(bo->base.resv, NULL); 1246 1247 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1248 if (!WARN_ON(r)) { 1249 amdgpu_bo_fence(abo, fence, false); 1250 dma_fence_put(fence); 1251 } 1252 1253 reservation_object_unlock(bo->base.resv); 1254 } 1255 1256 /** 1257 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1258 * @bo: pointer to a buffer object 1259 * 1260 * Notifies the driver we are taking a fault on this BO and have reserved it, 1261 * also performs bookkeeping. 1262 * TTM driver callback for dealing with vm faults. 1263 * 1264 * Returns: 1265 * 0 for success or a negative error code on failure. 1266 */ 1267 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1268 { 1269 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1270 struct ttm_operation_ctx ctx = { false, false }; 1271 struct amdgpu_bo *abo; 1272 unsigned long offset, size; 1273 int r; 1274 1275 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1276 return 0; 1277 1278 abo = ttm_to_amdgpu_bo(bo); 1279 1280 /* Remember that this BO was accessed by the CPU */ 1281 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1282 1283 if (bo->mem.mem_type != TTM_PL_VRAM) 1284 return 0; 1285 1286 size = bo->mem.num_pages << PAGE_SHIFT; 1287 offset = bo->mem.start << PAGE_SHIFT; 1288 if ((offset + size) <= adev->gmc.visible_vram_size) 1289 return 0; 1290 1291 /* Can't move a pinned BO to visible VRAM */ 1292 if (abo->pin_count > 0) 1293 return -EINVAL; 1294 1295 /* hurrah the memory is not visible ! */ 1296 atomic64_inc(&adev->num_vram_cpu_page_faults); 1297 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1298 AMDGPU_GEM_DOMAIN_GTT); 1299 1300 /* Avoid costly evictions; only set GTT as a busy placement */ 1301 abo->placement.num_busy_placement = 1; 1302 abo->placement.busy_placement = &abo->placements[1]; 1303 1304 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1305 if (unlikely(r != 0)) 1306 return r; 1307 1308 offset = bo->mem.start << PAGE_SHIFT; 1309 /* this should never happen */ 1310 if (bo->mem.mem_type == TTM_PL_VRAM && 1311 (offset + size) > adev->gmc.visible_vram_size) 1312 return -EINVAL; 1313 1314 return 0; 1315 } 1316 1317 /** 1318 * amdgpu_bo_fence - add fence to buffer object 1319 * 1320 * @bo: buffer object in question 1321 * @fence: fence to add 1322 * @shared: true if fence should be added shared 1323 * 1324 */ 1325 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1326 bool shared) 1327 { 1328 struct reservation_object *resv = bo->tbo.base.resv; 1329 1330 if (shared) 1331 reservation_object_add_shared_fence(resv, fence); 1332 else 1333 reservation_object_add_excl_fence(resv, fence); 1334 } 1335 1336 /** 1337 * amdgpu_sync_wait_resv - Wait for BO reservation fences 1338 * 1339 * @bo: buffer object 1340 * @owner: fence owner 1341 * @intr: Whether the wait is interruptible 1342 * 1343 * Returns: 1344 * 0 on success, errno otherwise. 1345 */ 1346 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1347 { 1348 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1349 struct amdgpu_sync sync; 1350 int r; 1351 1352 amdgpu_sync_create(&sync); 1353 amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, owner, false); 1354 r = amdgpu_sync_wait(&sync, intr); 1355 amdgpu_sync_free(&sync); 1356 1357 return r; 1358 } 1359 1360 /** 1361 * amdgpu_bo_gpu_offset - return GPU offset of bo 1362 * @bo: amdgpu object for which we query the offset 1363 * 1364 * Note: object should either be pinned or reserved when calling this 1365 * function, it might be useful to add check for this for debugging. 1366 * 1367 * Returns: 1368 * current GPU offset of the object. 1369 */ 1370 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1371 { 1372 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1373 WARN_ON_ONCE(!reservation_object_is_locked(bo->tbo.base.resv) && 1374 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); 1375 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1376 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1377 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1378 1379 return amdgpu_gmc_sign_extend(bo->tbo.offset); 1380 } 1381 1382 /** 1383 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1384 * @adev: amdgpu device object 1385 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1386 * 1387 * Returns: 1388 * Which of the allowed domains is preferred for pinning the BO for scanout. 1389 */ 1390 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1391 uint32_t domain) 1392 { 1393 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1394 domain = AMDGPU_GEM_DOMAIN_VRAM; 1395 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1396 domain = AMDGPU_GEM_DOMAIN_GTT; 1397 } 1398 return domain; 1399 } 1400