1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
35 
36 #include <drm/drm_drv.h>
37 #include <drm/amdgpu_drm.h>
38 #include <drm/drm_cache.h>
39 #include "amdgpu.h"
40 #include "amdgpu_trace.h"
41 #include "amdgpu_amdkfd.h"
42 
43 /**
44  * DOC: amdgpu_object
45  *
46  * This defines the interfaces to operate on an &amdgpu_bo buffer object which
47  * represents memory used by driver (VRAM, system memory, etc.). The driver
48  * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
49  * to create/destroy/set buffer object which are then managed by the kernel TTM
50  * memory manager.
51  * The interfaces are also used internally by kernel clients, including gfx,
52  * uvd, etc. for kernel managed allocations used by the GPU.
53  *
54  */
55 
56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
57 {
58 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
59 
60 	amdgpu_bo_kunmap(bo);
61 
62 	if (bo->tbo.base.import_attach)
63 		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
64 	drm_gem_object_release(&bo->tbo.base);
65 	amdgpu_bo_unref(&bo->parent);
66 	kvfree(bo);
67 }
68 
69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
70 {
71 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
72 	struct amdgpu_bo_user *ubo;
73 
74 	ubo = to_amdgpu_bo_user(bo);
75 	kfree(ubo->metadata);
76 	amdgpu_bo_destroy(tbo);
77 }
78 
79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
80 {
81 	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
82 	struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo;
83 	struct amdgpu_bo_vm *vmbo;
84 
85 	bo = shadow_bo->parent;
86 	vmbo = to_amdgpu_bo_vm(bo);
87 	/* in case amdgpu_device_recover_vram got NULL of bo->parent */
88 	if (!list_empty(&vmbo->shadow_list)) {
89 		mutex_lock(&adev->shadow_list_lock);
90 		list_del_init(&vmbo->shadow_list);
91 		mutex_unlock(&adev->shadow_list_lock);
92 	}
93 
94 	amdgpu_bo_destroy(tbo);
95 }
96 
97 /**
98  * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
99  * @bo: buffer object to be checked
100  *
101  * Uses destroy function associated with the object to determine if this is
102  * an &amdgpu_bo.
103  *
104  * Returns:
105  * true if the object belongs to &amdgpu_bo, false if not.
106  */
107 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
108 {
109 	if (bo->destroy == &amdgpu_bo_destroy ||
110 	    bo->destroy == &amdgpu_bo_user_destroy ||
111 	    bo->destroy == &amdgpu_bo_vm_destroy)
112 		return true;
113 
114 	return false;
115 }
116 
117 /**
118  * amdgpu_bo_placement_from_domain - set buffer's placement
119  * @abo: &amdgpu_bo buffer object whose placement is to be set
120  * @domain: requested domain
121  *
122  * Sets buffer's placement according to requested domain and the buffer's
123  * flags.
124  */
125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
126 {
127 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
128 	struct ttm_placement *placement = &abo->placement;
129 	struct ttm_place *places = abo->placements;
130 	u64 flags = abo->flags;
131 	u32 c = 0;
132 
133 	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
134 		unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
135 		int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
136 
137 		if (adev->gmc.mem_partitions && mem_id >= 0) {
138 			places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn;
139 			/*
140 			 * memory partition range lpfn is inclusive start + size - 1
141 			 * TTM place lpfn is exclusive start + size
142 			 */
143 			places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1;
144 		} else {
145 			places[c].fpfn = 0;
146 			places[c].lpfn = 0;
147 		}
148 		places[c].mem_type = TTM_PL_VRAM;
149 		places[c].flags = 0;
150 
151 		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
152 			places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn);
153 		else
154 			places[c].flags |= TTM_PL_FLAG_TOPDOWN;
155 
156 		if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
157 			places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
158 		c++;
159 	}
160 
161 	if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) {
162 		places[c].fpfn = 0;
163 		places[c].lpfn = 0;
164 		places[c].mem_type = AMDGPU_PL_DOORBELL;
165 		places[c].flags = 0;
166 		c++;
167 	}
168 
169 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
170 		places[c].fpfn = 0;
171 		places[c].lpfn = 0;
172 		places[c].mem_type =
173 			abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
174 			AMDGPU_PL_PREEMPT : TTM_PL_TT;
175 		places[c].flags = 0;
176 		c++;
177 	}
178 
179 	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
180 		places[c].fpfn = 0;
181 		places[c].lpfn = 0;
182 		places[c].mem_type = TTM_PL_SYSTEM;
183 		places[c].flags = 0;
184 		c++;
185 	}
186 
187 	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
188 		places[c].fpfn = 0;
189 		places[c].lpfn = 0;
190 		places[c].mem_type = AMDGPU_PL_GDS;
191 		places[c].flags = 0;
192 		c++;
193 	}
194 
195 	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
196 		places[c].fpfn = 0;
197 		places[c].lpfn = 0;
198 		places[c].mem_type = AMDGPU_PL_GWS;
199 		places[c].flags = 0;
200 		c++;
201 	}
202 
203 	if (domain & AMDGPU_GEM_DOMAIN_OA) {
204 		places[c].fpfn = 0;
205 		places[c].lpfn = 0;
206 		places[c].mem_type = AMDGPU_PL_OA;
207 		places[c].flags = 0;
208 		c++;
209 	}
210 
211 	if (!c) {
212 		places[c].fpfn = 0;
213 		places[c].lpfn = 0;
214 		places[c].mem_type = TTM_PL_SYSTEM;
215 		places[c].flags = 0;
216 		c++;
217 	}
218 
219 	BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
220 
221 	placement->num_placement = c;
222 	placement->placement = places;
223 
224 	placement->num_busy_placement = c;
225 	placement->busy_placement = places;
226 }
227 
228 /**
229  * amdgpu_bo_create_reserved - create reserved BO for kernel use
230  *
231  * @adev: amdgpu device object
232  * @size: size for the new BO
233  * @align: alignment for the new BO
234  * @domain: where to place it
235  * @bo_ptr: used to initialize BOs in structures
236  * @gpu_addr: GPU addr of the pinned BO
237  * @cpu_addr: optional CPU address mapping
238  *
239  * Allocates and pins a BO for kernel internal use, and returns it still
240  * reserved.
241  *
242  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
243  *
244  * Returns:
245  * 0 on success, negative error code otherwise.
246  */
247 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
248 			      unsigned long size, int align,
249 			      u32 domain, struct amdgpu_bo **bo_ptr,
250 			      u64 *gpu_addr, void **cpu_addr)
251 {
252 	struct amdgpu_bo_param bp;
253 	bool free = false;
254 	int r;
255 
256 	if (!size) {
257 		amdgpu_bo_unref(bo_ptr);
258 		return 0;
259 	}
260 
261 	memset(&bp, 0, sizeof(bp));
262 	bp.size = size;
263 	bp.byte_align = align;
264 	bp.domain = domain;
265 	bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
266 		: AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
267 	bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
268 	bp.type = ttm_bo_type_kernel;
269 	bp.resv = NULL;
270 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
271 
272 	if (!*bo_ptr) {
273 		r = amdgpu_bo_create(adev, &bp, bo_ptr);
274 		if (r) {
275 			dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
276 				r);
277 			return r;
278 		}
279 		free = true;
280 	}
281 
282 	r = amdgpu_bo_reserve(*bo_ptr, false);
283 	if (r) {
284 		dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
285 		goto error_free;
286 	}
287 
288 	r = amdgpu_bo_pin(*bo_ptr, domain);
289 	if (r) {
290 		dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
291 		goto error_unreserve;
292 	}
293 
294 	r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
295 	if (r) {
296 		dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
297 		goto error_unpin;
298 	}
299 
300 	if (gpu_addr)
301 		*gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
302 
303 	if (cpu_addr) {
304 		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
305 		if (r) {
306 			dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
307 			goto error_unpin;
308 		}
309 	}
310 
311 	return 0;
312 
313 error_unpin:
314 	amdgpu_bo_unpin(*bo_ptr);
315 error_unreserve:
316 	amdgpu_bo_unreserve(*bo_ptr);
317 
318 error_free:
319 	if (free)
320 		amdgpu_bo_unref(bo_ptr);
321 
322 	return r;
323 }
324 
325 /**
326  * amdgpu_bo_create_kernel - create BO for kernel use
327  *
328  * @adev: amdgpu device object
329  * @size: size for the new BO
330  * @align: alignment for the new BO
331  * @domain: where to place it
332  * @bo_ptr:  used to initialize BOs in structures
333  * @gpu_addr: GPU addr of the pinned BO
334  * @cpu_addr: optional CPU address mapping
335  *
336  * Allocates and pins a BO for kernel internal use.
337  *
338  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
339  *
340  * Returns:
341  * 0 on success, negative error code otherwise.
342  */
343 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
344 			    unsigned long size, int align,
345 			    u32 domain, struct amdgpu_bo **bo_ptr,
346 			    u64 *gpu_addr, void **cpu_addr)
347 {
348 	int r;
349 
350 	r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
351 				      gpu_addr, cpu_addr);
352 
353 	if (r)
354 		return r;
355 
356 	if (*bo_ptr)
357 		amdgpu_bo_unreserve(*bo_ptr);
358 
359 	return 0;
360 }
361 
362 /**
363  * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
364  *
365  * @adev: amdgpu device object
366  * @offset: offset of the BO
367  * @size: size of the BO
368  * @bo_ptr:  used to initialize BOs in structures
369  * @cpu_addr: optional CPU address mapping
370  *
371  * Creates a kernel BO at a specific offset in VRAM.
372  *
373  * Returns:
374  * 0 on success, negative error code otherwise.
375  */
376 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
377 			       uint64_t offset, uint64_t size,
378 			       struct amdgpu_bo **bo_ptr, void **cpu_addr)
379 {
380 	struct ttm_operation_ctx ctx = { false, false };
381 	unsigned int i;
382 	int r;
383 
384 	offset &= PAGE_MASK;
385 	size = ALIGN(size, PAGE_SIZE);
386 
387 	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
388 				      AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL,
389 				      cpu_addr);
390 	if (r)
391 		return r;
392 
393 	if ((*bo_ptr) == NULL)
394 		return 0;
395 
396 	/*
397 	 * Remove the original mem node and create a new one at the request
398 	 * position.
399 	 */
400 	if (cpu_addr)
401 		amdgpu_bo_kunmap(*bo_ptr);
402 
403 	ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
404 
405 	for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
406 		(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
407 		(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
408 	}
409 	r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
410 			     &(*bo_ptr)->tbo.resource, &ctx);
411 	if (r)
412 		goto error;
413 
414 	if (cpu_addr) {
415 		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
416 		if (r)
417 			goto error;
418 	}
419 
420 	amdgpu_bo_unreserve(*bo_ptr);
421 	return 0;
422 
423 error:
424 	amdgpu_bo_unreserve(*bo_ptr);
425 	amdgpu_bo_unref(bo_ptr);
426 	return r;
427 }
428 
429 /**
430  * amdgpu_bo_free_kernel - free BO for kernel use
431  *
432  * @bo: amdgpu BO to free
433  * @gpu_addr: pointer to where the BO's GPU memory space address was stored
434  * @cpu_addr: pointer to where the BO's CPU memory space address was stored
435  *
436  * unmaps and unpin a BO for kernel internal use.
437  */
438 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
439 			   void **cpu_addr)
440 {
441 	if (*bo == NULL)
442 		return;
443 
444 	WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend);
445 
446 	if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
447 		if (cpu_addr)
448 			amdgpu_bo_kunmap(*bo);
449 
450 		amdgpu_bo_unpin(*bo);
451 		amdgpu_bo_unreserve(*bo);
452 	}
453 	amdgpu_bo_unref(bo);
454 
455 	if (gpu_addr)
456 		*gpu_addr = 0;
457 
458 	if (cpu_addr)
459 		*cpu_addr = NULL;
460 }
461 
462 /* Validate bo size is bit bigger then the request domain */
463 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
464 					  unsigned long size, u32 domain)
465 {
466 	struct ttm_resource_manager *man = NULL;
467 
468 	/*
469 	 * If GTT is part of requested domains the check must succeed to
470 	 * allow fall back to GTT.
471 	 */
472 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
473 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
474 
475 		if (man && size < man->size)
476 			return true;
477 		else if (!man)
478 			WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized");
479 		goto fail;
480 	} else if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
481 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
482 
483 		if (man && size < man->size)
484 			return true;
485 		goto fail;
486 	}
487 
488 	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */
489 	return true;
490 
491 fail:
492 	if (man)
493 		DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
494 			  man->size);
495 	return false;
496 }
497 
498 bool amdgpu_bo_support_uswc(u64 bo_flags)
499 {
500 
501 #ifdef CONFIG_X86_32
502 	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
503 	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
504 	 */
505 	return false;
506 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
507 	/* Don't try to enable write-combining when it can't work, or things
508 	 * may be slow
509 	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
510 	 */
511 
512 #ifndef CONFIG_COMPILE_TEST
513 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
514 	 thanks to write-combining
515 #endif
516 
517 	if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
518 		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
519 			      "better performance thanks to write-combining\n");
520 	return false;
521 #else
522 	/* For architectures that don't support WC memory,
523 	 * mask out the WC flag from the BO
524 	 */
525 	if (!drm_arch_can_wc_memory())
526 		return false;
527 
528 	return true;
529 #endif
530 }
531 
532 /**
533  * amdgpu_bo_create - create an &amdgpu_bo buffer object
534  * @adev: amdgpu device object
535  * @bp: parameters to be used for the buffer object
536  * @bo_ptr: pointer to the buffer object pointer
537  *
538  * Creates an &amdgpu_bo buffer object.
539  *
540  * Returns:
541  * 0 for success or a negative error code on failure.
542  */
543 int amdgpu_bo_create(struct amdgpu_device *adev,
544 			       struct amdgpu_bo_param *bp,
545 			       struct amdgpu_bo **bo_ptr)
546 {
547 	struct ttm_operation_ctx ctx = {
548 		.interruptible = (bp->type != ttm_bo_type_kernel),
549 		.no_wait_gpu = bp->no_wait_gpu,
550 		/* We opt to avoid OOM on system pages allocations */
551 		.gfp_retry_mayfail = true,
552 		.allow_res_evict = bp->type != ttm_bo_type_kernel,
553 		.resv = bp->resv
554 	};
555 	struct amdgpu_bo *bo;
556 	unsigned long page_align, size = bp->size;
557 	int r;
558 
559 	/* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
560 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
561 		/* GWS and OA don't need any alignment. */
562 		page_align = bp->byte_align;
563 		size <<= PAGE_SHIFT;
564 
565 	} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
566 		/* Both size and alignment must be a multiple of 4. */
567 		page_align = ALIGN(bp->byte_align, 4);
568 		size = ALIGN(size, 4) << PAGE_SHIFT;
569 	} else {
570 		/* Memory should be aligned at least to a page size. */
571 		page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
572 		size = ALIGN(size, PAGE_SIZE);
573 	}
574 
575 	if (!amdgpu_bo_validate_size(adev, size, bp->domain))
576 		return -ENOMEM;
577 
578 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
579 
580 	*bo_ptr = NULL;
581 	bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
582 	if (bo == NULL)
583 		return -ENOMEM;
584 	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
585 	bo->vm_bo = NULL;
586 	bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
587 		bp->domain;
588 	bo->allowed_domains = bo->preferred_domains;
589 	if (bp->type != ttm_bo_type_kernel &&
590 	    !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) &&
591 	    bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
592 		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
593 
594 	bo->flags = bp->flags;
595 
596 	if (adev->gmc.mem_partitions)
597 		/* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */
598 		bo->xcp_id = bp->xcp_id_plus1 - 1;
599 	else
600 		/* For GPUs without spatial partitioning */
601 		bo->xcp_id = 0;
602 
603 	if (!amdgpu_bo_support_uswc(bo->flags))
604 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
605 
606 	if (adev->ras_enabled)
607 		bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
608 
609 	bo->tbo.bdev = &adev->mman.bdev;
610 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
611 			  AMDGPU_GEM_DOMAIN_GDS))
612 		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
613 	else
614 		amdgpu_bo_placement_from_domain(bo, bp->domain);
615 	if (bp->type == ttm_bo_type_kernel)
616 		bo->tbo.priority = 2;
617 	else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE))
618 		bo->tbo.priority = 1;
619 
620 	if (!bp->destroy)
621 		bp->destroy = &amdgpu_bo_destroy;
622 
623 	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type,
624 				 &bo->placement, page_align, &ctx,  NULL,
625 				 bp->resv, bp->destroy);
626 	if (unlikely(r != 0))
627 		return r;
628 
629 	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
630 	    amdgpu_res_cpu_visible(adev, bo->tbo.resource))
631 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
632 					     ctx.bytes_moved);
633 	else
634 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
635 
636 	if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
637 	    bo->tbo.resource->mem_type == TTM_PL_VRAM) {
638 		struct dma_fence *fence;
639 
640 		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence, true);
641 		if (unlikely(r))
642 			goto fail_unreserve;
643 
644 		dma_resv_add_fence(bo->tbo.base.resv, fence,
645 				   DMA_RESV_USAGE_KERNEL);
646 		dma_fence_put(fence);
647 	}
648 	if (!bp->resv)
649 		amdgpu_bo_unreserve(bo);
650 	*bo_ptr = bo;
651 
652 	trace_amdgpu_bo_create(bo);
653 
654 	/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
655 	if (bp->type == ttm_bo_type_device)
656 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
657 
658 	return 0;
659 
660 fail_unreserve:
661 	if (!bp->resv)
662 		dma_resv_unlock(bo->tbo.base.resv);
663 	amdgpu_bo_unref(&bo);
664 	return r;
665 }
666 
667 /**
668  * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
669  * @adev: amdgpu device object
670  * @bp: parameters to be used for the buffer object
671  * @ubo_ptr: pointer to the buffer object pointer
672  *
673  * Create a BO to be used by user application;
674  *
675  * Returns:
676  * 0 for success or a negative error code on failure.
677  */
678 
679 int amdgpu_bo_create_user(struct amdgpu_device *adev,
680 			  struct amdgpu_bo_param *bp,
681 			  struct amdgpu_bo_user **ubo_ptr)
682 {
683 	struct amdgpu_bo *bo_ptr;
684 	int r;
685 
686 	bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
687 	bp->destroy = &amdgpu_bo_user_destroy;
688 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
689 	if (r)
690 		return r;
691 
692 	*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
693 	return r;
694 }
695 
696 /**
697  * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
698  * @adev: amdgpu device object
699  * @bp: parameters to be used for the buffer object
700  * @vmbo_ptr: pointer to the buffer object pointer
701  *
702  * Create a BO to be for GPUVM.
703  *
704  * Returns:
705  * 0 for success or a negative error code on failure.
706  */
707 
708 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
709 			struct amdgpu_bo_param *bp,
710 			struct amdgpu_bo_vm **vmbo_ptr)
711 {
712 	struct amdgpu_bo *bo_ptr;
713 	int r;
714 
715 	/* bo_ptr_size will be determined by the caller and it depends on
716 	 * num of amdgpu_vm_pt entries.
717 	 */
718 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
719 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
720 	if (r)
721 		return r;
722 
723 	*vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
724 	return r;
725 }
726 
727 /**
728  * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
729  *
730  * @vmbo: BO that will be inserted into the shadow list
731  *
732  * Insert a BO to the shadow list.
733  */
734 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)
735 {
736 	struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev);
737 
738 	mutex_lock(&adev->shadow_list_lock);
739 	list_add_tail(&vmbo->shadow_list, &adev->shadow_list);
740 	vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo);
741 	vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy;
742 	mutex_unlock(&adev->shadow_list_lock);
743 }
744 
745 /**
746  * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
747  *
748  * @shadow: &amdgpu_bo shadow to be restored
749  * @fence: dma_fence associated with the operation
750  *
751  * Copies a buffer object's shadow content back to the object.
752  * This is used for recovering a buffer from its shadow in case of a gpu
753  * reset where vram context may be lost.
754  *
755  * Returns:
756  * 0 for success or a negative error code on failure.
757  */
758 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
759 
760 {
761 	struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
762 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
763 	uint64_t shadow_addr, parent_addr;
764 
765 	shadow_addr = amdgpu_bo_gpu_offset(shadow);
766 	parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
767 
768 	return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
769 				  amdgpu_bo_size(shadow), NULL, fence,
770 				  true, false, false);
771 }
772 
773 /**
774  * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
775  * @bo: &amdgpu_bo buffer object to be mapped
776  * @ptr: kernel virtual address to be returned
777  *
778  * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
779  * amdgpu_bo_kptr() to get the kernel virtual address.
780  *
781  * Returns:
782  * 0 for success or a negative error code on failure.
783  */
784 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
785 {
786 	void *kptr;
787 	long r;
788 
789 	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
790 		return -EPERM;
791 
792 	r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
793 				  false, MAX_SCHEDULE_TIMEOUT);
794 	if (r < 0)
795 		return r;
796 
797 	kptr = amdgpu_bo_kptr(bo);
798 	if (kptr) {
799 		if (ptr)
800 			*ptr = kptr;
801 		return 0;
802 	}
803 
804 	r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
805 	if (r)
806 		return r;
807 
808 	if (ptr)
809 		*ptr = amdgpu_bo_kptr(bo);
810 
811 	return 0;
812 }
813 
814 /**
815  * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
816  * @bo: &amdgpu_bo buffer object
817  *
818  * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
819  *
820  * Returns:
821  * the virtual address of a buffer object area.
822  */
823 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
824 {
825 	bool is_iomem;
826 
827 	return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
828 }
829 
830 /**
831  * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
832  * @bo: &amdgpu_bo buffer object to be unmapped
833  *
834  * Unmaps a kernel map set up by amdgpu_bo_kmap().
835  */
836 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
837 {
838 	if (bo->kmap.bo)
839 		ttm_bo_kunmap(&bo->kmap);
840 }
841 
842 /**
843  * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
844  * @bo: &amdgpu_bo buffer object
845  *
846  * References the contained &ttm_buffer_object.
847  *
848  * Returns:
849  * a refcounted pointer to the &amdgpu_bo buffer object.
850  */
851 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
852 {
853 	if (bo == NULL)
854 		return NULL;
855 
856 	ttm_bo_get(&bo->tbo);
857 	return bo;
858 }
859 
860 /**
861  * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
862  * @bo: &amdgpu_bo buffer object
863  *
864  * Unreferences the contained &ttm_buffer_object and clear the pointer
865  */
866 void amdgpu_bo_unref(struct amdgpu_bo **bo)
867 {
868 	struct ttm_buffer_object *tbo;
869 
870 	if ((*bo) == NULL)
871 		return;
872 
873 	tbo = &((*bo)->tbo);
874 	ttm_bo_put(tbo);
875 	*bo = NULL;
876 }
877 
878 /**
879  * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
880  * @bo: &amdgpu_bo buffer object to be pinned
881  * @domain: domain to be pinned to
882  * @min_offset: the start of requested address range
883  * @max_offset: the end of requested address range
884  *
885  * Pins the buffer object according to requested domain and address range. If
886  * the memory is unbound gart memory, binds the pages into gart table. Adjusts
887  * pin_count and pin_size accordingly.
888  *
889  * Pinning means to lock pages in memory along with keeping them at a fixed
890  * offset. It is required when a buffer can not be moved, for example, when
891  * a display buffer is being scanned out.
892  *
893  * Compared with amdgpu_bo_pin(), this function gives more flexibility on
894  * where to pin a buffer if there are specific restrictions on where a buffer
895  * must be located.
896  *
897  * Returns:
898  * 0 for success or a negative error code on failure.
899  */
900 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
901 			     u64 min_offset, u64 max_offset)
902 {
903 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
904 	struct ttm_operation_ctx ctx = { false, false };
905 	int r, i;
906 
907 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
908 		return -EPERM;
909 
910 	if (WARN_ON_ONCE(min_offset > max_offset))
911 		return -EINVAL;
912 
913 	/* Check domain to be pinned to against preferred domains */
914 	if (bo->preferred_domains & domain)
915 		domain = bo->preferred_domains & domain;
916 
917 	/* A shared bo cannot be migrated to VRAM */
918 	if (bo->tbo.base.import_attach) {
919 		if (domain & AMDGPU_GEM_DOMAIN_GTT)
920 			domain = AMDGPU_GEM_DOMAIN_GTT;
921 		else
922 			return -EINVAL;
923 	}
924 
925 	if (bo->tbo.pin_count) {
926 		uint32_t mem_type = bo->tbo.resource->mem_type;
927 		uint32_t mem_flags = bo->tbo.resource->placement;
928 
929 		if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
930 			return -EINVAL;
931 
932 		if ((mem_type == TTM_PL_VRAM) &&
933 		    (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
934 		    !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
935 			return -EINVAL;
936 
937 		ttm_bo_pin(&bo->tbo);
938 
939 		if (max_offset != 0) {
940 			u64 domain_start = amdgpu_ttm_domain_start(adev,
941 								   mem_type);
942 			WARN_ON_ONCE(max_offset <
943 				     (amdgpu_bo_gpu_offset(bo) - domain_start));
944 		}
945 
946 		return 0;
947 	}
948 
949 	/* This assumes only APU display buffers are pinned with (VRAM|GTT).
950 	 * See function amdgpu_display_supported_domains()
951 	 */
952 	domain = amdgpu_bo_get_preferred_domain(adev, domain);
953 
954 	if (bo->tbo.base.import_attach)
955 		dma_buf_pin(bo->tbo.base.import_attach);
956 
957 	/* force to pin into visible video ram */
958 	if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
959 		bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
960 	amdgpu_bo_placement_from_domain(bo, domain);
961 	for (i = 0; i < bo->placement.num_placement; i++) {
962 		unsigned int fpfn, lpfn;
963 
964 		fpfn = min_offset >> PAGE_SHIFT;
965 		lpfn = max_offset >> PAGE_SHIFT;
966 
967 		if (fpfn > bo->placements[i].fpfn)
968 			bo->placements[i].fpfn = fpfn;
969 		if (!bo->placements[i].lpfn ||
970 		    (lpfn && lpfn < bo->placements[i].lpfn))
971 			bo->placements[i].lpfn = lpfn;
972 	}
973 
974 	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
975 	if (unlikely(r)) {
976 		dev_err(adev->dev, "%p pin failed\n", bo);
977 		goto error;
978 	}
979 
980 	ttm_bo_pin(&bo->tbo);
981 
982 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
983 	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
984 		atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
985 		atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
986 			     &adev->visible_pin_size);
987 	} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
988 		atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
989 	}
990 
991 error:
992 	return r;
993 }
994 
995 /**
996  * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
997  * @bo: &amdgpu_bo buffer object to be pinned
998  * @domain: domain to be pinned to
999  *
1000  * A simple wrapper to amdgpu_bo_pin_restricted().
1001  * Provides a simpler API for buffers that do not have any strict restrictions
1002  * on where a buffer must be located.
1003  *
1004  * Returns:
1005  * 0 for success or a negative error code on failure.
1006  */
1007 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
1008 {
1009 	bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1010 	return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1011 }
1012 
1013 /**
1014  * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
1015  * @bo: &amdgpu_bo buffer object to be unpinned
1016  *
1017  * Decreases the pin_count, and clears the flags if pin_count reaches 0.
1018  * Changes placement and pin size accordingly.
1019  *
1020  * Returns:
1021  * 0 for success or a negative error code on failure.
1022  */
1023 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
1024 {
1025 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1026 
1027 	ttm_bo_unpin(&bo->tbo);
1028 	if (bo->tbo.pin_count)
1029 		return;
1030 
1031 	if (bo->tbo.base.import_attach)
1032 		dma_buf_unpin(bo->tbo.base.import_attach);
1033 
1034 	if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
1035 		atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
1036 		atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
1037 			     &adev->visible_pin_size);
1038 	} else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1039 		atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
1040 	}
1041 
1042 }
1043 
1044 static const char * const amdgpu_vram_names[] = {
1045 	"UNKNOWN",
1046 	"GDDR1",
1047 	"DDR2",
1048 	"GDDR3",
1049 	"GDDR4",
1050 	"GDDR5",
1051 	"HBM",
1052 	"DDR3",
1053 	"DDR4",
1054 	"GDDR6",
1055 	"DDR5",
1056 	"LPDDR4",
1057 	"LPDDR5"
1058 };
1059 
1060 /**
1061  * amdgpu_bo_init - initialize memory manager
1062  * @adev: amdgpu device object
1063  *
1064  * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1065  *
1066  * Returns:
1067  * 0 for success or a negative error code on failure.
1068  */
1069 int amdgpu_bo_init(struct amdgpu_device *adev)
1070 {
1071 	/* On A+A platform, VRAM can be mapped as WB */
1072 	if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
1073 		/* reserve PAT memory space to WC for VRAM */
1074 		int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1075 				adev->gmc.aper_size);
1076 
1077 		if (r) {
1078 			DRM_ERROR("Unable to set WC memtype for the aperture base\n");
1079 			return r;
1080 		}
1081 
1082 		/* Add an MTRR for the VRAM */
1083 		adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1084 				adev->gmc.aper_size);
1085 	}
1086 
1087 	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1088 		 adev->gmc.mc_vram_size >> 20,
1089 		 (unsigned long long)adev->gmc.aper_size >> 20);
1090 	DRM_INFO("RAM width %dbits %s\n",
1091 		 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1092 	return amdgpu_ttm_init(adev);
1093 }
1094 
1095 /**
1096  * amdgpu_bo_fini - tear down memory manager
1097  * @adev: amdgpu device object
1098  *
1099  * Reverses amdgpu_bo_init() to tear down memory manager.
1100  */
1101 void amdgpu_bo_fini(struct amdgpu_device *adev)
1102 {
1103 	int idx;
1104 
1105 	amdgpu_ttm_fini(adev);
1106 
1107 	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1108 		if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
1109 			arch_phys_wc_del(adev->gmc.vram_mtrr);
1110 			arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
1111 		}
1112 		drm_dev_exit(idx);
1113 	}
1114 }
1115 
1116 /**
1117  * amdgpu_bo_set_tiling_flags - set tiling flags
1118  * @bo: &amdgpu_bo buffer object
1119  * @tiling_flags: new flags
1120  *
1121  * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1122  * kernel driver to set the tiling flags on a buffer.
1123  *
1124  * Returns:
1125  * 0 for success or a negative error code on failure.
1126  */
1127 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1128 {
1129 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1130 	struct amdgpu_bo_user *ubo;
1131 
1132 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1133 	if (adev->family <= AMDGPU_FAMILY_CZ &&
1134 	    AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1135 		return -EINVAL;
1136 
1137 	ubo = to_amdgpu_bo_user(bo);
1138 	ubo->tiling_flags = tiling_flags;
1139 	return 0;
1140 }
1141 
1142 /**
1143  * amdgpu_bo_get_tiling_flags - get tiling flags
1144  * @bo: &amdgpu_bo buffer object
1145  * @tiling_flags: returned flags
1146  *
1147  * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1148  * set the tiling flags on a buffer.
1149  */
1150 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1151 {
1152 	struct amdgpu_bo_user *ubo;
1153 
1154 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1155 	dma_resv_assert_held(bo->tbo.base.resv);
1156 	ubo = to_amdgpu_bo_user(bo);
1157 
1158 	if (tiling_flags)
1159 		*tiling_flags = ubo->tiling_flags;
1160 }
1161 
1162 /**
1163  * amdgpu_bo_set_metadata - set metadata
1164  * @bo: &amdgpu_bo buffer object
1165  * @metadata: new metadata
1166  * @metadata_size: size of the new metadata
1167  * @flags: flags of the new metadata
1168  *
1169  * Sets buffer object's metadata, its size and flags.
1170  * Used via GEM ioctl.
1171  *
1172  * Returns:
1173  * 0 for success or a negative error code on failure.
1174  */
1175 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata,
1176 			   u32 metadata_size, uint64_t flags)
1177 {
1178 	struct amdgpu_bo_user *ubo;
1179 	void *buffer;
1180 
1181 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1182 	ubo = to_amdgpu_bo_user(bo);
1183 	if (!metadata_size) {
1184 		if (ubo->metadata_size) {
1185 			kfree(ubo->metadata);
1186 			ubo->metadata = NULL;
1187 			ubo->metadata_size = 0;
1188 		}
1189 		return 0;
1190 	}
1191 
1192 	if (metadata == NULL)
1193 		return -EINVAL;
1194 
1195 	buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1196 	if (buffer == NULL)
1197 		return -ENOMEM;
1198 
1199 	kfree(ubo->metadata);
1200 	ubo->metadata_flags = flags;
1201 	ubo->metadata = buffer;
1202 	ubo->metadata_size = metadata_size;
1203 
1204 	return 0;
1205 }
1206 
1207 /**
1208  * amdgpu_bo_get_metadata - get metadata
1209  * @bo: &amdgpu_bo buffer object
1210  * @buffer: returned metadata
1211  * @buffer_size: size of the buffer
1212  * @metadata_size: size of the returned metadata
1213  * @flags: flags of the returned metadata
1214  *
1215  * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1216  * less than metadata_size.
1217  * Used via GEM ioctl.
1218  *
1219  * Returns:
1220  * 0 for success or a negative error code on failure.
1221  */
1222 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1223 			   size_t buffer_size, uint32_t *metadata_size,
1224 			   uint64_t *flags)
1225 {
1226 	struct amdgpu_bo_user *ubo;
1227 
1228 	if (!buffer && !metadata_size)
1229 		return -EINVAL;
1230 
1231 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1232 	ubo = to_amdgpu_bo_user(bo);
1233 	if (metadata_size)
1234 		*metadata_size = ubo->metadata_size;
1235 
1236 	if (buffer) {
1237 		if (buffer_size < ubo->metadata_size)
1238 			return -EINVAL;
1239 
1240 		if (ubo->metadata_size)
1241 			memcpy(buffer, ubo->metadata, ubo->metadata_size);
1242 	}
1243 
1244 	if (flags)
1245 		*flags = ubo->metadata_flags;
1246 
1247 	return 0;
1248 }
1249 
1250 /**
1251  * amdgpu_bo_move_notify - notification about a memory move
1252  * @bo: pointer to a buffer object
1253  * @evict: if this move is evicting the buffer from the graphics address space
1254  * @new_mem: new resource for backing the BO
1255  *
1256  * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1257  * bookkeeping.
1258  * TTM driver callback which is called when ttm moves a buffer.
1259  */
1260 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1261 			   bool evict,
1262 			   struct ttm_resource *new_mem)
1263 {
1264 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1265 	struct ttm_resource *old_mem = bo->resource;
1266 	struct amdgpu_bo *abo;
1267 
1268 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1269 		return;
1270 
1271 	abo = ttm_to_amdgpu_bo(bo);
1272 	amdgpu_vm_bo_invalidate(adev, abo, evict);
1273 
1274 	amdgpu_bo_kunmap(abo);
1275 
1276 	if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1277 	    old_mem && old_mem->mem_type != TTM_PL_SYSTEM)
1278 		dma_buf_move_notify(abo->tbo.base.dma_buf);
1279 
1280 	/* move_notify is called before move happens */
1281 	trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1,
1282 			     old_mem ? old_mem->mem_type : -1);
1283 }
1284 
1285 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
1286 			  struct amdgpu_mem_stats *stats)
1287 {
1288 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1289 	struct ttm_resource *res = bo->tbo.resource;
1290 	uint64_t size = amdgpu_bo_size(bo);
1291 	struct drm_gem_object *obj;
1292 	unsigned int domain;
1293 	bool shared;
1294 
1295 	/* Abort if the BO doesn't currently have a backing store */
1296 	if (!res)
1297 		return;
1298 
1299 	obj = &bo->tbo.base;
1300 	shared = drm_gem_object_is_shared_for_memory_stats(obj);
1301 
1302 	domain = amdgpu_mem_type_to_domain(res->mem_type);
1303 	switch (domain) {
1304 	case AMDGPU_GEM_DOMAIN_VRAM:
1305 		stats->vram += size;
1306 		if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
1307 			stats->visible_vram += size;
1308 		if (shared)
1309 			stats->vram_shared += size;
1310 		break;
1311 	case AMDGPU_GEM_DOMAIN_GTT:
1312 		stats->gtt += size;
1313 		if (shared)
1314 			stats->gtt_shared += size;
1315 		break;
1316 	case AMDGPU_GEM_DOMAIN_CPU:
1317 	default:
1318 		stats->cpu += size;
1319 		if (shared)
1320 			stats->cpu_shared += size;
1321 		break;
1322 	}
1323 
1324 	if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) {
1325 		stats->requested_vram += size;
1326 		if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1327 			stats->requested_visible_vram += size;
1328 
1329 		if (domain != AMDGPU_GEM_DOMAIN_VRAM) {
1330 			stats->evicted_vram += size;
1331 			if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1332 				stats->evicted_visible_vram += size;
1333 		}
1334 	} else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) {
1335 		stats->requested_gtt += size;
1336 	}
1337 }
1338 
1339 /**
1340  * amdgpu_bo_release_notify - notification about a BO being released
1341  * @bo: pointer to a buffer object
1342  *
1343  * Wipes VRAM buffers whose contents should not be leaked before the
1344  * memory is released.
1345  */
1346 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1347 {
1348 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1349 	struct dma_fence *fence = NULL;
1350 	struct amdgpu_bo *abo;
1351 	int r;
1352 
1353 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1354 		return;
1355 
1356 	abo = ttm_to_amdgpu_bo(bo);
1357 
1358 	if (abo->kfd_bo)
1359 		amdgpu_amdkfd_release_notify(abo);
1360 
1361 	/* We only remove the fence if the resv has individualized. */
1362 	WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1363 			&& bo->base.resv != &bo->base._resv);
1364 	if (bo->base.resv == &bo->base._resv)
1365 		amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1366 
1367 	if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
1368 	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
1369 	    adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
1370 		return;
1371 
1372 	if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
1373 		return;
1374 
1375 	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence, true);
1376 	if (!WARN_ON(r)) {
1377 		amdgpu_bo_fence(abo, fence, false);
1378 		dma_fence_put(fence);
1379 	}
1380 
1381 	dma_resv_unlock(bo->base.resv);
1382 }
1383 
1384 /**
1385  * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1386  * @bo: pointer to a buffer object
1387  *
1388  * Notifies the driver we are taking a fault on this BO and have reserved it,
1389  * also performs bookkeeping.
1390  * TTM driver callback for dealing with vm faults.
1391  *
1392  * Returns:
1393  * 0 for success or a negative error code on failure.
1394  */
1395 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1396 {
1397 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1398 	struct ttm_operation_ctx ctx = { false, false };
1399 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1400 	int r;
1401 
1402 	/* Remember that this BO was accessed by the CPU */
1403 	abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1404 
1405 	if (amdgpu_res_cpu_visible(adev, bo->resource))
1406 		return 0;
1407 
1408 	/* Can't move a pinned BO to visible VRAM */
1409 	if (abo->tbo.pin_count > 0)
1410 		return VM_FAULT_SIGBUS;
1411 
1412 	/* hurrah the memory is not visible ! */
1413 	atomic64_inc(&adev->num_vram_cpu_page_faults);
1414 	amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1415 					AMDGPU_GEM_DOMAIN_GTT);
1416 
1417 	/* Avoid costly evictions; only set GTT as a busy placement */
1418 	abo->placement.num_busy_placement = 1;
1419 	abo->placement.busy_placement = &abo->placements[1];
1420 
1421 	r = ttm_bo_validate(bo, &abo->placement, &ctx);
1422 	if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1423 		return VM_FAULT_NOPAGE;
1424 	else if (unlikely(r))
1425 		return VM_FAULT_SIGBUS;
1426 
1427 	/* this should never happen */
1428 	if (bo->resource->mem_type == TTM_PL_VRAM &&
1429 	    !amdgpu_res_cpu_visible(adev, bo->resource))
1430 		return VM_FAULT_SIGBUS;
1431 
1432 	ttm_bo_move_to_lru_tail_unlocked(bo);
1433 	return 0;
1434 }
1435 
1436 /**
1437  * amdgpu_bo_fence - add fence to buffer object
1438  *
1439  * @bo: buffer object in question
1440  * @fence: fence to add
1441  * @shared: true if fence should be added shared
1442  *
1443  */
1444 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1445 		     bool shared)
1446 {
1447 	struct dma_resv *resv = bo->tbo.base.resv;
1448 	int r;
1449 
1450 	r = dma_resv_reserve_fences(resv, 1);
1451 	if (r) {
1452 		/* As last resort on OOM we block for the fence */
1453 		dma_fence_wait(fence, false);
1454 		return;
1455 	}
1456 
1457 	dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ :
1458 			   DMA_RESV_USAGE_WRITE);
1459 }
1460 
1461 /**
1462  * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1463  *
1464  * @adev: amdgpu device pointer
1465  * @resv: reservation object to sync to
1466  * @sync_mode: synchronization mode
1467  * @owner: fence owner
1468  * @intr: Whether the wait is interruptible
1469  *
1470  * Extract the fences from the reservation object and waits for them to finish.
1471  *
1472  * Returns:
1473  * 0 on success, errno otherwise.
1474  */
1475 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1476 			     enum amdgpu_sync_mode sync_mode, void *owner,
1477 			     bool intr)
1478 {
1479 	struct amdgpu_sync sync;
1480 	int r;
1481 
1482 	amdgpu_sync_create(&sync);
1483 	amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1484 	r = amdgpu_sync_wait(&sync, intr);
1485 	amdgpu_sync_free(&sync);
1486 	return r;
1487 }
1488 
1489 /**
1490  * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1491  * @bo: buffer object to wait for
1492  * @owner: fence owner
1493  * @intr: Whether the wait is interruptible
1494  *
1495  * Wrapper to wait for fences in a BO.
1496  * Returns:
1497  * 0 on success, errno otherwise.
1498  */
1499 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1500 {
1501 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1502 
1503 	return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1504 					AMDGPU_SYNC_NE_OWNER, owner, intr);
1505 }
1506 
1507 /**
1508  * amdgpu_bo_gpu_offset - return GPU offset of bo
1509  * @bo:	amdgpu object for which we query the offset
1510  *
1511  * Note: object should either be pinned or reserved when calling this
1512  * function, it might be useful to add check for this for debugging.
1513  *
1514  * Returns:
1515  * current GPU offset of the object.
1516  */
1517 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1518 {
1519 	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
1520 	WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1521 		     !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1522 	WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
1523 	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
1524 		     !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1525 
1526 	return amdgpu_bo_gpu_offset_no_check(bo);
1527 }
1528 
1529 /**
1530  * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1531  * @bo:	amdgpu object for which we query the offset
1532  *
1533  * Returns:
1534  * current GPU offset of the object without raising warnings.
1535  */
1536 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1537 {
1538 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1539 	uint64_t offset;
1540 
1541 	offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1542 		 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1543 
1544 	return amdgpu_gmc_sign_extend(offset);
1545 }
1546 
1547 /**
1548  * amdgpu_bo_get_preferred_domain - get preferred domain
1549  * @adev: amdgpu device object
1550  * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1551  *
1552  * Returns:
1553  * Which of the allowed domains is preferred for allocating the BO.
1554  */
1555 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
1556 					    uint32_t domain)
1557 {
1558 	if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
1559 	    ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
1560 		domain = AMDGPU_GEM_DOMAIN_VRAM;
1561 		if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1562 			domain = AMDGPU_GEM_DOMAIN_GTT;
1563 	}
1564 	return domain;
1565 }
1566 
1567 #if defined(CONFIG_DEBUG_FS)
1568 #define amdgpu_bo_print_flag(m, bo, flag)		        \
1569 	do {							\
1570 		if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) {	\
1571 			seq_printf((m), " " #flag);		\
1572 		}						\
1573 	} while (0)
1574 
1575 /**
1576  * amdgpu_bo_print_info - print BO info in debugfs file
1577  *
1578  * @id: Index or Id of the BO
1579  * @bo: Requested BO for printing info
1580  * @m: debugfs file
1581  *
1582  * Print BO information in debugfs file
1583  *
1584  * Returns:
1585  * Size of the BO in bytes.
1586  */
1587 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1588 {
1589 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1590 	struct dma_buf_attachment *attachment;
1591 	struct dma_buf *dma_buf;
1592 	const char *placement;
1593 	unsigned int pin_count;
1594 	u64 size;
1595 
1596 	if (dma_resv_trylock(bo->tbo.base.resv)) {
1597 		unsigned int domain;
1598 
1599 		domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1600 		switch (domain) {
1601 		case AMDGPU_GEM_DOMAIN_VRAM:
1602 			if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
1603 				placement = "VRAM VISIBLE";
1604 			else
1605 				placement = "VRAM";
1606 			break;
1607 		case AMDGPU_GEM_DOMAIN_GTT:
1608 			placement = "GTT";
1609 			break;
1610 		case AMDGPU_GEM_DOMAIN_CPU:
1611 		default:
1612 			placement = "CPU";
1613 			break;
1614 		}
1615 		dma_resv_unlock(bo->tbo.base.resv);
1616 	} else {
1617 		placement = "UNKNOWN";
1618 	}
1619 
1620 	size = amdgpu_bo_size(bo);
1621 	seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1622 			id, size, placement);
1623 
1624 	pin_count = READ_ONCE(bo->tbo.pin_count);
1625 	if (pin_count)
1626 		seq_printf(m, " pin count %d", pin_count);
1627 
1628 	dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1629 	attachment = READ_ONCE(bo->tbo.base.import_attach);
1630 
1631 	if (attachment)
1632 		seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino);
1633 	else if (dma_buf)
1634 		seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino);
1635 
1636 	amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1637 	amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1638 	amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1639 	amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1640 	amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1641 	amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1642 	amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
1643 
1644 	seq_puts(m, "\n");
1645 
1646 	return size;
1647 }
1648 #endif
1649