1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 59 60 amdgpu_bo_kunmap(bo); 61 62 if (bo->tbo.base.import_attach) 63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 64 drm_gem_object_release(&bo->tbo.base); 65 amdgpu_bo_unref(&bo->parent); 66 kvfree(bo); 67 } 68 69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 70 { 71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 72 struct amdgpu_bo_user *ubo; 73 74 ubo = to_amdgpu_bo_user(bo); 75 kfree(ubo->metadata); 76 amdgpu_bo_destroy(tbo); 77 } 78 79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 82 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 83 struct amdgpu_bo_vm *vmbo; 84 85 vmbo = to_amdgpu_bo_vm(bo); 86 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 87 if (!list_empty(&vmbo->shadow_list)) { 88 mutex_lock(&adev->shadow_list_lock); 89 list_del_init(&vmbo->shadow_list); 90 mutex_unlock(&adev->shadow_list_lock); 91 } 92 93 amdgpu_bo_destroy(tbo); 94 } 95 96 /** 97 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 98 * @bo: buffer object to be checked 99 * 100 * Uses destroy function associated with the object to determine if this is 101 * an &amdgpu_bo. 102 * 103 * Returns: 104 * true if the object belongs to &amdgpu_bo, false if not. 105 */ 106 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 107 { 108 if (bo->destroy == &amdgpu_bo_destroy || 109 bo->destroy == &amdgpu_bo_user_destroy || 110 bo->destroy == &amdgpu_bo_vm_destroy) 111 return true; 112 113 return false; 114 } 115 116 /** 117 * amdgpu_bo_placement_from_domain - set buffer's placement 118 * @abo: &amdgpu_bo buffer object whose placement is to be set 119 * @domain: requested domain 120 * 121 * Sets buffer's placement according to requested domain and the buffer's 122 * flags. 123 */ 124 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 125 { 126 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 127 struct ttm_placement *placement = &abo->placement; 128 struct ttm_place *places = abo->placements; 129 u64 flags = abo->flags; 130 u32 c = 0; 131 132 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 133 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 134 135 places[c].fpfn = 0; 136 places[c].lpfn = 0; 137 places[c].mem_type = TTM_PL_VRAM; 138 places[c].flags = 0; 139 140 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 141 places[c].lpfn = visible_pfn; 142 else 143 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 144 145 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 146 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 147 c++; 148 } 149 150 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 151 places[c].fpfn = 0; 152 places[c].lpfn = 0; 153 places[c].mem_type = 154 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 155 AMDGPU_PL_PREEMPT : TTM_PL_TT; 156 places[c].flags = 0; 157 c++; 158 } 159 160 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 161 places[c].fpfn = 0; 162 places[c].lpfn = 0; 163 places[c].mem_type = TTM_PL_SYSTEM; 164 places[c].flags = 0; 165 c++; 166 } 167 168 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 169 places[c].fpfn = 0; 170 places[c].lpfn = 0; 171 places[c].mem_type = AMDGPU_PL_GDS; 172 places[c].flags = 0; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].mem_type = AMDGPU_PL_GWS; 180 places[c].flags = 0; 181 c++; 182 } 183 184 if (domain & AMDGPU_GEM_DOMAIN_OA) { 185 places[c].fpfn = 0; 186 places[c].lpfn = 0; 187 places[c].mem_type = AMDGPU_PL_OA; 188 places[c].flags = 0; 189 c++; 190 } 191 192 if (!c) { 193 places[c].fpfn = 0; 194 places[c].lpfn = 0; 195 places[c].mem_type = TTM_PL_SYSTEM; 196 places[c].flags = 0; 197 c++; 198 } 199 200 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 201 202 placement->num_placement = c; 203 placement->placement = places; 204 205 placement->num_busy_placement = c; 206 placement->busy_placement = places; 207 } 208 209 /** 210 * amdgpu_bo_create_reserved - create reserved BO for kernel use 211 * 212 * @adev: amdgpu device object 213 * @size: size for the new BO 214 * @align: alignment for the new BO 215 * @domain: where to place it 216 * @bo_ptr: used to initialize BOs in structures 217 * @gpu_addr: GPU addr of the pinned BO 218 * @cpu_addr: optional CPU address mapping 219 * 220 * Allocates and pins a BO for kernel internal use, and returns it still 221 * reserved. 222 * 223 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 224 * 225 * Returns: 226 * 0 on success, negative error code otherwise. 227 */ 228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 229 unsigned long size, int align, 230 u32 domain, struct amdgpu_bo **bo_ptr, 231 u64 *gpu_addr, void **cpu_addr) 232 { 233 struct amdgpu_bo_param bp; 234 bool free = false; 235 int r; 236 237 if (!size) { 238 amdgpu_bo_unref(bo_ptr); 239 return 0; 240 } 241 242 memset(&bp, 0, sizeof(bp)); 243 bp.size = size; 244 bp.byte_align = align; 245 bp.domain = domain; 246 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 247 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 248 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 249 bp.type = ttm_bo_type_kernel; 250 bp.resv = NULL; 251 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 252 253 if (!*bo_ptr) { 254 r = amdgpu_bo_create(adev, &bp, bo_ptr); 255 if (r) { 256 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 257 r); 258 return r; 259 } 260 free = true; 261 } 262 263 r = amdgpu_bo_reserve(*bo_ptr, false); 264 if (r) { 265 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 266 goto error_free; 267 } 268 269 r = amdgpu_bo_pin(*bo_ptr, domain); 270 if (r) { 271 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 272 goto error_unreserve; 273 } 274 275 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 276 if (r) { 277 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 278 goto error_unpin; 279 } 280 281 if (gpu_addr) 282 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 283 284 if (cpu_addr) { 285 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 286 if (r) { 287 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 288 goto error_unpin; 289 } 290 } 291 292 return 0; 293 294 error_unpin: 295 amdgpu_bo_unpin(*bo_ptr); 296 error_unreserve: 297 amdgpu_bo_unreserve(*bo_ptr); 298 299 error_free: 300 if (free) 301 amdgpu_bo_unref(bo_ptr); 302 303 return r; 304 } 305 306 /** 307 * amdgpu_bo_create_kernel - create BO for kernel use 308 * 309 * @adev: amdgpu device object 310 * @size: size for the new BO 311 * @align: alignment for the new BO 312 * @domain: where to place it 313 * @bo_ptr: used to initialize BOs in structures 314 * @gpu_addr: GPU addr of the pinned BO 315 * @cpu_addr: optional CPU address mapping 316 * 317 * Allocates and pins a BO for kernel internal use. 318 * 319 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 320 * 321 * Returns: 322 * 0 on success, negative error code otherwise. 323 */ 324 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 325 unsigned long size, int align, 326 u32 domain, struct amdgpu_bo **bo_ptr, 327 u64 *gpu_addr, void **cpu_addr) 328 { 329 int r; 330 331 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 332 gpu_addr, cpu_addr); 333 334 if (r) 335 return r; 336 337 if (*bo_ptr) 338 amdgpu_bo_unreserve(*bo_ptr); 339 340 return 0; 341 } 342 343 /** 344 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 345 * 346 * @adev: amdgpu device object 347 * @offset: offset of the BO 348 * @size: size of the BO 349 * @domain: where to place it 350 * @bo_ptr: used to initialize BOs in structures 351 * @cpu_addr: optional CPU address mapping 352 * 353 * Creates a kernel BO at a specific offset in the address space of the domain. 354 * 355 * Returns: 356 * 0 on success, negative error code otherwise. 357 */ 358 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 359 uint64_t offset, uint64_t size, uint32_t domain, 360 struct amdgpu_bo **bo_ptr, void **cpu_addr) 361 { 362 struct ttm_operation_ctx ctx = { false, false }; 363 unsigned int i; 364 int r; 365 366 offset &= PAGE_MASK; 367 size = ALIGN(size, PAGE_SIZE); 368 369 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 370 NULL, cpu_addr); 371 if (r) 372 return r; 373 374 if ((*bo_ptr) == NULL) 375 return 0; 376 377 /* 378 * Remove the original mem node and create a new one at the request 379 * position. 380 */ 381 if (cpu_addr) 382 amdgpu_bo_kunmap(*bo_ptr); 383 384 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 385 386 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 387 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 388 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 389 } 390 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 391 &(*bo_ptr)->tbo.resource, &ctx); 392 if (r) 393 goto error; 394 395 if (cpu_addr) { 396 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 397 if (r) 398 goto error; 399 } 400 401 amdgpu_bo_unreserve(*bo_ptr); 402 return 0; 403 404 error: 405 amdgpu_bo_unreserve(*bo_ptr); 406 amdgpu_bo_unref(bo_ptr); 407 return r; 408 } 409 410 /** 411 * amdgpu_bo_free_kernel - free BO for kernel use 412 * 413 * @bo: amdgpu BO to free 414 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 415 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 416 * 417 * unmaps and unpin a BO for kernel internal use. 418 */ 419 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 420 void **cpu_addr) 421 { 422 if (*bo == NULL) 423 return; 424 425 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 426 if (cpu_addr) 427 amdgpu_bo_kunmap(*bo); 428 429 amdgpu_bo_unpin(*bo); 430 amdgpu_bo_unreserve(*bo); 431 } 432 amdgpu_bo_unref(bo); 433 434 if (gpu_addr) 435 *gpu_addr = 0; 436 437 if (cpu_addr) 438 *cpu_addr = NULL; 439 } 440 441 /* Validate bo size is bit bigger then the request domain */ 442 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 443 unsigned long size, u32 domain) 444 { 445 struct ttm_resource_manager *man = NULL; 446 447 /* 448 * If GTT is part of requested domains the check must succeed to 449 * allow fall back to GTT 450 */ 451 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 452 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 453 454 if (size < (man->size << PAGE_SHIFT)) 455 return true; 456 else 457 goto fail; 458 } 459 460 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 461 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 462 463 if (size < (man->size << PAGE_SHIFT)) 464 return true; 465 else 466 goto fail; 467 } 468 469 470 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 471 return true; 472 473 fail: 474 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 475 man->size << PAGE_SHIFT); 476 return false; 477 } 478 479 bool amdgpu_bo_support_uswc(u64 bo_flags) 480 { 481 482 #ifdef CONFIG_X86_32 483 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 484 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 485 */ 486 return false; 487 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 488 /* Don't try to enable write-combining when it can't work, or things 489 * may be slow 490 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 491 */ 492 493 #ifndef CONFIG_COMPILE_TEST 494 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 495 thanks to write-combining 496 #endif 497 498 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 499 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 500 "better performance thanks to write-combining\n"); 501 return false; 502 #else 503 /* For architectures that don't support WC memory, 504 * mask out the WC flag from the BO 505 */ 506 if (!drm_arch_can_wc_memory()) 507 return false; 508 509 return true; 510 #endif 511 } 512 513 /** 514 * amdgpu_bo_create - create an &amdgpu_bo buffer object 515 * @adev: amdgpu device object 516 * @bp: parameters to be used for the buffer object 517 * @bo_ptr: pointer to the buffer object pointer 518 * 519 * Creates an &amdgpu_bo buffer object. 520 * 521 * Returns: 522 * 0 for success or a negative error code on failure. 523 */ 524 int amdgpu_bo_create(struct amdgpu_device *adev, 525 struct amdgpu_bo_param *bp, 526 struct amdgpu_bo **bo_ptr) 527 { 528 struct ttm_operation_ctx ctx = { 529 .interruptible = (bp->type != ttm_bo_type_kernel), 530 .no_wait_gpu = bp->no_wait_gpu, 531 /* We opt to avoid OOM on system pages allocations */ 532 .gfp_retry_mayfail = true, 533 .allow_res_evict = bp->type != ttm_bo_type_kernel, 534 .resv = bp->resv 535 }; 536 struct amdgpu_bo *bo; 537 unsigned long page_align, size = bp->size; 538 int r; 539 540 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 541 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 542 /* GWS and OA don't need any alignment. */ 543 page_align = bp->byte_align; 544 size <<= PAGE_SHIFT; 545 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 546 /* Both size and alignment must be a multiple of 4. */ 547 page_align = ALIGN(bp->byte_align, 4); 548 size = ALIGN(size, 4) << PAGE_SHIFT; 549 } else { 550 /* Memory should be aligned at least to a page size. */ 551 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 552 size = ALIGN(size, PAGE_SIZE); 553 } 554 555 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 556 return -ENOMEM; 557 558 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 559 560 *bo_ptr = NULL; 561 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 562 if (bo == NULL) 563 return -ENOMEM; 564 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 565 bo->vm_bo = NULL; 566 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 567 bp->domain; 568 bo->allowed_domains = bo->preferred_domains; 569 if (bp->type != ttm_bo_type_kernel && 570 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 571 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 572 573 bo->flags = bp->flags; 574 575 if (!amdgpu_bo_support_uswc(bo->flags)) 576 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 577 578 bo->tbo.bdev = &adev->mman.bdev; 579 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 580 AMDGPU_GEM_DOMAIN_GDS)) 581 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 582 else 583 amdgpu_bo_placement_from_domain(bo, bp->domain); 584 if (bp->type == ttm_bo_type_kernel) 585 bo->tbo.priority = 1; 586 587 if (!bp->destroy) 588 bp->destroy = &amdgpu_bo_destroy; 589 590 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 591 &bo->placement, page_align, &ctx, NULL, 592 bp->resv, bp->destroy); 593 if (unlikely(r != 0)) 594 return r; 595 596 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 597 bo->tbo.resource->mem_type == TTM_PL_VRAM && 598 bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 599 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 600 ctx.bytes_moved); 601 else 602 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 603 604 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 605 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 606 struct dma_fence *fence; 607 608 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 609 if (unlikely(r)) 610 goto fail_unreserve; 611 612 amdgpu_bo_fence(bo, fence, false); 613 dma_fence_put(bo->tbo.moving); 614 bo->tbo.moving = dma_fence_get(fence); 615 dma_fence_put(fence); 616 } 617 if (!bp->resv) 618 amdgpu_bo_unreserve(bo); 619 *bo_ptr = bo; 620 621 trace_amdgpu_bo_create(bo); 622 623 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 624 if (bp->type == ttm_bo_type_device) 625 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 626 627 return 0; 628 629 fail_unreserve: 630 if (!bp->resv) 631 dma_resv_unlock(bo->tbo.base.resv); 632 amdgpu_bo_unref(&bo); 633 return r; 634 } 635 636 /** 637 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 638 * @adev: amdgpu device object 639 * @bp: parameters to be used for the buffer object 640 * @ubo_ptr: pointer to the buffer object pointer 641 * 642 * Create a BO to be used by user application; 643 * 644 * Returns: 645 * 0 for success or a negative error code on failure. 646 */ 647 648 int amdgpu_bo_create_user(struct amdgpu_device *adev, 649 struct amdgpu_bo_param *bp, 650 struct amdgpu_bo_user **ubo_ptr) 651 { 652 struct amdgpu_bo *bo_ptr; 653 int r; 654 655 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 656 bp->destroy = &amdgpu_bo_user_destroy; 657 r = amdgpu_bo_create(adev, bp, &bo_ptr); 658 if (r) 659 return r; 660 661 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 662 return r; 663 } 664 665 /** 666 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 667 * @adev: amdgpu device object 668 * @bp: parameters to be used for the buffer object 669 * @vmbo_ptr: pointer to the buffer object pointer 670 * 671 * Create a BO to be for GPUVM. 672 * 673 * Returns: 674 * 0 for success or a negative error code on failure. 675 */ 676 677 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 678 struct amdgpu_bo_param *bp, 679 struct amdgpu_bo_vm **vmbo_ptr) 680 { 681 struct amdgpu_bo *bo_ptr; 682 int r; 683 684 /* bo_ptr_size will be determined by the caller and it depends on 685 * num of amdgpu_vm_pt entries. 686 */ 687 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 688 bp->destroy = &amdgpu_bo_vm_destroy; 689 r = amdgpu_bo_create(adev, bp, &bo_ptr); 690 if (r) 691 return r; 692 693 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 694 INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list); 695 return r; 696 } 697 698 /** 699 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 700 * 701 * @vmbo: BO that will be inserted into the shadow list 702 * 703 * Insert a BO to the shadow list. 704 */ 705 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 706 { 707 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 708 709 mutex_lock(&adev->shadow_list_lock); 710 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 711 mutex_unlock(&adev->shadow_list_lock); 712 } 713 714 /** 715 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 716 * 717 * @shadow: &amdgpu_bo shadow to be restored 718 * @fence: dma_fence associated with the operation 719 * 720 * Copies a buffer object's shadow content back to the object. 721 * This is used for recovering a buffer from its shadow in case of a gpu 722 * reset where vram context may be lost. 723 * 724 * Returns: 725 * 0 for success or a negative error code on failure. 726 */ 727 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 728 729 { 730 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 731 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 732 uint64_t shadow_addr, parent_addr; 733 734 shadow_addr = amdgpu_bo_gpu_offset(shadow); 735 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 736 737 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 738 amdgpu_bo_size(shadow), NULL, fence, 739 true, false, false); 740 } 741 742 /** 743 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 744 * @bo: &amdgpu_bo buffer object to be mapped 745 * @ptr: kernel virtual address to be returned 746 * 747 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 748 * amdgpu_bo_kptr() to get the kernel virtual address. 749 * 750 * Returns: 751 * 0 for success or a negative error code on failure. 752 */ 753 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 754 { 755 void *kptr; 756 long r; 757 758 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 759 return -EPERM; 760 761 kptr = amdgpu_bo_kptr(bo); 762 if (kptr) { 763 if (ptr) 764 *ptr = kptr; 765 return 0; 766 } 767 768 r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false, 769 MAX_SCHEDULE_TIMEOUT); 770 if (r < 0) 771 return r; 772 773 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap); 774 if (r) 775 return r; 776 777 if (ptr) 778 *ptr = amdgpu_bo_kptr(bo); 779 780 return 0; 781 } 782 783 /** 784 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 785 * @bo: &amdgpu_bo buffer object 786 * 787 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 788 * 789 * Returns: 790 * the virtual address of a buffer object area. 791 */ 792 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 793 { 794 bool is_iomem; 795 796 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 797 } 798 799 /** 800 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 801 * @bo: &amdgpu_bo buffer object to be unmapped 802 * 803 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 804 */ 805 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 806 { 807 if (bo->kmap.bo) 808 ttm_bo_kunmap(&bo->kmap); 809 } 810 811 /** 812 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 813 * @bo: &amdgpu_bo buffer object 814 * 815 * References the contained &ttm_buffer_object. 816 * 817 * Returns: 818 * a refcounted pointer to the &amdgpu_bo buffer object. 819 */ 820 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 821 { 822 if (bo == NULL) 823 return NULL; 824 825 ttm_bo_get(&bo->tbo); 826 return bo; 827 } 828 829 /** 830 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 831 * @bo: &amdgpu_bo buffer object 832 * 833 * Unreferences the contained &ttm_buffer_object and clear the pointer 834 */ 835 void amdgpu_bo_unref(struct amdgpu_bo **bo) 836 { 837 struct ttm_buffer_object *tbo; 838 839 if ((*bo) == NULL) 840 return; 841 842 tbo = &((*bo)->tbo); 843 ttm_bo_put(tbo); 844 *bo = NULL; 845 } 846 847 /** 848 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 849 * @bo: &amdgpu_bo buffer object to be pinned 850 * @domain: domain to be pinned to 851 * @min_offset: the start of requested address range 852 * @max_offset: the end of requested address range 853 * 854 * Pins the buffer object according to requested domain and address range. If 855 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 856 * pin_count and pin_size accordingly. 857 * 858 * Pinning means to lock pages in memory along with keeping them at a fixed 859 * offset. It is required when a buffer can not be moved, for example, when 860 * a display buffer is being scanned out. 861 * 862 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 863 * where to pin a buffer if there are specific restrictions on where a buffer 864 * must be located. 865 * 866 * Returns: 867 * 0 for success or a negative error code on failure. 868 */ 869 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 870 u64 min_offset, u64 max_offset) 871 { 872 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 873 struct ttm_operation_ctx ctx = { false, false }; 874 int r, i; 875 876 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 877 return -EPERM; 878 879 if (WARN_ON_ONCE(min_offset > max_offset)) 880 return -EINVAL; 881 882 /* A shared bo cannot be migrated to VRAM */ 883 if (bo->tbo.base.import_attach) { 884 if (domain & AMDGPU_GEM_DOMAIN_GTT) 885 domain = AMDGPU_GEM_DOMAIN_GTT; 886 else 887 return -EINVAL; 888 } 889 890 if (bo->tbo.pin_count) { 891 uint32_t mem_type = bo->tbo.resource->mem_type; 892 uint32_t mem_flags = bo->tbo.resource->placement; 893 894 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 895 return -EINVAL; 896 897 if ((mem_type == TTM_PL_VRAM) && 898 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 899 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 900 return -EINVAL; 901 902 ttm_bo_pin(&bo->tbo); 903 904 if (max_offset != 0) { 905 u64 domain_start = amdgpu_ttm_domain_start(adev, 906 mem_type); 907 WARN_ON_ONCE(max_offset < 908 (amdgpu_bo_gpu_offset(bo) - domain_start)); 909 } 910 911 return 0; 912 } 913 914 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 915 * See function amdgpu_display_supported_domains() 916 */ 917 domain = amdgpu_bo_get_preferred_domain(adev, domain); 918 919 if (bo->tbo.base.import_attach) 920 dma_buf_pin(bo->tbo.base.import_attach); 921 922 /* force to pin into visible video ram */ 923 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 924 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 925 amdgpu_bo_placement_from_domain(bo, domain); 926 for (i = 0; i < bo->placement.num_placement; i++) { 927 unsigned fpfn, lpfn; 928 929 fpfn = min_offset >> PAGE_SHIFT; 930 lpfn = max_offset >> PAGE_SHIFT; 931 932 if (fpfn > bo->placements[i].fpfn) 933 bo->placements[i].fpfn = fpfn; 934 if (!bo->placements[i].lpfn || 935 (lpfn && lpfn < bo->placements[i].lpfn)) 936 bo->placements[i].lpfn = lpfn; 937 } 938 939 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 940 if (unlikely(r)) { 941 dev_err(adev->dev, "%p pin failed\n", bo); 942 goto error; 943 } 944 945 ttm_bo_pin(&bo->tbo); 946 947 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 948 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 949 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 950 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 951 &adev->visible_pin_size); 952 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 953 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 954 } 955 956 error: 957 return r; 958 } 959 960 /** 961 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 962 * @bo: &amdgpu_bo buffer object to be pinned 963 * @domain: domain to be pinned to 964 * 965 * A simple wrapper to amdgpu_bo_pin_restricted(). 966 * Provides a simpler API for buffers that do not have any strict restrictions 967 * on where a buffer must be located. 968 * 969 * Returns: 970 * 0 for success or a negative error code on failure. 971 */ 972 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 973 { 974 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 975 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 976 } 977 978 /** 979 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 980 * @bo: &amdgpu_bo buffer object to be unpinned 981 * 982 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 983 * Changes placement and pin size accordingly. 984 * 985 * Returns: 986 * 0 for success or a negative error code on failure. 987 */ 988 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 989 { 990 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 991 992 ttm_bo_unpin(&bo->tbo); 993 if (bo->tbo.pin_count) 994 return; 995 996 if (bo->tbo.base.import_attach) 997 dma_buf_unpin(bo->tbo.base.import_attach); 998 999 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1000 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1001 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1002 &adev->visible_pin_size); 1003 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1004 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1005 } 1006 } 1007 1008 static const char *amdgpu_vram_names[] = { 1009 "UNKNOWN", 1010 "GDDR1", 1011 "DDR2", 1012 "GDDR3", 1013 "GDDR4", 1014 "GDDR5", 1015 "HBM", 1016 "DDR3", 1017 "DDR4", 1018 "GDDR6", 1019 "DDR5" 1020 }; 1021 1022 /** 1023 * amdgpu_bo_init - initialize memory manager 1024 * @adev: amdgpu device object 1025 * 1026 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1027 * 1028 * Returns: 1029 * 0 for success or a negative error code on failure. 1030 */ 1031 int amdgpu_bo_init(struct amdgpu_device *adev) 1032 { 1033 /* On A+A platform, VRAM can be mapped as WB */ 1034 if (!adev->gmc.xgmi.connected_to_cpu) { 1035 /* reserve PAT memory space to WC for VRAM */ 1036 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1037 adev->gmc.aper_size); 1038 1039 if (r) { 1040 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1041 return r; 1042 } 1043 1044 /* Add an MTRR for the VRAM */ 1045 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1046 adev->gmc.aper_size); 1047 } 1048 1049 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1050 adev->gmc.mc_vram_size >> 20, 1051 (unsigned long long)adev->gmc.aper_size >> 20); 1052 DRM_INFO("RAM width %dbits %s\n", 1053 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1054 return amdgpu_ttm_init(adev); 1055 } 1056 1057 /** 1058 * amdgpu_bo_fini - tear down memory manager 1059 * @adev: amdgpu device object 1060 * 1061 * Reverses amdgpu_bo_init() to tear down memory manager. 1062 */ 1063 void amdgpu_bo_fini(struct amdgpu_device *adev) 1064 { 1065 int idx; 1066 1067 amdgpu_ttm_fini(adev); 1068 1069 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1070 1071 if (!adev->gmc.xgmi.connected_to_cpu) { 1072 arch_phys_wc_del(adev->gmc.vram_mtrr); 1073 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1074 } 1075 drm_dev_exit(idx); 1076 } 1077 } 1078 1079 /** 1080 * amdgpu_bo_set_tiling_flags - set tiling flags 1081 * @bo: &amdgpu_bo buffer object 1082 * @tiling_flags: new flags 1083 * 1084 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1085 * kernel driver to set the tiling flags on a buffer. 1086 * 1087 * Returns: 1088 * 0 for success or a negative error code on failure. 1089 */ 1090 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1091 { 1092 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1093 struct amdgpu_bo_user *ubo; 1094 1095 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1096 if (adev->family <= AMDGPU_FAMILY_CZ && 1097 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1098 return -EINVAL; 1099 1100 ubo = to_amdgpu_bo_user(bo); 1101 ubo->tiling_flags = tiling_flags; 1102 return 0; 1103 } 1104 1105 /** 1106 * amdgpu_bo_get_tiling_flags - get tiling flags 1107 * @bo: &amdgpu_bo buffer object 1108 * @tiling_flags: returned flags 1109 * 1110 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1111 * set the tiling flags on a buffer. 1112 */ 1113 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1114 { 1115 struct amdgpu_bo_user *ubo; 1116 1117 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1118 dma_resv_assert_held(bo->tbo.base.resv); 1119 ubo = to_amdgpu_bo_user(bo); 1120 1121 if (tiling_flags) 1122 *tiling_flags = ubo->tiling_flags; 1123 } 1124 1125 /** 1126 * amdgpu_bo_set_metadata - set metadata 1127 * @bo: &amdgpu_bo buffer object 1128 * @metadata: new metadata 1129 * @metadata_size: size of the new metadata 1130 * @flags: flags of the new metadata 1131 * 1132 * Sets buffer object's metadata, its size and flags. 1133 * Used via GEM ioctl. 1134 * 1135 * Returns: 1136 * 0 for success or a negative error code on failure. 1137 */ 1138 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1139 uint32_t metadata_size, uint64_t flags) 1140 { 1141 struct amdgpu_bo_user *ubo; 1142 void *buffer; 1143 1144 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1145 ubo = to_amdgpu_bo_user(bo); 1146 if (!metadata_size) { 1147 if (ubo->metadata_size) { 1148 kfree(ubo->metadata); 1149 ubo->metadata = NULL; 1150 ubo->metadata_size = 0; 1151 } 1152 return 0; 1153 } 1154 1155 if (metadata == NULL) 1156 return -EINVAL; 1157 1158 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1159 if (buffer == NULL) 1160 return -ENOMEM; 1161 1162 kfree(ubo->metadata); 1163 ubo->metadata_flags = flags; 1164 ubo->metadata = buffer; 1165 ubo->metadata_size = metadata_size; 1166 1167 return 0; 1168 } 1169 1170 /** 1171 * amdgpu_bo_get_metadata - get metadata 1172 * @bo: &amdgpu_bo buffer object 1173 * @buffer: returned metadata 1174 * @buffer_size: size of the buffer 1175 * @metadata_size: size of the returned metadata 1176 * @flags: flags of the returned metadata 1177 * 1178 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1179 * less than metadata_size. 1180 * Used via GEM ioctl. 1181 * 1182 * Returns: 1183 * 0 for success or a negative error code on failure. 1184 */ 1185 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1186 size_t buffer_size, uint32_t *metadata_size, 1187 uint64_t *flags) 1188 { 1189 struct amdgpu_bo_user *ubo; 1190 1191 if (!buffer && !metadata_size) 1192 return -EINVAL; 1193 1194 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1195 ubo = to_amdgpu_bo_user(bo); 1196 if (metadata_size) 1197 *metadata_size = ubo->metadata_size; 1198 1199 if (buffer) { 1200 if (buffer_size < ubo->metadata_size) 1201 return -EINVAL; 1202 1203 if (ubo->metadata_size) 1204 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1205 } 1206 1207 if (flags) 1208 *flags = ubo->metadata_flags; 1209 1210 return 0; 1211 } 1212 1213 /** 1214 * amdgpu_bo_move_notify - notification about a memory move 1215 * @bo: pointer to a buffer object 1216 * @evict: if this move is evicting the buffer from the graphics address space 1217 * @new_mem: new information of the bufer object 1218 * 1219 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1220 * bookkeeping. 1221 * TTM driver callback which is called when ttm moves a buffer. 1222 */ 1223 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1224 bool evict, 1225 struct ttm_resource *new_mem) 1226 { 1227 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1228 struct amdgpu_bo *abo; 1229 struct ttm_resource *old_mem = bo->resource; 1230 1231 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1232 return; 1233 1234 abo = ttm_to_amdgpu_bo(bo); 1235 amdgpu_vm_bo_invalidate(adev, abo, evict); 1236 1237 amdgpu_bo_kunmap(abo); 1238 1239 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1240 bo->resource->mem_type != TTM_PL_SYSTEM) 1241 dma_buf_move_notify(abo->tbo.base.dma_buf); 1242 1243 /* remember the eviction */ 1244 if (evict) 1245 atomic64_inc(&adev->num_evictions); 1246 1247 /* update statistics */ 1248 if (!new_mem) 1249 return; 1250 1251 /* move_notify is called before move happens */ 1252 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1253 } 1254 1255 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, 1256 uint64_t *gtt_mem, uint64_t *cpu_mem) 1257 { 1258 unsigned int domain; 1259 1260 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1261 switch (domain) { 1262 case AMDGPU_GEM_DOMAIN_VRAM: 1263 *vram_mem += amdgpu_bo_size(bo); 1264 break; 1265 case AMDGPU_GEM_DOMAIN_GTT: 1266 *gtt_mem += amdgpu_bo_size(bo); 1267 break; 1268 case AMDGPU_GEM_DOMAIN_CPU: 1269 default: 1270 *cpu_mem += amdgpu_bo_size(bo); 1271 break; 1272 } 1273 } 1274 1275 /** 1276 * amdgpu_bo_release_notify - notification about a BO being released 1277 * @bo: pointer to a buffer object 1278 * 1279 * Wipes VRAM buffers whose contents should not be leaked before the 1280 * memory is released. 1281 */ 1282 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1283 { 1284 struct dma_fence *fence = NULL; 1285 struct amdgpu_bo *abo; 1286 int r; 1287 1288 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1289 return; 1290 1291 abo = ttm_to_amdgpu_bo(bo); 1292 1293 if (abo->kfd_bo) 1294 amdgpu_amdkfd_release_notify(abo); 1295 1296 /* We only remove the fence if the resv has individualized. */ 1297 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1298 && bo->base.resv != &bo->base._resv); 1299 if (bo->base.resv == &bo->base._resv) 1300 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1301 1302 if (bo->resource->mem_type != TTM_PL_VRAM || 1303 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1304 return; 1305 1306 dma_resv_lock(bo->base.resv, NULL); 1307 1308 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1309 if (!WARN_ON(r)) { 1310 amdgpu_bo_fence(abo, fence, false); 1311 dma_fence_put(fence); 1312 } 1313 1314 dma_resv_unlock(bo->base.resv); 1315 } 1316 1317 /** 1318 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1319 * @bo: pointer to a buffer object 1320 * 1321 * Notifies the driver we are taking a fault on this BO and have reserved it, 1322 * also performs bookkeeping. 1323 * TTM driver callback for dealing with vm faults. 1324 * 1325 * Returns: 1326 * 0 for success or a negative error code on failure. 1327 */ 1328 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1329 { 1330 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1331 struct ttm_operation_ctx ctx = { false, false }; 1332 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1333 unsigned long offset; 1334 int r; 1335 1336 /* Remember that this BO was accessed by the CPU */ 1337 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1338 1339 if (bo->resource->mem_type != TTM_PL_VRAM) 1340 return 0; 1341 1342 offset = bo->resource->start << PAGE_SHIFT; 1343 if ((offset + bo->base.size) <= adev->gmc.visible_vram_size) 1344 return 0; 1345 1346 /* Can't move a pinned BO to visible VRAM */ 1347 if (abo->tbo.pin_count > 0) 1348 return VM_FAULT_SIGBUS; 1349 1350 /* hurrah the memory is not visible ! */ 1351 atomic64_inc(&adev->num_vram_cpu_page_faults); 1352 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1353 AMDGPU_GEM_DOMAIN_GTT); 1354 1355 /* Avoid costly evictions; only set GTT as a busy placement */ 1356 abo->placement.num_busy_placement = 1; 1357 abo->placement.busy_placement = &abo->placements[1]; 1358 1359 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1360 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1361 return VM_FAULT_NOPAGE; 1362 else if (unlikely(r)) 1363 return VM_FAULT_SIGBUS; 1364 1365 offset = bo->resource->start << PAGE_SHIFT; 1366 /* this should never happen */ 1367 if (bo->resource->mem_type == TTM_PL_VRAM && 1368 (offset + bo->base.size) > adev->gmc.visible_vram_size) 1369 return VM_FAULT_SIGBUS; 1370 1371 ttm_bo_move_to_lru_tail_unlocked(bo); 1372 return 0; 1373 } 1374 1375 /** 1376 * amdgpu_bo_fence - add fence to buffer object 1377 * 1378 * @bo: buffer object in question 1379 * @fence: fence to add 1380 * @shared: true if fence should be added shared 1381 * 1382 */ 1383 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1384 bool shared) 1385 { 1386 struct dma_resv *resv = bo->tbo.base.resv; 1387 1388 if (shared) 1389 dma_resv_add_shared_fence(resv, fence); 1390 else 1391 dma_resv_add_excl_fence(resv, fence); 1392 } 1393 1394 /** 1395 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1396 * 1397 * @adev: amdgpu device pointer 1398 * @resv: reservation object to sync to 1399 * @sync_mode: synchronization mode 1400 * @owner: fence owner 1401 * @intr: Whether the wait is interruptible 1402 * 1403 * Extract the fences from the reservation object and waits for them to finish. 1404 * 1405 * Returns: 1406 * 0 on success, errno otherwise. 1407 */ 1408 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1409 enum amdgpu_sync_mode sync_mode, void *owner, 1410 bool intr) 1411 { 1412 struct amdgpu_sync sync; 1413 int r; 1414 1415 amdgpu_sync_create(&sync); 1416 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1417 r = amdgpu_sync_wait(&sync, intr); 1418 amdgpu_sync_free(&sync); 1419 return r; 1420 } 1421 1422 /** 1423 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1424 * @bo: buffer object to wait for 1425 * @owner: fence owner 1426 * @intr: Whether the wait is interruptible 1427 * 1428 * Wrapper to wait for fences in a BO. 1429 * Returns: 1430 * 0 on success, errno otherwise. 1431 */ 1432 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1433 { 1434 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1435 1436 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1437 AMDGPU_SYNC_NE_OWNER, owner, intr); 1438 } 1439 1440 /** 1441 * amdgpu_bo_gpu_offset - return GPU offset of bo 1442 * @bo: amdgpu object for which we query the offset 1443 * 1444 * Note: object should either be pinned or reserved when calling this 1445 * function, it might be useful to add check for this for debugging. 1446 * 1447 * Returns: 1448 * current GPU offset of the object. 1449 */ 1450 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1451 { 1452 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1453 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1454 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1455 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1456 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1457 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1458 1459 return amdgpu_bo_gpu_offset_no_check(bo); 1460 } 1461 1462 /** 1463 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1464 * @bo: amdgpu object for which we query the offset 1465 * 1466 * Returns: 1467 * current GPU offset of the object without raising warnings. 1468 */ 1469 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1470 { 1471 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1472 uint64_t offset; 1473 1474 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1475 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1476 1477 return amdgpu_gmc_sign_extend(offset); 1478 } 1479 1480 /** 1481 * amdgpu_bo_get_preferred_domain - get preferred domain 1482 * @adev: amdgpu device object 1483 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1484 * 1485 * Returns: 1486 * Which of the allowed domains is preferred for allocating the BO. 1487 */ 1488 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1489 uint32_t domain) 1490 { 1491 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1492 domain = AMDGPU_GEM_DOMAIN_VRAM; 1493 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1494 domain = AMDGPU_GEM_DOMAIN_GTT; 1495 } 1496 return domain; 1497 } 1498 1499 #if defined(CONFIG_DEBUG_FS) 1500 #define amdgpu_bo_print_flag(m, bo, flag) \ 1501 do { \ 1502 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1503 seq_printf((m), " " #flag); \ 1504 } \ 1505 } while (0) 1506 1507 /** 1508 * amdgpu_bo_print_info - print BO info in debugfs file 1509 * 1510 * @id: Index or Id of the BO 1511 * @bo: Requested BO for printing info 1512 * @m: debugfs file 1513 * 1514 * Print BO information in debugfs file 1515 * 1516 * Returns: 1517 * Size of the BO in bytes. 1518 */ 1519 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1520 { 1521 struct dma_buf_attachment *attachment; 1522 struct dma_buf *dma_buf; 1523 unsigned int domain; 1524 const char *placement; 1525 unsigned int pin_count; 1526 u64 size; 1527 1528 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1529 switch (domain) { 1530 case AMDGPU_GEM_DOMAIN_VRAM: 1531 placement = "VRAM"; 1532 break; 1533 case AMDGPU_GEM_DOMAIN_GTT: 1534 placement = " GTT"; 1535 break; 1536 case AMDGPU_GEM_DOMAIN_CPU: 1537 default: 1538 placement = " CPU"; 1539 break; 1540 } 1541 1542 size = amdgpu_bo_size(bo); 1543 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1544 id, size, placement); 1545 1546 pin_count = READ_ONCE(bo->tbo.pin_count); 1547 if (pin_count) 1548 seq_printf(m, " pin count %d", pin_count); 1549 1550 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1551 attachment = READ_ONCE(bo->tbo.base.import_attach); 1552 1553 if (attachment) 1554 seq_printf(m, " imported from %p", dma_buf); 1555 else if (dma_buf) 1556 seq_printf(m, " exported as %p", dma_buf); 1557 1558 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1559 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1560 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1561 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1562 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1563 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1564 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1565 1566 seq_puts(m, "\n"); 1567 1568 return size; 1569 } 1570 #endif 1571