1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * DOC: amdgpu_object 43 * 44 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 45 * represents memory used by driver (VRAM, system memory, etc.). The driver 46 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 47 * to create/destroy/set buffer object which are then managed by the kernel TTM 48 * memory manager. 49 * The interfaces are also used internally by kernel clients, including gfx, 50 * uvd, etc. for kernel managed allocations used by the GPU. 51 * 52 */ 53 54 /** 55 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 56 * 57 * @bo: &amdgpu_bo buffer object 58 * 59 * This function is called when a BO stops being pinned, and updates the 60 * &amdgpu_device pin_size values accordingly. 61 */ 62 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 63 { 64 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 65 66 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 67 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 68 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 69 &adev->visible_pin_size); 70 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 71 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 72 } 73 } 74 75 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 76 { 77 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 78 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 79 80 if (bo->pin_count > 0) 81 amdgpu_bo_subtract_pin_size(bo); 82 83 amdgpu_bo_kunmap(bo); 84 85 if (bo->tbo.base.import_attach) 86 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 87 drm_gem_object_release(&bo->tbo.base); 88 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 89 if (!list_empty(&bo->shadow_list)) { 90 mutex_lock(&adev->shadow_list_lock); 91 list_del_init(&bo->shadow_list); 92 mutex_unlock(&adev->shadow_list_lock); 93 } 94 amdgpu_bo_unref(&bo->parent); 95 96 kfree(bo->metadata); 97 kfree(bo); 98 } 99 100 /** 101 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 102 * @bo: buffer object to be checked 103 * 104 * Uses destroy function associated with the object to determine if this is 105 * an &amdgpu_bo. 106 * 107 * Returns: 108 * true if the object belongs to &amdgpu_bo, false if not. 109 */ 110 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 111 { 112 if (bo->destroy == &amdgpu_bo_destroy) 113 return true; 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 136 places[c].fpfn = 0; 137 places[c].lpfn = 0; 138 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 139 TTM_PL_FLAG_VRAM; 140 141 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 142 places[c].lpfn = visible_pfn; 143 else 144 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 145 146 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 147 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 148 c++; 149 } 150 151 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 152 places[c].fpfn = 0; 153 places[c].lpfn = 0; 154 places[c].flags = TTM_PL_FLAG_TT; 155 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 156 places[c].flags |= TTM_PL_FLAG_WC | 157 TTM_PL_FLAG_UNCACHED; 158 else 159 places[c].flags |= TTM_PL_FLAG_CACHED; 160 c++; 161 } 162 163 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 164 places[c].fpfn = 0; 165 places[c].lpfn = 0; 166 places[c].flags = TTM_PL_FLAG_SYSTEM; 167 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 168 places[c].flags |= TTM_PL_FLAG_WC | 169 TTM_PL_FLAG_UNCACHED; 170 else 171 places[c].flags |= TTM_PL_FLAG_CACHED; 172 c++; 173 } 174 175 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 176 places[c].fpfn = 0; 177 places[c].lpfn = 0; 178 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 179 c++; 180 } 181 182 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 183 places[c].fpfn = 0; 184 places[c].lpfn = 0; 185 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 186 c++; 187 } 188 189 if (domain & AMDGPU_GEM_DOMAIN_OA) { 190 places[c].fpfn = 0; 191 places[c].lpfn = 0; 192 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 193 c++; 194 } 195 196 if (!c) { 197 places[c].fpfn = 0; 198 places[c].lpfn = 0; 199 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 200 c++; 201 } 202 203 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 204 205 placement->num_placement = c; 206 placement->placement = places; 207 208 placement->num_busy_placement = c; 209 placement->busy_placement = places; 210 } 211 212 /** 213 * amdgpu_bo_create_reserved - create reserved BO for kernel use 214 * 215 * @adev: amdgpu device object 216 * @size: size for the new BO 217 * @align: alignment for the new BO 218 * @domain: where to place it 219 * @bo_ptr: used to initialize BOs in structures 220 * @gpu_addr: GPU addr of the pinned BO 221 * @cpu_addr: optional CPU address mapping 222 * 223 * Allocates and pins a BO for kernel internal use, and returns it still 224 * reserved. 225 * 226 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 227 * 228 * Returns: 229 * 0 on success, negative error code otherwise. 230 */ 231 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 232 unsigned long size, int align, 233 u32 domain, struct amdgpu_bo **bo_ptr, 234 u64 *gpu_addr, void **cpu_addr) 235 { 236 struct amdgpu_bo_param bp; 237 bool free = false; 238 int r; 239 240 if (!size) { 241 amdgpu_bo_unref(bo_ptr); 242 return 0; 243 } 244 245 memset(&bp, 0, sizeof(bp)); 246 bp.size = size; 247 bp.byte_align = align; 248 bp.domain = domain; 249 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 250 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 251 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 252 bp.type = ttm_bo_type_kernel; 253 bp.resv = NULL; 254 255 if (!*bo_ptr) { 256 r = amdgpu_bo_create(adev, &bp, bo_ptr); 257 if (r) { 258 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 259 r); 260 return r; 261 } 262 free = true; 263 } 264 265 r = amdgpu_bo_reserve(*bo_ptr, false); 266 if (r) { 267 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 268 goto error_free; 269 } 270 271 r = amdgpu_bo_pin(*bo_ptr, domain); 272 if (r) { 273 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 274 goto error_unreserve; 275 } 276 277 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 278 if (r) { 279 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 280 goto error_unpin; 281 } 282 283 if (gpu_addr) 284 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 285 286 if (cpu_addr) { 287 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 288 if (r) { 289 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 290 goto error_unpin; 291 } 292 } 293 294 return 0; 295 296 error_unpin: 297 amdgpu_bo_unpin(*bo_ptr); 298 error_unreserve: 299 amdgpu_bo_unreserve(*bo_ptr); 300 301 error_free: 302 if (free) 303 amdgpu_bo_unref(bo_ptr); 304 305 return r; 306 } 307 308 /** 309 * amdgpu_bo_create_kernel - create BO for kernel use 310 * 311 * @adev: amdgpu device object 312 * @size: size for the new BO 313 * @align: alignment for the new BO 314 * @domain: where to place it 315 * @bo_ptr: used to initialize BOs in structures 316 * @gpu_addr: GPU addr of the pinned BO 317 * @cpu_addr: optional CPU address mapping 318 * 319 * Allocates and pins a BO for kernel internal use. 320 * 321 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 322 * 323 * Returns: 324 * 0 on success, negative error code otherwise. 325 */ 326 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 327 unsigned long size, int align, 328 u32 domain, struct amdgpu_bo **bo_ptr, 329 u64 *gpu_addr, void **cpu_addr) 330 { 331 int r; 332 333 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 334 gpu_addr, cpu_addr); 335 336 if (r) 337 return r; 338 339 if (*bo_ptr) 340 amdgpu_bo_unreserve(*bo_ptr); 341 342 return 0; 343 } 344 345 /** 346 * amdgpu_bo_free_kernel - free BO for kernel use 347 * 348 * @bo: amdgpu BO to free 349 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 350 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 351 * 352 * unmaps and unpin a BO for kernel internal use. 353 */ 354 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 355 void **cpu_addr) 356 { 357 if (*bo == NULL) 358 return; 359 360 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 361 if (cpu_addr) 362 amdgpu_bo_kunmap(*bo); 363 364 amdgpu_bo_unpin(*bo); 365 amdgpu_bo_unreserve(*bo); 366 } 367 amdgpu_bo_unref(bo); 368 369 if (gpu_addr) 370 *gpu_addr = 0; 371 372 if (cpu_addr) 373 *cpu_addr = NULL; 374 } 375 376 /* Validate bo size is bit bigger then the request domain */ 377 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 378 unsigned long size, u32 domain) 379 { 380 struct ttm_mem_type_manager *man = NULL; 381 382 /* 383 * If GTT is part of requested domains the check must succeed to 384 * allow fall back to GTT 385 */ 386 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 387 man = &adev->mman.bdev.man[TTM_PL_TT]; 388 389 if (size < (man->size << PAGE_SHIFT)) 390 return true; 391 else 392 goto fail; 393 } 394 395 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 396 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 397 398 if (size < (man->size << PAGE_SHIFT)) 399 return true; 400 else 401 goto fail; 402 } 403 404 405 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 406 return true; 407 408 fail: 409 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 410 man->size << PAGE_SHIFT); 411 return false; 412 } 413 414 bool amdgpu_bo_support_uswc(u64 bo_flags) 415 { 416 417 #ifdef CONFIG_X86_32 418 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 419 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 420 */ 421 return false; 422 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 423 /* Don't try to enable write-combining when it can't work, or things 424 * may be slow 425 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 426 */ 427 428 #ifndef CONFIG_COMPILE_TEST 429 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 430 thanks to write-combining 431 #endif 432 433 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 434 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 435 "better performance thanks to write-combining\n"); 436 return false; 437 #else 438 /* For architectures that don't support WC memory, 439 * mask out the WC flag from the BO 440 */ 441 if (!drm_arch_can_wc_memory()) 442 return false; 443 444 return true; 445 #endif 446 } 447 448 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 449 struct amdgpu_bo_param *bp, 450 struct amdgpu_bo **bo_ptr) 451 { 452 struct ttm_operation_ctx ctx = { 453 .interruptible = (bp->type != ttm_bo_type_kernel), 454 .no_wait_gpu = false, 455 .resv = bp->resv, 456 .flags = bp->type != ttm_bo_type_kernel ? 457 TTM_OPT_FLAG_ALLOW_RES_EVICT : 0 458 }; 459 struct amdgpu_bo *bo; 460 unsigned long page_align, size = bp->size; 461 size_t acc_size; 462 int r; 463 464 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 465 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 466 /* GWS and OA don't need any alignment. */ 467 page_align = bp->byte_align; 468 size <<= PAGE_SHIFT; 469 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 470 /* Both size and alignment must be a multiple of 4. */ 471 page_align = ALIGN(bp->byte_align, 4); 472 size = ALIGN(size, 4) << PAGE_SHIFT; 473 } else { 474 /* Memory should be aligned at least to a page size. */ 475 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 476 size = ALIGN(size, PAGE_SIZE); 477 } 478 479 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 480 return -ENOMEM; 481 482 *bo_ptr = NULL; 483 484 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 485 sizeof(struct amdgpu_bo)); 486 487 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 488 if (bo == NULL) 489 return -ENOMEM; 490 drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size); 491 INIT_LIST_HEAD(&bo->shadow_list); 492 bo->vm_bo = NULL; 493 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 494 bp->domain; 495 bo->allowed_domains = bo->preferred_domains; 496 if (bp->type != ttm_bo_type_kernel && 497 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 498 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 499 500 bo->flags = bp->flags; 501 502 if (!amdgpu_bo_support_uswc(bo->flags)) 503 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 504 505 bo->tbo.bdev = &adev->mman.bdev; 506 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 507 AMDGPU_GEM_DOMAIN_GDS)) 508 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 509 else 510 amdgpu_bo_placement_from_domain(bo, bp->domain); 511 if (bp->type == ttm_bo_type_kernel) 512 bo->tbo.priority = 1; 513 514 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 515 &bo->placement, page_align, &ctx, acc_size, 516 NULL, bp->resv, &amdgpu_bo_destroy); 517 if (unlikely(r != 0)) 518 return r; 519 520 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 521 bo->tbo.mem.mem_type == TTM_PL_VRAM && 522 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 523 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 524 ctx.bytes_moved); 525 else 526 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 527 528 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 529 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 530 struct dma_fence *fence; 531 532 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 533 if (unlikely(r)) 534 goto fail_unreserve; 535 536 amdgpu_bo_fence(bo, fence, false); 537 dma_fence_put(bo->tbo.moving); 538 bo->tbo.moving = dma_fence_get(fence); 539 dma_fence_put(fence); 540 } 541 if (!bp->resv) 542 amdgpu_bo_unreserve(bo); 543 *bo_ptr = bo; 544 545 trace_amdgpu_bo_create(bo); 546 547 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 548 if (bp->type == ttm_bo_type_device) 549 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 550 551 return 0; 552 553 fail_unreserve: 554 if (!bp->resv) 555 dma_resv_unlock(bo->tbo.base.resv); 556 amdgpu_bo_unref(&bo); 557 return r; 558 } 559 560 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 561 unsigned long size, 562 struct amdgpu_bo *bo) 563 { 564 struct amdgpu_bo_param bp; 565 int r; 566 567 if (bo->shadow) 568 return 0; 569 570 memset(&bp, 0, sizeof(bp)); 571 bp.size = size; 572 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 573 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 574 AMDGPU_GEM_CREATE_SHADOW; 575 bp.type = ttm_bo_type_kernel; 576 bp.resv = bo->tbo.base.resv; 577 578 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 579 if (!r) { 580 bo->shadow->parent = amdgpu_bo_ref(bo); 581 mutex_lock(&adev->shadow_list_lock); 582 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 583 mutex_unlock(&adev->shadow_list_lock); 584 } 585 586 return r; 587 } 588 589 /** 590 * amdgpu_bo_create - create an &amdgpu_bo buffer object 591 * @adev: amdgpu device object 592 * @bp: parameters to be used for the buffer object 593 * @bo_ptr: pointer to the buffer object pointer 594 * 595 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 596 * shadow object. 597 * Shadow object is used to backup the original buffer object, and is always 598 * in GTT. 599 * 600 * Returns: 601 * 0 for success or a negative error code on failure. 602 */ 603 int amdgpu_bo_create(struct amdgpu_device *adev, 604 struct amdgpu_bo_param *bp, 605 struct amdgpu_bo **bo_ptr) 606 { 607 u64 flags = bp->flags; 608 int r; 609 610 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 611 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 612 if (r) 613 return r; 614 615 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 616 if (!bp->resv) 617 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 618 NULL)); 619 620 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 621 622 if (!bp->resv) 623 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 624 625 if (r) 626 amdgpu_bo_unref(bo_ptr); 627 } 628 629 return r; 630 } 631 632 /** 633 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 634 * @bo: pointer to the buffer object 635 * 636 * Sets placement according to domain; and changes placement and caching 637 * policy of the buffer object according to the placement. 638 * This is used for validating shadow bos. It calls ttm_bo_validate() to 639 * make sure the buffer is resident where it needs to be. 640 * 641 * Returns: 642 * 0 for success or a negative error code on failure. 643 */ 644 int amdgpu_bo_validate(struct amdgpu_bo *bo) 645 { 646 struct ttm_operation_ctx ctx = { false, false }; 647 uint32_t domain; 648 int r; 649 650 if (bo->pin_count) 651 return 0; 652 653 domain = bo->preferred_domains; 654 655 retry: 656 amdgpu_bo_placement_from_domain(bo, domain); 657 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 658 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 659 domain = bo->allowed_domains; 660 goto retry; 661 } 662 663 return r; 664 } 665 666 /** 667 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 668 * 669 * @shadow: &amdgpu_bo shadow to be restored 670 * @fence: dma_fence associated with the operation 671 * 672 * Copies a buffer object's shadow content back to the object. 673 * This is used for recovering a buffer from its shadow in case of a gpu 674 * reset where vram context may be lost. 675 * 676 * Returns: 677 * 0 for success or a negative error code on failure. 678 */ 679 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 680 681 { 682 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 683 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 684 uint64_t shadow_addr, parent_addr; 685 686 shadow_addr = amdgpu_bo_gpu_offset(shadow); 687 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 688 689 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 690 amdgpu_bo_size(shadow), NULL, fence, 691 true, false); 692 } 693 694 /** 695 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 696 * @bo: &amdgpu_bo buffer object to be mapped 697 * @ptr: kernel virtual address to be returned 698 * 699 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 700 * amdgpu_bo_kptr() to get the kernel virtual address. 701 * 702 * Returns: 703 * 0 for success or a negative error code on failure. 704 */ 705 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 706 { 707 void *kptr; 708 long r; 709 710 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 711 return -EPERM; 712 713 kptr = amdgpu_bo_kptr(bo); 714 if (kptr) { 715 if (ptr) 716 *ptr = kptr; 717 return 0; 718 } 719 720 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 721 MAX_SCHEDULE_TIMEOUT); 722 if (r < 0) 723 return r; 724 725 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 726 if (r) 727 return r; 728 729 if (ptr) 730 *ptr = amdgpu_bo_kptr(bo); 731 732 return 0; 733 } 734 735 /** 736 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 737 * @bo: &amdgpu_bo buffer object 738 * 739 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 740 * 741 * Returns: 742 * the virtual address of a buffer object area. 743 */ 744 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 745 { 746 bool is_iomem; 747 748 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 749 } 750 751 /** 752 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 753 * @bo: &amdgpu_bo buffer object to be unmapped 754 * 755 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 756 */ 757 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 758 { 759 if (bo->kmap.bo) 760 ttm_bo_kunmap(&bo->kmap); 761 } 762 763 /** 764 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 765 * @bo: &amdgpu_bo buffer object 766 * 767 * References the contained &ttm_buffer_object. 768 * 769 * Returns: 770 * a refcounted pointer to the &amdgpu_bo buffer object. 771 */ 772 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 773 { 774 if (bo == NULL) 775 return NULL; 776 777 ttm_bo_get(&bo->tbo); 778 return bo; 779 } 780 781 /** 782 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 783 * @bo: &amdgpu_bo buffer object 784 * 785 * Unreferences the contained &ttm_buffer_object and clear the pointer 786 */ 787 void amdgpu_bo_unref(struct amdgpu_bo **bo) 788 { 789 struct ttm_buffer_object *tbo; 790 791 if ((*bo) == NULL) 792 return; 793 794 tbo = &((*bo)->tbo); 795 ttm_bo_put(tbo); 796 *bo = NULL; 797 } 798 799 /** 800 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 801 * @bo: &amdgpu_bo buffer object to be pinned 802 * @domain: domain to be pinned to 803 * @min_offset: the start of requested address range 804 * @max_offset: the end of requested address range 805 * 806 * Pins the buffer object according to requested domain and address range. If 807 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 808 * pin_count and pin_size accordingly. 809 * 810 * Pinning means to lock pages in memory along with keeping them at a fixed 811 * offset. It is required when a buffer can not be moved, for example, when 812 * a display buffer is being scanned out. 813 * 814 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 815 * where to pin a buffer if there are specific restrictions on where a buffer 816 * must be located. 817 * 818 * Returns: 819 * 0 for success or a negative error code on failure. 820 */ 821 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 822 u64 min_offset, u64 max_offset) 823 { 824 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 825 struct ttm_operation_ctx ctx = { false, false }; 826 int r, i; 827 828 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 829 return -EPERM; 830 831 if (WARN_ON_ONCE(min_offset > max_offset)) 832 return -EINVAL; 833 834 /* A shared bo cannot be migrated to VRAM */ 835 if (bo->prime_shared_count) { 836 if (domain & AMDGPU_GEM_DOMAIN_GTT) 837 domain = AMDGPU_GEM_DOMAIN_GTT; 838 else 839 return -EINVAL; 840 } 841 842 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 843 * See function amdgpu_display_supported_domains() 844 */ 845 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 846 847 if (bo->pin_count) { 848 uint32_t mem_type = bo->tbo.mem.mem_type; 849 850 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 851 return -EINVAL; 852 853 bo->pin_count++; 854 855 if (max_offset != 0) { 856 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 857 WARN_ON_ONCE(max_offset < 858 (amdgpu_bo_gpu_offset(bo) - domain_start)); 859 } 860 861 return 0; 862 } 863 864 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 865 /* force to pin into visible video ram */ 866 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 867 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 868 amdgpu_bo_placement_from_domain(bo, domain); 869 for (i = 0; i < bo->placement.num_placement; i++) { 870 unsigned fpfn, lpfn; 871 872 fpfn = min_offset >> PAGE_SHIFT; 873 lpfn = max_offset >> PAGE_SHIFT; 874 875 if (fpfn > bo->placements[i].fpfn) 876 bo->placements[i].fpfn = fpfn; 877 if (!bo->placements[i].lpfn || 878 (lpfn && lpfn < bo->placements[i].lpfn)) 879 bo->placements[i].lpfn = lpfn; 880 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 881 } 882 883 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 884 if (unlikely(r)) { 885 dev_err(adev->dev, "%p pin failed\n", bo); 886 goto error; 887 } 888 889 bo->pin_count = 1; 890 891 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 892 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 893 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 894 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 895 &adev->visible_pin_size); 896 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 897 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 898 } 899 900 error: 901 return r; 902 } 903 904 /** 905 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 906 * @bo: &amdgpu_bo buffer object to be pinned 907 * @domain: domain to be pinned to 908 * 909 * A simple wrapper to amdgpu_bo_pin_restricted(). 910 * Provides a simpler API for buffers that do not have any strict restrictions 911 * on where a buffer must be located. 912 * 913 * Returns: 914 * 0 for success or a negative error code on failure. 915 */ 916 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 917 { 918 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 919 } 920 921 /** 922 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 923 * @bo: &amdgpu_bo buffer object to be unpinned 924 * 925 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 926 * Changes placement and pin size accordingly. 927 * 928 * Returns: 929 * 0 for success or a negative error code on failure. 930 */ 931 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 932 { 933 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 934 struct ttm_operation_ctx ctx = { false, false }; 935 int r, i; 936 937 if (WARN_ON_ONCE(!bo->pin_count)) { 938 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 939 return 0; 940 } 941 bo->pin_count--; 942 if (bo->pin_count) 943 return 0; 944 945 amdgpu_bo_subtract_pin_size(bo); 946 947 for (i = 0; i < bo->placement.num_placement; i++) { 948 bo->placements[i].lpfn = 0; 949 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 950 } 951 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 952 if (unlikely(r)) 953 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 954 955 return r; 956 } 957 958 /** 959 * amdgpu_bo_evict_vram - evict VRAM buffers 960 * @adev: amdgpu device object 961 * 962 * Evicts all VRAM buffers on the lru list of the memory type. 963 * Mainly used for evicting vram at suspend time. 964 * 965 * Returns: 966 * 0 for success or a negative error code on failure. 967 */ 968 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 969 { 970 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 971 #ifndef CONFIG_HIBERNATION 972 if (adev->flags & AMD_IS_APU) { 973 /* Useless to evict on IGP chips */ 974 return 0; 975 } 976 #endif 977 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 978 } 979 980 static const char *amdgpu_vram_names[] = { 981 "UNKNOWN", 982 "GDDR1", 983 "DDR2", 984 "GDDR3", 985 "GDDR4", 986 "GDDR5", 987 "HBM", 988 "DDR3", 989 "DDR4", 990 "GDDR6", 991 }; 992 993 /** 994 * amdgpu_bo_init - initialize memory manager 995 * @adev: amdgpu device object 996 * 997 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 998 * 999 * Returns: 1000 * 0 for success or a negative error code on failure. 1001 */ 1002 int amdgpu_bo_init(struct amdgpu_device *adev) 1003 { 1004 /* reserve PAT memory space to WC for VRAM */ 1005 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1006 adev->gmc.aper_size); 1007 1008 /* Add an MTRR for the VRAM */ 1009 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1010 adev->gmc.aper_size); 1011 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1012 adev->gmc.mc_vram_size >> 20, 1013 (unsigned long long)adev->gmc.aper_size >> 20); 1014 DRM_INFO("RAM width %dbits %s\n", 1015 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1016 return amdgpu_ttm_init(adev); 1017 } 1018 1019 /** 1020 * amdgpu_bo_late_init - late init 1021 * @adev: amdgpu device object 1022 * 1023 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1024 * initialization. 1025 * 1026 * Returns: 1027 * 0 for success or a negative error code on failure. 1028 */ 1029 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1030 { 1031 amdgpu_ttm_late_init(adev); 1032 1033 return 0; 1034 } 1035 1036 /** 1037 * amdgpu_bo_fini - tear down memory manager 1038 * @adev: amdgpu device object 1039 * 1040 * Reverses amdgpu_bo_init() to tear down memory manager. 1041 */ 1042 void amdgpu_bo_fini(struct amdgpu_device *adev) 1043 { 1044 amdgpu_ttm_fini(adev); 1045 arch_phys_wc_del(adev->gmc.vram_mtrr); 1046 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1047 } 1048 1049 /** 1050 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1051 * @bo: &amdgpu_bo buffer object 1052 * @vma: vma as input from the fbdev mmap method 1053 * 1054 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1055 * 1056 * Returns: 1057 * 0 for success or a negative error code on failure. 1058 */ 1059 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1060 struct vm_area_struct *vma) 1061 { 1062 return ttm_fbdev_mmap(vma, &bo->tbo); 1063 } 1064 1065 /** 1066 * amdgpu_bo_set_tiling_flags - set tiling flags 1067 * @bo: &amdgpu_bo buffer object 1068 * @tiling_flags: new flags 1069 * 1070 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1071 * kernel driver to set the tiling flags on a buffer. 1072 * 1073 * Returns: 1074 * 0 for success or a negative error code on failure. 1075 */ 1076 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1077 { 1078 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1079 1080 if (adev->family <= AMDGPU_FAMILY_CZ && 1081 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1082 return -EINVAL; 1083 1084 bo->tiling_flags = tiling_flags; 1085 return 0; 1086 } 1087 1088 /** 1089 * amdgpu_bo_get_tiling_flags - get tiling flags 1090 * @bo: &amdgpu_bo buffer object 1091 * @tiling_flags: returned flags 1092 * 1093 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1094 * set the tiling flags on a buffer. 1095 */ 1096 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1097 { 1098 dma_resv_assert_held(bo->tbo.base.resv); 1099 1100 if (tiling_flags) 1101 *tiling_flags = bo->tiling_flags; 1102 } 1103 1104 /** 1105 * amdgpu_bo_set_metadata - set metadata 1106 * @bo: &amdgpu_bo buffer object 1107 * @metadata: new metadata 1108 * @metadata_size: size of the new metadata 1109 * @flags: flags of the new metadata 1110 * 1111 * Sets buffer object's metadata, its size and flags. 1112 * Used via GEM ioctl. 1113 * 1114 * Returns: 1115 * 0 for success or a negative error code on failure. 1116 */ 1117 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1118 uint32_t metadata_size, uint64_t flags) 1119 { 1120 void *buffer; 1121 1122 if (!metadata_size) { 1123 if (bo->metadata_size) { 1124 kfree(bo->metadata); 1125 bo->metadata = NULL; 1126 bo->metadata_size = 0; 1127 } 1128 return 0; 1129 } 1130 1131 if (metadata == NULL) 1132 return -EINVAL; 1133 1134 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1135 if (buffer == NULL) 1136 return -ENOMEM; 1137 1138 kfree(bo->metadata); 1139 bo->metadata_flags = flags; 1140 bo->metadata = buffer; 1141 bo->metadata_size = metadata_size; 1142 1143 return 0; 1144 } 1145 1146 /** 1147 * amdgpu_bo_get_metadata - get metadata 1148 * @bo: &amdgpu_bo buffer object 1149 * @buffer: returned metadata 1150 * @buffer_size: size of the buffer 1151 * @metadata_size: size of the returned metadata 1152 * @flags: flags of the returned metadata 1153 * 1154 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1155 * less than metadata_size. 1156 * Used via GEM ioctl. 1157 * 1158 * Returns: 1159 * 0 for success or a negative error code on failure. 1160 */ 1161 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1162 size_t buffer_size, uint32_t *metadata_size, 1163 uint64_t *flags) 1164 { 1165 if (!buffer && !metadata_size) 1166 return -EINVAL; 1167 1168 if (buffer) { 1169 if (buffer_size < bo->metadata_size) 1170 return -EINVAL; 1171 1172 if (bo->metadata_size) 1173 memcpy(buffer, bo->metadata, bo->metadata_size); 1174 } 1175 1176 if (metadata_size) 1177 *metadata_size = bo->metadata_size; 1178 if (flags) 1179 *flags = bo->metadata_flags; 1180 1181 return 0; 1182 } 1183 1184 /** 1185 * amdgpu_bo_move_notify - notification about a memory move 1186 * @bo: pointer to a buffer object 1187 * @evict: if this move is evicting the buffer from the graphics address space 1188 * @new_mem: new information of the bufer object 1189 * 1190 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1191 * bookkeeping. 1192 * TTM driver callback which is called when ttm moves a buffer. 1193 */ 1194 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1195 bool evict, 1196 struct ttm_mem_reg *new_mem) 1197 { 1198 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1199 struct amdgpu_bo *abo; 1200 struct ttm_mem_reg *old_mem = &bo->mem; 1201 1202 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1203 return; 1204 1205 abo = ttm_to_amdgpu_bo(bo); 1206 amdgpu_vm_bo_invalidate(adev, abo, evict); 1207 1208 amdgpu_bo_kunmap(abo); 1209 1210 /* remember the eviction */ 1211 if (evict) 1212 atomic64_inc(&adev->num_evictions); 1213 1214 /* update statistics */ 1215 if (!new_mem) 1216 return; 1217 1218 /* move_notify is called before move happens */ 1219 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1220 } 1221 1222 /** 1223 * amdgpu_bo_move_notify - notification about a BO being released 1224 * @bo: pointer to a buffer object 1225 * 1226 * Wipes VRAM buffers whose contents should not be leaked before the 1227 * memory is released. 1228 */ 1229 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1230 { 1231 struct dma_fence *fence = NULL; 1232 struct amdgpu_bo *abo; 1233 int r; 1234 1235 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1236 return; 1237 1238 abo = ttm_to_amdgpu_bo(bo); 1239 1240 if (abo->kfd_bo) 1241 amdgpu_amdkfd_unreserve_memory_limit(abo); 1242 1243 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1244 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1245 return; 1246 1247 dma_resv_lock(bo->base.resv, NULL); 1248 1249 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1250 if (!WARN_ON(r)) { 1251 amdgpu_bo_fence(abo, fence, false); 1252 dma_fence_put(fence); 1253 } 1254 1255 dma_resv_unlock(bo->base.resv); 1256 } 1257 1258 /** 1259 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1260 * @bo: pointer to a buffer object 1261 * 1262 * Notifies the driver we are taking a fault on this BO and have reserved it, 1263 * also performs bookkeeping. 1264 * TTM driver callback for dealing with vm faults. 1265 * 1266 * Returns: 1267 * 0 for success or a negative error code on failure. 1268 */ 1269 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1270 { 1271 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1272 struct ttm_operation_ctx ctx = { false, false }; 1273 struct amdgpu_bo *abo; 1274 unsigned long offset, size; 1275 int r; 1276 1277 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1278 return 0; 1279 1280 abo = ttm_to_amdgpu_bo(bo); 1281 1282 /* Remember that this BO was accessed by the CPU */ 1283 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1284 1285 if (bo->mem.mem_type != TTM_PL_VRAM) 1286 return 0; 1287 1288 size = bo->mem.num_pages << PAGE_SHIFT; 1289 offset = bo->mem.start << PAGE_SHIFT; 1290 if ((offset + size) <= adev->gmc.visible_vram_size) 1291 return 0; 1292 1293 /* Can't move a pinned BO to visible VRAM */ 1294 if (abo->pin_count > 0) 1295 return -EINVAL; 1296 1297 /* hurrah the memory is not visible ! */ 1298 atomic64_inc(&adev->num_vram_cpu_page_faults); 1299 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1300 AMDGPU_GEM_DOMAIN_GTT); 1301 1302 /* Avoid costly evictions; only set GTT as a busy placement */ 1303 abo->placement.num_busy_placement = 1; 1304 abo->placement.busy_placement = &abo->placements[1]; 1305 1306 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1307 if (unlikely(r != 0)) 1308 return r; 1309 1310 offset = bo->mem.start << PAGE_SHIFT; 1311 /* this should never happen */ 1312 if (bo->mem.mem_type == TTM_PL_VRAM && 1313 (offset + size) > adev->gmc.visible_vram_size) 1314 return -EINVAL; 1315 1316 return 0; 1317 } 1318 1319 /** 1320 * amdgpu_bo_fence - add fence to buffer object 1321 * 1322 * @bo: buffer object in question 1323 * @fence: fence to add 1324 * @shared: true if fence should be added shared 1325 * 1326 */ 1327 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1328 bool shared) 1329 { 1330 struct dma_resv *resv = bo->tbo.base.resv; 1331 1332 if (shared) 1333 dma_resv_add_shared_fence(resv, fence); 1334 else 1335 dma_resv_add_excl_fence(resv, fence); 1336 } 1337 1338 /** 1339 * amdgpu_sync_wait_resv - Wait for BO reservation fences 1340 * 1341 * @bo: buffer object 1342 * @owner: fence owner 1343 * @intr: Whether the wait is interruptible 1344 * 1345 * Returns: 1346 * 0 on success, errno otherwise. 1347 */ 1348 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1349 { 1350 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1351 struct amdgpu_sync sync; 1352 int r; 1353 1354 amdgpu_sync_create(&sync); 1355 amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, owner, false); 1356 r = amdgpu_sync_wait(&sync, intr); 1357 amdgpu_sync_free(&sync); 1358 1359 return r; 1360 } 1361 1362 /** 1363 * amdgpu_bo_gpu_offset - return GPU offset of bo 1364 * @bo: amdgpu object for which we query the offset 1365 * 1366 * Note: object should either be pinned or reserved when calling this 1367 * function, it might be useful to add check for this for debugging. 1368 * 1369 * Returns: 1370 * current GPU offset of the object. 1371 */ 1372 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1373 { 1374 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1375 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1376 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); 1377 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1378 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1379 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1380 1381 return amdgpu_gmc_sign_extend(bo->tbo.offset); 1382 } 1383 1384 /** 1385 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1386 * @adev: amdgpu device object 1387 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1388 * 1389 * Returns: 1390 * Which of the allowed domains is preferred for pinning the BO for scanout. 1391 */ 1392 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1393 uint32_t domain) 1394 { 1395 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1396 domain = AMDGPU_GEM_DOMAIN_VRAM; 1397 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1398 domain = AMDGPU_GEM_DOMAIN_GTT; 1399 } 1400 return domain; 1401 } 1402