1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/amdgpu_drm.h> 37 #include <drm/drm_cache.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 #include "amdgpu_amdkfd.h" 41 42 /** 43 * DOC: amdgpu_object 44 * 45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 46 * represents memory used by driver (VRAM, system memory, etc.). The driver 47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 48 * to create/destroy/set buffer object which are then managed by the kernel TTM 49 * memory manager. 50 * The interfaces are also used internally by kernel clients, including gfx, 51 * uvd, etc. for kernel managed allocations used by the GPU. 52 * 53 */ 54 55 /** 56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 57 * 58 * @bo: &amdgpu_bo buffer object 59 * 60 * This function is called when a BO stops being pinned, and updates the 61 * &amdgpu_device pin_size values accordingly. 62 */ 63 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 64 { 65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 66 67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 70 &adev->visible_pin_size); 71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 73 } 74 } 75 76 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 77 { 78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 80 81 if (bo->tbo.pin_count > 0) 82 amdgpu_bo_subtract_pin_size(bo); 83 84 amdgpu_bo_kunmap(bo); 85 86 if (bo->tbo.base.import_attach) 87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 88 drm_gem_object_release(&bo->tbo.base); 89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 90 if (!list_empty(&bo->shadow_list)) { 91 mutex_lock(&adev->shadow_list_lock); 92 list_del_init(&bo->shadow_list); 93 mutex_unlock(&adev->shadow_list_lock); 94 } 95 amdgpu_bo_unref(&bo->parent); 96 97 kfree(bo->metadata); 98 kfree(bo); 99 } 100 101 /** 102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 103 * @bo: buffer object to be checked 104 * 105 * Uses destroy function associated with the object to determine if this is 106 * an &amdgpu_bo. 107 * 108 * Returns: 109 * true if the object belongs to &amdgpu_bo, false if not. 110 */ 111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 112 { 113 if (bo->destroy == &amdgpu_bo_destroy) 114 return true; 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 137 places[c].fpfn = 0; 138 places[c].lpfn = 0; 139 places[c].mem_type = TTM_PL_VRAM; 140 places[c].flags = 0; 141 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 places[c].lpfn = visible_pfn; 144 else 145 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 146 147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 149 c++; 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 places[c].fpfn = 0; 154 places[c].lpfn = 0; 155 places[c].mem_type = TTM_PL_TT; 156 places[c].flags = 0; 157 c++; 158 } 159 160 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 161 places[c].fpfn = 0; 162 places[c].lpfn = 0; 163 places[c].mem_type = TTM_PL_SYSTEM; 164 places[c].flags = 0; 165 c++; 166 } 167 168 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 169 places[c].fpfn = 0; 170 places[c].lpfn = 0; 171 places[c].mem_type = AMDGPU_PL_GDS; 172 places[c].flags = 0; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].mem_type = AMDGPU_PL_GWS; 180 places[c].flags = 0; 181 c++; 182 } 183 184 if (domain & AMDGPU_GEM_DOMAIN_OA) { 185 places[c].fpfn = 0; 186 places[c].lpfn = 0; 187 places[c].mem_type = AMDGPU_PL_OA; 188 places[c].flags = 0; 189 c++; 190 } 191 192 if (!c) { 193 places[c].fpfn = 0; 194 places[c].lpfn = 0; 195 places[c].mem_type = TTM_PL_SYSTEM; 196 places[c].flags = 0; 197 c++; 198 } 199 200 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 201 202 placement->num_placement = c; 203 placement->placement = places; 204 205 placement->num_busy_placement = c; 206 placement->busy_placement = places; 207 } 208 209 /** 210 * amdgpu_bo_create_reserved - create reserved BO for kernel use 211 * 212 * @adev: amdgpu device object 213 * @size: size for the new BO 214 * @align: alignment for the new BO 215 * @domain: where to place it 216 * @bo_ptr: used to initialize BOs in structures 217 * @gpu_addr: GPU addr of the pinned BO 218 * @cpu_addr: optional CPU address mapping 219 * 220 * Allocates and pins a BO for kernel internal use, and returns it still 221 * reserved. 222 * 223 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 224 * 225 * Returns: 226 * 0 on success, negative error code otherwise. 227 */ 228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 229 unsigned long size, int align, 230 u32 domain, struct amdgpu_bo **bo_ptr, 231 u64 *gpu_addr, void **cpu_addr) 232 { 233 struct amdgpu_bo_param bp; 234 bool free = false; 235 int r; 236 237 if (!size) { 238 amdgpu_bo_unref(bo_ptr); 239 return 0; 240 } 241 242 memset(&bp, 0, sizeof(bp)); 243 bp.size = size; 244 bp.byte_align = align; 245 bp.domain = domain; 246 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 247 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 248 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 249 bp.type = ttm_bo_type_kernel; 250 bp.resv = NULL; 251 252 if (!*bo_ptr) { 253 r = amdgpu_bo_create(adev, &bp, bo_ptr); 254 if (r) { 255 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 256 r); 257 return r; 258 } 259 free = true; 260 } 261 262 r = amdgpu_bo_reserve(*bo_ptr, false); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 265 goto error_free; 266 } 267 268 r = amdgpu_bo_pin(*bo_ptr, domain); 269 if (r) { 270 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 271 goto error_unreserve; 272 } 273 274 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 275 if (r) { 276 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 277 goto error_unpin; 278 } 279 280 if (gpu_addr) 281 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 282 283 if (cpu_addr) { 284 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 285 if (r) { 286 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 287 goto error_unpin; 288 } 289 } 290 291 return 0; 292 293 error_unpin: 294 amdgpu_bo_unpin(*bo_ptr); 295 error_unreserve: 296 amdgpu_bo_unreserve(*bo_ptr); 297 298 error_free: 299 if (free) 300 amdgpu_bo_unref(bo_ptr); 301 302 return r; 303 } 304 305 /** 306 * amdgpu_bo_create_kernel - create BO for kernel use 307 * 308 * @adev: amdgpu device object 309 * @size: size for the new BO 310 * @align: alignment for the new BO 311 * @domain: where to place it 312 * @bo_ptr: used to initialize BOs in structures 313 * @gpu_addr: GPU addr of the pinned BO 314 * @cpu_addr: optional CPU address mapping 315 * 316 * Allocates and pins a BO for kernel internal use. 317 * 318 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 319 * 320 * Returns: 321 * 0 on success, negative error code otherwise. 322 */ 323 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 324 unsigned long size, int align, 325 u32 domain, struct amdgpu_bo **bo_ptr, 326 u64 *gpu_addr, void **cpu_addr) 327 { 328 int r; 329 330 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 331 gpu_addr, cpu_addr); 332 333 if (r) 334 return r; 335 336 if (*bo_ptr) 337 amdgpu_bo_unreserve(*bo_ptr); 338 339 return 0; 340 } 341 342 /** 343 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 344 * 345 * @adev: amdgpu device object 346 * @offset: offset of the BO 347 * @size: size of the BO 348 * @domain: where to place it 349 * @bo_ptr: used to initialize BOs in structures 350 * @cpu_addr: optional CPU address mapping 351 * 352 * Creates a kernel BO at a specific offset in the address space of the domain. 353 * 354 * Returns: 355 * 0 on success, negative error code otherwise. 356 */ 357 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 358 uint64_t offset, uint64_t size, uint32_t domain, 359 struct amdgpu_bo **bo_ptr, void **cpu_addr) 360 { 361 struct ttm_operation_ctx ctx = { false, false }; 362 unsigned int i; 363 int r; 364 365 offset &= PAGE_MASK; 366 size = ALIGN(size, PAGE_SIZE); 367 368 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 369 NULL, cpu_addr); 370 if (r) 371 return r; 372 373 if ((*bo_ptr) == NULL) 374 return 0; 375 376 /* 377 * Remove the original mem node and create a new one at the request 378 * position. 379 */ 380 if (cpu_addr) 381 amdgpu_bo_kunmap(*bo_ptr); 382 383 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); 384 385 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 386 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 387 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 388 } 389 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 390 &(*bo_ptr)->tbo.mem, &ctx); 391 if (r) 392 goto error; 393 394 if (cpu_addr) { 395 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 396 if (r) 397 goto error; 398 } 399 400 amdgpu_bo_unreserve(*bo_ptr); 401 return 0; 402 403 error: 404 amdgpu_bo_unreserve(*bo_ptr); 405 amdgpu_bo_unref(bo_ptr); 406 return r; 407 } 408 409 /** 410 * amdgpu_bo_free_kernel - free BO for kernel use 411 * 412 * @bo: amdgpu BO to free 413 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 414 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 415 * 416 * unmaps and unpin a BO for kernel internal use. 417 */ 418 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 419 void **cpu_addr) 420 { 421 if (*bo == NULL) 422 return; 423 424 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 425 if (cpu_addr) 426 amdgpu_bo_kunmap(*bo); 427 428 amdgpu_bo_unpin(*bo); 429 amdgpu_bo_unreserve(*bo); 430 } 431 amdgpu_bo_unref(bo); 432 433 if (gpu_addr) 434 *gpu_addr = 0; 435 436 if (cpu_addr) 437 *cpu_addr = NULL; 438 } 439 440 /* Validate bo size is bit bigger then the request domain */ 441 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 442 unsigned long size, u32 domain) 443 { 444 struct ttm_resource_manager *man = NULL; 445 446 /* 447 * If GTT is part of requested domains the check must succeed to 448 * allow fall back to GTT 449 */ 450 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 451 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 452 453 if (size < (man->size << PAGE_SHIFT)) 454 return true; 455 else 456 goto fail; 457 } 458 459 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 460 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 461 462 if (size < (man->size << PAGE_SHIFT)) 463 return true; 464 else 465 goto fail; 466 } 467 468 469 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 470 return true; 471 472 fail: 473 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 474 man->size << PAGE_SHIFT); 475 return false; 476 } 477 478 bool amdgpu_bo_support_uswc(u64 bo_flags) 479 { 480 481 #ifdef CONFIG_X86_32 482 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 483 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 484 */ 485 return false; 486 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 487 /* Don't try to enable write-combining when it can't work, or things 488 * may be slow 489 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 490 */ 491 492 #ifndef CONFIG_COMPILE_TEST 493 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 494 thanks to write-combining 495 #endif 496 497 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 498 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 499 "better performance thanks to write-combining\n"); 500 return false; 501 #else 502 /* For architectures that don't support WC memory, 503 * mask out the WC flag from the BO 504 */ 505 if (!drm_arch_can_wc_memory()) 506 return false; 507 508 return true; 509 #endif 510 } 511 512 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 513 struct amdgpu_bo_param *bp, 514 struct amdgpu_bo **bo_ptr) 515 { 516 struct ttm_operation_ctx ctx = { 517 .interruptible = (bp->type != ttm_bo_type_kernel), 518 .no_wait_gpu = bp->no_wait_gpu, 519 .resv = bp->resv, 520 .flags = bp->type != ttm_bo_type_kernel ? 521 TTM_OPT_FLAG_ALLOW_RES_EVICT : 0 522 }; 523 struct amdgpu_bo *bo; 524 unsigned long page_align, size = bp->size; 525 size_t acc_size; 526 int r; 527 528 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 529 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 530 /* GWS and OA don't need any alignment. */ 531 page_align = bp->byte_align; 532 size <<= PAGE_SHIFT; 533 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 534 /* Both size and alignment must be a multiple of 4. */ 535 page_align = ALIGN(bp->byte_align, 4); 536 size = ALIGN(size, 4) << PAGE_SHIFT; 537 } else { 538 /* Memory should be aligned at least to a page size. */ 539 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 540 size = ALIGN(size, PAGE_SIZE); 541 } 542 543 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 544 return -ENOMEM; 545 546 *bo_ptr = NULL; 547 548 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 549 sizeof(struct amdgpu_bo)); 550 551 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 552 if (bo == NULL) 553 return -ENOMEM; 554 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 555 INIT_LIST_HEAD(&bo->shadow_list); 556 bo->vm_bo = NULL; 557 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 558 bp->domain; 559 bo->allowed_domains = bo->preferred_domains; 560 if (bp->type != ttm_bo_type_kernel && 561 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 562 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 563 564 bo->flags = bp->flags; 565 566 if (!amdgpu_bo_support_uswc(bo->flags)) 567 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 568 569 bo->tbo.bdev = &adev->mman.bdev; 570 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 571 AMDGPU_GEM_DOMAIN_GDS)) 572 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 573 else 574 amdgpu_bo_placement_from_domain(bo, bp->domain); 575 if (bp->type == ttm_bo_type_kernel) 576 bo->tbo.priority = 1; 577 578 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 579 &bo->placement, page_align, &ctx, acc_size, 580 NULL, bp->resv, &amdgpu_bo_destroy); 581 if (unlikely(r != 0)) 582 return r; 583 584 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 585 bo->tbo.mem.mem_type == TTM_PL_VRAM && 586 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 587 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 588 ctx.bytes_moved); 589 else 590 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 591 592 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 593 bo->tbo.mem.mem_type == TTM_PL_VRAM) { 594 struct dma_fence *fence; 595 596 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 597 if (unlikely(r)) 598 goto fail_unreserve; 599 600 amdgpu_bo_fence(bo, fence, false); 601 dma_fence_put(bo->tbo.moving); 602 bo->tbo.moving = dma_fence_get(fence); 603 dma_fence_put(fence); 604 } 605 if (!bp->resv) 606 amdgpu_bo_unreserve(bo); 607 *bo_ptr = bo; 608 609 trace_amdgpu_bo_create(bo); 610 611 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 612 if (bp->type == ttm_bo_type_device) 613 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 614 615 return 0; 616 617 fail_unreserve: 618 if (!bp->resv) 619 dma_resv_unlock(bo->tbo.base.resv); 620 amdgpu_bo_unref(&bo); 621 return r; 622 } 623 624 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 625 unsigned long size, 626 struct amdgpu_bo *bo) 627 { 628 struct amdgpu_bo_param bp; 629 int r; 630 631 if (bo->shadow) 632 return 0; 633 634 memset(&bp, 0, sizeof(bp)); 635 bp.size = size; 636 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 637 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 638 AMDGPU_GEM_CREATE_SHADOW; 639 bp.type = ttm_bo_type_kernel; 640 bp.resv = bo->tbo.base.resv; 641 642 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 643 if (!r) { 644 bo->shadow->parent = amdgpu_bo_ref(bo); 645 mutex_lock(&adev->shadow_list_lock); 646 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 647 mutex_unlock(&adev->shadow_list_lock); 648 } 649 650 return r; 651 } 652 653 /** 654 * amdgpu_bo_create - create an &amdgpu_bo buffer object 655 * @adev: amdgpu device object 656 * @bp: parameters to be used for the buffer object 657 * @bo_ptr: pointer to the buffer object pointer 658 * 659 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 660 * shadow object. 661 * Shadow object is used to backup the original buffer object, and is always 662 * in GTT. 663 * 664 * Returns: 665 * 0 for success or a negative error code on failure. 666 */ 667 int amdgpu_bo_create(struct amdgpu_device *adev, 668 struct amdgpu_bo_param *bp, 669 struct amdgpu_bo **bo_ptr) 670 { 671 u64 flags = bp->flags; 672 int r; 673 674 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 675 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 676 if (r) 677 return r; 678 679 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 680 if (!bp->resv) 681 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 682 NULL)); 683 684 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 685 686 if (!bp->resv) 687 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 688 689 if (r) 690 amdgpu_bo_unref(bo_ptr); 691 } 692 693 return r; 694 } 695 696 /** 697 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 698 * @bo: pointer to the buffer object 699 * 700 * Sets placement according to domain; and changes placement and caching 701 * policy of the buffer object according to the placement. 702 * This is used for validating shadow bos. It calls ttm_bo_validate() to 703 * make sure the buffer is resident where it needs to be. 704 * 705 * Returns: 706 * 0 for success or a negative error code on failure. 707 */ 708 int amdgpu_bo_validate(struct amdgpu_bo *bo) 709 { 710 struct ttm_operation_ctx ctx = { false, false }; 711 uint32_t domain; 712 int r; 713 714 if (bo->tbo.pin_count) 715 return 0; 716 717 domain = bo->preferred_domains; 718 719 retry: 720 amdgpu_bo_placement_from_domain(bo, domain); 721 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 722 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 723 domain = bo->allowed_domains; 724 goto retry; 725 } 726 727 return r; 728 } 729 730 /** 731 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 732 * 733 * @shadow: &amdgpu_bo shadow to be restored 734 * @fence: dma_fence associated with the operation 735 * 736 * Copies a buffer object's shadow content back to the object. 737 * This is used for recovering a buffer from its shadow in case of a gpu 738 * reset where vram context may be lost. 739 * 740 * Returns: 741 * 0 for success or a negative error code on failure. 742 */ 743 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 744 745 { 746 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 747 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 748 uint64_t shadow_addr, parent_addr; 749 750 shadow_addr = amdgpu_bo_gpu_offset(shadow); 751 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 752 753 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 754 amdgpu_bo_size(shadow), NULL, fence, 755 true, false, false); 756 } 757 758 /** 759 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 760 * @bo: &amdgpu_bo buffer object to be mapped 761 * @ptr: kernel virtual address to be returned 762 * 763 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 764 * amdgpu_bo_kptr() to get the kernel virtual address. 765 * 766 * Returns: 767 * 0 for success or a negative error code on failure. 768 */ 769 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 770 { 771 void *kptr; 772 long r; 773 774 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 775 return -EPERM; 776 777 kptr = amdgpu_bo_kptr(bo); 778 if (kptr) { 779 if (ptr) 780 *ptr = kptr; 781 return 0; 782 } 783 784 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 785 MAX_SCHEDULE_TIMEOUT); 786 if (r < 0) 787 return r; 788 789 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 790 if (r) 791 return r; 792 793 if (ptr) 794 *ptr = amdgpu_bo_kptr(bo); 795 796 return 0; 797 } 798 799 /** 800 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 801 * @bo: &amdgpu_bo buffer object 802 * 803 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 804 * 805 * Returns: 806 * the virtual address of a buffer object area. 807 */ 808 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 809 { 810 bool is_iomem; 811 812 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 813 } 814 815 /** 816 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 817 * @bo: &amdgpu_bo buffer object to be unmapped 818 * 819 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 820 */ 821 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 822 { 823 if (bo->kmap.bo) 824 ttm_bo_kunmap(&bo->kmap); 825 } 826 827 /** 828 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 829 * @bo: &amdgpu_bo buffer object 830 * 831 * References the contained &ttm_buffer_object. 832 * 833 * Returns: 834 * a refcounted pointer to the &amdgpu_bo buffer object. 835 */ 836 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 837 { 838 if (bo == NULL) 839 return NULL; 840 841 ttm_bo_get(&bo->tbo); 842 return bo; 843 } 844 845 /** 846 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 847 * @bo: &amdgpu_bo buffer object 848 * 849 * Unreferences the contained &ttm_buffer_object and clear the pointer 850 */ 851 void amdgpu_bo_unref(struct amdgpu_bo **bo) 852 { 853 struct ttm_buffer_object *tbo; 854 855 if ((*bo) == NULL) 856 return; 857 858 tbo = &((*bo)->tbo); 859 ttm_bo_put(tbo); 860 *bo = NULL; 861 } 862 863 /** 864 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 865 * @bo: &amdgpu_bo buffer object to be pinned 866 * @domain: domain to be pinned to 867 * @min_offset: the start of requested address range 868 * @max_offset: the end of requested address range 869 * 870 * Pins the buffer object according to requested domain and address range. If 871 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 872 * pin_count and pin_size accordingly. 873 * 874 * Pinning means to lock pages in memory along with keeping them at a fixed 875 * offset. It is required when a buffer can not be moved, for example, when 876 * a display buffer is being scanned out. 877 * 878 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 879 * where to pin a buffer if there are specific restrictions on where a buffer 880 * must be located. 881 * 882 * Returns: 883 * 0 for success or a negative error code on failure. 884 */ 885 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 886 u64 min_offset, u64 max_offset) 887 { 888 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 889 struct ttm_operation_ctx ctx = { false, false }; 890 int r, i; 891 892 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 893 return -EPERM; 894 895 if (WARN_ON_ONCE(min_offset > max_offset)) 896 return -EINVAL; 897 898 /* A shared bo cannot be migrated to VRAM */ 899 if (bo->prime_shared_count) { 900 if (domain & AMDGPU_GEM_DOMAIN_GTT) 901 domain = AMDGPU_GEM_DOMAIN_GTT; 902 else 903 return -EINVAL; 904 } 905 906 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 907 * See function amdgpu_display_supported_domains() 908 */ 909 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 910 911 if (bo->tbo.pin_count) { 912 uint32_t mem_type = bo->tbo.mem.mem_type; 913 914 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 915 return -EINVAL; 916 917 ttm_bo_pin(&bo->tbo); 918 919 if (max_offset != 0) { 920 u64 domain_start = amdgpu_ttm_domain_start(adev, 921 mem_type); 922 WARN_ON_ONCE(max_offset < 923 (amdgpu_bo_gpu_offset(bo) - domain_start)); 924 } 925 926 return 0; 927 } 928 929 if (bo->tbo.base.import_attach) 930 dma_buf_pin(bo->tbo.base.import_attach); 931 932 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 933 /* force to pin into visible video ram */ 934 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 935 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 936 amdgpu_bo_placement_from_domain(bo, domain); 937 for (i = 0; i < bo->placement.num_placement; i++) { 938 unsigned fpfn, lpfn; 939 940 fpfn = min_offset >> PAGE_SHIFT; 941 lpfn = max_offset >> PAGE_SHIFT; 942 943 if (fpfn > bo->placements[i].fpfn) 944 bo->placements[i].fpfn = fpfn; 945 if (!bo->placements[i].lpfn || 946 (lpfn && lpfn < bo->placements[i].lpfn)) 947 bo->placements[i].lpfn = lpfn; 948 } 949 950 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 951 if (unlikely(r)) { 952 dev_err(adev->dev, "%p pin failed\n", bo); 953 goto error; 954 } 955 956 ttm_bo_pin(&bo->tbo); 957 958 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 959 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 960 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 961 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 962 &adev->visible_pin_size); 963 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 964 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 965 } 966 967 error: 968 return r; 969 } 970 971 /** 972 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 973 * @bo: &amdgpu_bo buffer object to be pinned 974 * @domain: domain to be pinned to 975 * 976 * A simple wrapper to amdgpu_bo_pin_restricted(). 977 * Provides a simpler API for buffers that do not have any strict restrictions 978 * on where a buffer must be located. 979 * 980 * Returns: 981 * 0 for success or a negative error code on failure. 982 */ 983 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 984 { 985 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 986 } 987 988 /** 989 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 990 * @bo: &amdgpu_bo buffer object to be unpinned 991 * 992 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 993 * Changes placement and pin size accordingly. 994 * 995 * Returns: 996 * 0 for success or a negative error code on failure. 997 */ 998 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 999 { 1000 ttm_bo_unpin(&bo->tbo); 1001 if (bo->tbo.pin_count) 1002 return; 1003 1004 amdgpu_bo_subtract_pin_size(bo); 1005 1006 if (bo->tbo.base.import_attach) 1007 dma_buf_unpin(bo->tbo.base.import_attach); 1008 } 1009 1010 /** 1011 * amdgpu_bo_evict_vram - evict VRAM buffers 1012 * @adev: amdgpu device object 1013 * 1014 * Evicts all VRAM buffers on the lru list of the memory type. 1015 * Mainly used for evicting vram at suspend time. 1016 * 1017 * Returns: 1018 * 0 for success or a negative error code on failure. 1019 */ 1020 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1021 { 1022 struct ttm_resource_manager *man; 1023 1024 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1025 #ifndef CONFIG_HIBERNATION 1026 if (adev->flags & AMD_IS_APU) { 1027 /* Useless to evict on IGP chips */ 1028 return 0; 1029 } 1030 #endif 1031 1032 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1033 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 1034 } 1035 1036 static const char *amdgpu_vram_names[] = { 1037 "UNKNOWN", 1038 "GDDR1", 1039 "DDR2", 1040 "GDDR3", 1041 "GDDR4", 1042 "GDDR5", 1043 "HBM", 1044 "DDR3", 1045 "DDR4", 1046 "GDDR6", 1047 }; 1048 1049 /** 1050 * amdgpu_bo_init - initialize memory manager 1051 * @adev: amdgpu device object 1052 * 1053 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1054 * 1055 * Returns: 1056 * 0 for success or a negative error code on failure. 1057 */ 1058 int amdgpu_bo_init(struct amdgpu_device *adev) 1059 { 1060 /* reserve PAT memory space to WC for VRAM */ 1061 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1062 adev->gmc.aper_size); 1063 1064 /* Add an MTRR for the VRAM */ 1065 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1066 adev->gmc.aper_size); 1067 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1068 adev->gmc.mc_vram_size >> 20, 1069 (unsigned long long)adev->gmc.aper_size >> 20); 1070 DRM_INFO("RAM width %dbits %s\n", 1071 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1072 return amdgpu_ttm_init(adev); 1073 } 1074 1075 /** 1076 * amdgpu_bo_late_init - late init 1077 * @adev: amdgpu device object 1078 * 1079 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1080 * initialization. 1081 * 1082 * Returns: 1083 * 0 for success or a negative error code on failure. 1084 */ 1085 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1086 { 1087 amdgpu_ttm_late_init(adev); 1088 1089 return 0; 1090 } 1091 1092 /** 1093 * amdgpu_bo_fini - tear down memory manager 1094 * @adev: amdgpu device object 1095 * 1096 * Reverses amdgpu_bo_init() to tear down memory manager. 1097 */ 1098 void amdgpu_bo_fini(struct amdgpu_device *adev) 1099 { 1100 amdgpu_ttm_fini(adev); 1101 arch_phys_wc_del(adev->gmc.vram_mtrr); 1102 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1103 } 1104 1105 /** 1106 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1107 * @bo: &amdgpu_bo buffer object 1108 * @vma: vma as input from the fbdev mmap method 1109 * 1110 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1111 * 1112 * Returns: 1113 * 0 for success or a negative error code on failure. 1114 */ 1115 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1116 struct vm_area_struct *vma) 1117 { 1118 if (vma->vm_pgoff != 0) 1119 return -EACCES; 1120 1121 return ttm_bo_mmap_obj(vma, &bo->tbo); 1122 } 1123 1124 /** 1125 * amdgpu_bo_set_tiling_flags - set tiling flags 1126 * @bo: &amdgpu_bo buffer object 1127 * @tiling_flags: new flags 1128 * 1129 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1130 * kernel driver to set the tiling flags on a buffer. 1131 * 1132 * Returns: 1133 * 0 for success or a negative error code on failure. 1134 */ 1135 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1136 { 1137 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1138 1139 if (adev->family <= AMDGPU_FAMILY_CZ && 1140 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1141 return -EINVAL; 1142 1143 bo->tiling_flags = tiling_flags; 1144 return 0; 1145 } 1146 1147 /** 1148 * amdgpu_bo_get_tiling_flags - get tiling flags 1149 * @bo: &amdgpu_bo buffer object 1150 * @tiling_flags: returned flags 1151 * 1152 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1153 * set the tiling flags on a buffer. 1154 */ 1155 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1156 { 1157 dma_resv_assert_held(bo->tbo.base.resv); 1158 1159 if (tiling_flags) 1160 *tiling_flags = bo->tiling_flags; 1161 } 1162 1163 /** 1164 * amdgpu_bo_set_metadata - set metadata 1165 * @bo: &amdgpu_bo buffer object 1166 * @metadata: new metadata 1167 * @metadata_size: size of the new metadata 1168 * @flags: flags of the new metadata 1169 * 1170 * Sets buffer object's metadata, its size and flags. 1171 * Used via GEM ioctl. 1172 * 1173 * Returns: 1174 * 0 for success or a negative error code on failure. 1175 */ 1176 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1177 uint32_t metadata_size, uint64_t flags) 1178 { 1179 void *buffer; 1180 1181 if (!metadata_size) { 1182 if (bo->metadata_size) { 1183 kfree(bo->metadata); 1184 bo->metadata = NULL; 1185 bo->metadata_size = 0; 1186 } 1187 return 0; 1188 } 1189 1190 if (metadata == NULL) 1191 return -EINVAL; 1192 1193 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1194 if (buffer == NULL) 1195 return -ENOMEM; 1196 1197 kfree(bo->metadata); 1198 bo->metadata_flags = flags; 1199 bo->metadata = buffer; 1200 bo->metadata_size = metadata_size; 1201 1202 return 0; 1203 } 1204 1205 /** 1206 * amdgpu_bo_get_metadata - get metadata 1207 * @bo: &amdgpu_bo buffer object 1208 * @buffer: returned metadata 1209 * @buffer_size: size of the buffer 1210 * @metadata_size: size of the returned metadata 1211 * @flags: flags of the returned metadata 1212 * 1213 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1214 * less than metadata_size. 1215 * Used via GEM ioctl. 1216 * 1217 * Returns: 1218 * 0 for success or a negative error code on failure. 1219 */ 1220 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1221 size_t buffer_size, uint32_t *metadata_size, 1222 uint64_t *flags) 1223 { 1224 if (!buffer && !metadata_size) 1225 return -EINVAL; 1226 1227 if (buffer) { 1228 if (buffer_size < bo->metadata_size) 1229 return -EINVAL; 1230 1231 if (bo->metadata_size) 1232 memcpy(buffer, bo->metadata, bo->metadata_size); 1233 } 1234 1235 if (metadata_size) 1236 *metadata_size = bo->metadata_size; 1237 if (flags) 1238 *flags = bo->metadata_flags; 1239 1240 return 0; 1241 } 1242 1243 /** 1244 * amdgpu_bo_move_notify - notification about a memory move 1245 * @bo: pointer to a buffer object 1246 * @evict: if this move is evicting the buffer from the graphics address space 1247 * @new_mem: new information of the bufer object 1248 * 1249 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1250 * bookkeeping. 1251 * TTM driver callback which is called when ttm moves a buffer. 1252 */ 1253 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1254 bool evict, 1255 struct ttm_resource *new_mem) 1256 { 1257 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1258 struct amdgpu_bo *abo; 1259 struct ttm_resource *old_mem = &bo->mem; 1260 1261 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1262 return; 1263 1264 abo = ttm_to_amdgpu_bo(bo); 1265 amdgpu_vm_bo_invalidate(adev, abo, evict); 1266 1267 amdgpu_bo_kunmap(abo); 1268 1269 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1270 bo->mem.mem_type != TTM_PL_SYSTEM) 1271 dma_buf_move_notify(abo->tbo.base.dma_buf); 1272 1273 /* remember the eviction */ 1274 if (evict) 1275 atomic64_inc(&adev->num_evictions); 1276 1277 /* update statistics */ 1278 if (!new_mem) 1279 return; 1280 1281 /* move_notify is called before move happens */ 1282 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1283 } 1284 1285 /** 1286 * amdgpu_bo_release_notify - notification about a BO being released 1287 * @bo: pointer to a buffer object 1288 * 1289 * Wipes VRAM buffers whose contents should not be leaked before the 1290 * memory is released. 1291 */ 1292 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1293 { 1294 struct dma_fence *fence = NULL; 1295 struct amdgpu_bo *abo; 1296 int r; 1297 1298 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1299 return; 1300 1301 abo = ttm_to_amdgpu_bo(bo); 1302 1303 if (abo->kfd_bo) 1304 amdgpu_amdkfd_unreserve_memory_limit(abo); 1305 1306 /* We only remove the fence if the resv has individualized. */ 1307 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1308 && bo->base.resv != &bo->base._resv); 1309 if (bo->base.resv == &bo->base._resv) 1310 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1311 1312 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1313 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1314 return; 1315 1316 dma_resv_lock(bo->base.resv, NULL); 1317 1318 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1319 if (!WARN_ON(r)) { 1320 amdgpu_bo_fence(abo, fence, false); 1321 dma_fence_put(fence); 1322 } 1323 1324 dma_resv_unlock(bo->base.resv); 1325 } 1326 1327 /** 1328 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1329 * @bo: pointer to a buffer object 1330 * 1331 * Notifies the driver we are taking a fault on this BO and have reserved it, 1332 * also performs bookkeeping. 1333 * TTM driver callback for dealing with vm faults. 1334 * 1335 * Returns: 1336 * 0 for success or a negative error code on failure. 1337 */ 1338 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1339 { 1340 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1341 struct ttm_operation_ctx ctx = { false, false }; 1342 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1343 unsigned long offset, size; 1344 int r; 1345 1346 /* Remember that this BO was accessed by the CPU */ 1347 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1348 1349 if (bo->mem.mem_type != TTM_PL_VRAM) 1350 return 0; 1351 1352 size = bo->mem.num_pages << PAGE_SHIFT; 1353 offset = bo->mem.start << PAGE_SHIFT; 1354 if ((offset + size) <= adev->gmc.visible_vram_size) 1355 return 0; 1356 1357 /* Can't move a pinned BO to visible VRAM */ 1358 if (abo->tbo.pin_count > 0) 1359 return VM_FAULT_SIGBUS; 1360 1361 /* hurrah the memory is not visible ! */ 1362 atomic64_inc(&adev->num_vram_cpu_page_faults); 1363 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1364 AMDGPU_GEM_DOMAIN_GTT); 1365 1366 /* Avoid costly evictions; only set GTT as a busy placement */ 1367 abo->placement.num_busy_placement = 1; 1368 abo->placement.busy_placement = &abo->placements[1]; 1369 1370 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1371 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1372 return VM_FAULT_NOPAGE; 1373 else if (unlikely(r)) 1374 return VM_FAULT_SIGBUS; 1375 1376 offset = bo->mem.start << PAGE_SHIFT; 1377 /* this should never happen */ 1378 if (bo->mem.mem_type == TTM_PL_VRAM && 1379 (offset + size) > adev->gmc.visible_vram_size) 1380 return VM_FAULT_SIGBUS; 1381 1382 ttm_bo_move_to_lru_tail_unlocked(bo); 1383 return 0; 1384 } 1385 1386 /** 1387 * amdgpu_bo_fence - add fence to buffer object 1388 * 1389 * @bo: buffer object in question 1390 * @fence: fence to add 1391 * @shared: true if fence should be added shared 1392 * 1393 */ 1394 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1395 bool shared) 1396 { 1397 struct dma_resv *resv = bo->tbo.base.resv; 1398 1399 if (shared) 1400 dma_resv_add_shared_fence(resv, fence); 1401 else 1402 dma_resv_add_excl_fence(resv, fence); 1403 } 1404 1405 /** 1406 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1407 * 1408 * @adev: amdgpu device pointer 1409 * @resv: reservation object to sync to 1410 * @sync_mode: synchronization mode 1411 * @owner: fence owner 1412 * @intr: Whether the wait is interruptible 1413 * 1414 * Extract the fences from the reservation object and waits for them to finish. 1415 * 1416 * Returns: 1417 * 0 on success, errno otherwise. 1418 */ 1419 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1420 enum amdgpu_sync_mode sync_mode, void *owner, 1421 bool intr) 1422 { 1423 struct amdgpu_sync sync; 1424 int r; 1425 1426 amdgpu_sync_create(&sync); 1427 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1428 r = amdgpu_sync_wait(&sync, intr); 1429 amdgpu_sync_free(&sync); 1430 return r; 1431 } 1432 1433 /** 1434 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1435 * @bo: buffer object to wait for 1436 * @owner: fence owner 1437 * @intr: Whether the wait is interruptible 1438 * 1439 * Wrapper to wait for fences in a BO. 1440 * Returns: 1441 * 0 on success, errno otherwise. 1442 */ 1443 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1444 { 1445 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1446 1447 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1448 AMDGPU_SYNC_NE_OWNER, owner, intr); 1449 } 1450 1451 /** 1452 * amdgpu_bo_gpu_offset - return GPU offset of bo 1453 * @bo: amdgpu object for which we query the offset 1454 * 1455 * Note: object should either be pinned or reserved when calling this 1456 * function, it might be useful to add check for this for debugging. 1457 * 1458 * Returns: 1459 * current GPU offset of the object. 1460 */ 1461 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1462 { 1463 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1464 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1465 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1466 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1467 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1468 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1469 1470 return amdgpu_bo_gpu_offset_no_check(bo); 1471 } 1472 1473 /** 1474 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1475 * @bo: amdgpu object for which we query the offset 1476 * 1477 * Returns: 1478 * current GPU offset of the object without raising warnings. 1479 */ 1480 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1481 { 1482 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1483 uint64_t offset; 1484 1485 offset = (bo->tbo.mem.start << PAGE_SHIFT) + 1486 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 1487 1488 return amdgpu_gmc_sign_extend(offset); 1489 } 1490 1491 /** 1492 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1493 * @adev: amdgpu device object 1494 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1495 * 1496 * Returns: 1497 * Which of the allowed domains is preferred for pinning the BO for scanout. 1498 */ 1499 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1500 uint32_t domain) 1501 { 1502 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1503 domain = AMDGPU_GEM_DOMAIN_VRAM; 1504 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1505 domain = AMDGPU_GEM_DOMAIN_GTT; 1506 } 1507 return domain; 1508 } 1509