1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/amdgpu_drm.h> 37 #include <drm/drm_cache.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 #include "amdgpu_amdkfd.h" 41 42 /** 43 * DOC: amdgpu_object 44 * 45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 46 * represents memory used by driver (VRAM, system memory, etc.). The driver 47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 48 * to create/destroy/set buffer object which are then managed by the kernel TTM 49 * memory manager. 50 * The interfaces are also used internally by kernel clients, including gfx, 51 * uvd, etc. for kernel managed allocations used by the GPU. 52 * 53 */ 54 55 /** 56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 57 * 58 * @bo: &amdgpu_bo buffer object 59 * 60 * This function is called when a BO stops being pinned, and updates the 61 * &amdgpu_device pin_size values accordingly. 62 */ 63 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 64 { 65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 66 67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 70 &adev->visible_pin_size); 71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 73 } 74 } 75 76 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 77 { 78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 80 81 if (bo->pin_count > 0) 82 amdgpu_bo_subtract_pin_size(bo); 83 84 amdgpu_bo_kunmap(bo); 85 86 if (bo->tbo.base.import_attach) 87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 88 drm_gem_object_release(&bo->tbo.base); 89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 90 if (!list_empty(&bo->shadow_list)) { 91 mutex_lock(&adev->shadow_list_lock); 92 list_del_init(&bo->shadow_list); 93 mutex_unlock(&adev->shadow_list_lock); 94 } 95 amdgpu_bo_unref(&bo->parent); 96 97 kfree(bo->metadata); 98 kfree(bo); 99 } 100 101 /** 102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 103 * @bo: buffer object to be checked 104 * 105 * Uses destroy function associated with the object to determine if this is 106 * an &amdgpu_bo. 107 * 108 * Returns: 109 * true if the object belongs to &amdgpu_bo, false if not. 110 */ 111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 112 { 113 if (bo->destroy == &amdgpu_bo_destroy) 114 return true; 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 137 places[c].fpfn = 0; 138 places[c].lpfn = 0; 139 places[c].mem_type = TTM_PL_VRAM; 140 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; 141 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 places[c].lpfn = visible_pfn; 144 else 145 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 146 147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 149 c++; 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 places[c].fpfn = 0; 154 places[c].lpfn = 0; 155 places[c].mem_type = TTM_PL_TT; 156 places[c].flags = 0; 157 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 158 places[c].flags |= TTM_PL_FLAG_WC | 159 TTM_PL_FLAG_UNCACHED; 160 else 161 places[c].flags |= TTM_PL_FLAG_CACHED; 162 c++; 163 } 164 165 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 166 places[c].fpfn = 0; 167 places[c].lpfn = 0; 168 places[c].mem_type = TTM_PL_SYSTEM; 169 places[c].flags = 0; 170 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 171 places[c].flags |= TTM_PL_FLAG_WC | 172 TTM_PL_FLAG_UNCACHED; 173 else 174 places[c].flags |= TTM_PL_FLAG_CACHED; 175 c++; 176 } 177 178 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 179 places[c].fpfn = 0; 180 places[c].lpfn = 0; 181 places[c].mem_type = AMDGPU_PL_GDS; 182 places[c].flags = TTM_PL_FLAG_UNCACHED; 183 c++; 184 } 185 186 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 187 places[c].fpfn = 0; 188 places[c].lpfn = 0; 189 places[c].mem_type = AMDGPU_PL_GWS; 190 places[c].flags = TTM_PL_FLAG_UNCACHED; 191 c++; 192 } 193 194 if (domain & AMDGPU_GEM_DOMAIN_OA) { 195 places[c].fpfn = 0; 196 places[c].lpfn = 0; 197 places[c].mem_type = AMDGPU_PL_OA; 198 places[c].flags = TTM_PL_FLAG_UNCACHED; 199 c++; 200 } 201 202 if (!c) { 203 places[c].fpfn = 0; 204 places[c].lpfn = 0; 205 places[c].mem_type = TTM_PL_SYSTEM; 206 places[c].flags = TTM_PL_MASK_CACHING; 207 c++; 208 } 209 210 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 211 212 placement->num_placement = c; 213 placement->placement = places; 214 215 placement->num_busy_placement = c; 216 placement->busy_placement = places; 217 } 218 219 /** 220 * amdgpu_bo_create_reserved - create reserved BO for kernel use 221 * 222 * @adev: amdgpu device object 223 * @size: size for the new BO 224 * @align: alignment for the new BO 225 * @domain: where to place it 226 * @bo_ptr: used to initialize BOs in structures 227 * @gpu_addr: GPU addr of the pinned BO 228 * @cpu_addr: optional CPU address mapping 229 * 230 * Allocates and pins a BO for kernel internal use, and returns it still 231 * reserved. 232 * 233 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 234 * 235 * Returns: 236 * 0 on success, negative error code otherwise. 237 */ 238 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 239 unsigned long size, int align, 240 u32 domain, struct amdgpu_bo **bo_ptr, 241 u64 *gpu_addr, void **cpu_addr) 242 { 243 struct amdgpu_bo_param bp; 244 bool free = false; 245 int r; 246 247 if (!size) { 248 amdgpu_bo_unref(bo_ptr); 249 return 0; 250 } 251 252 memset(&bp, 0, sizeof(bp)); 253 bp.size = size; 254 bp.byte_align = align; 255 bp.domain = domain; 256 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 257 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 258 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 259 bp.type = ttm_bo_type_kernel; 260 bp.resv = NULL; 261 262 if (!*bo_ptr) { 263 r = amdgpu_bo_create(adev, &bp, bo_ptr); 264 if (r) { 265 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 266 r); 267 return r; 268 } 269 free = true; 270 } 271 272 r = amdgpu_bo_reserve(*bo_ptr, false); 273 if (r) { 274 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 275 goto error_free; 276 } 277 278 r = amdgpu_bo_pin(*bo_ptr, domain); 279 if (r) { 280 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 281 goto error_unreserve; 282 } 283 284 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 285 if (r) { 286 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 287 goto error_unpin; 288 } 289 290 if (gpu_addr) 291 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 292 293 if (cpu_addr) { 294 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 295 if (r) { 296 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 297 goto error_unpin; 298 } 299 } 300 301 return 0; 302 303 error_unpin: 304 amdgpu_bo_unpin(*bo_ptr); 305 error_unreserve: 306 amdgpu_bo_unreserve(*bo_ptr); 307 308 error_free: 309 if (free) 310 amdgpu_bo_unref(bo_ptr); 311 312 return r; 313 } 314 315 /** 316 * amdgpu_bo_create_kernel - create BO for kernel use 317 * 318 * @adev: amdgpu device object 319 * @size: size for the new BO 320 * @align: alignment for the new BO 321 * @domain: where to place it 322 * @bo_ptr: used to initialize BOs in structures 323 * @gpu_addr: GPU addr of the pinned BO 324 * @cpu_addr: optional CPU address mapping 325 * 326 * Allocates and pins a BO for kernel internal use. 327 * 328 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 329 * 330 * Returns: 331 * 0 on success, negative error code otherwise. 332 */ 333 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 334 unsigned long size, int align, 335 u32 domain, struct amdgpu_bo **bo_ptr, 336 u64 *gpu_addr, void **cpu_addr) 337 { 338 int r; 339 340 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 341 gpu_addr, cpu_addr); 342 343 if (r) 344 return r; 345 346 if (*bo_ptr) 347 amdgpu_bo_unreserve(*bo_ptr); 348 349 return 0; 350 } 351 352 /** 353 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 354 * 355 * @adev: amdgpu device object 356 * @offset: offset of the BO 357 * @size: size of the BO 358 * @domain: where to place it 359 * @bo_ptr: used to initialize BOs in structures 360 * @cpu_addr: optional CPU address mapping 361 * 362 * Creates a kernel BO at a specific offset in the address space of the domain. 363 * 364 * Returns: 365 * 0 on success, negative error code otherwise. 366 */ 367 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 368 uint64_t offset, uint64_t size, uint32_t domain, 369 struct amdgpu_bo **bo_ptr, void **cpu_addr) 370 { 371 struct ttm_operation_ctx ctx = { false, false }; 372 unsigned int i; 373 int r; 374 375 offset &= PAGE_MASK; 376 size = ALIGN(size, PAGE_SIZE); 377 378 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 379 NULL, cpu_addr); 380 if (r) 381 return r; 382 383 if ((*bo_ptr) == NULL) 384 return 0; 385 386 /* 387 * Remove the original mem node and create a new one at the request 388 * position. 389 */ 390 if (cpu_addr) 391 amdgpu_bo_kunmap(*bo_ptr); 392 393 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); 394 395 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 396 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 397 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 398 } 399 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 400 &(*bo_ptr)->tbo.mem, &ctx); 401 if (r) 402 goto error; 403 404 if (cpu_addr) { 405 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 406 if (r) 407 goto error; 408 } 409 410 amdgpu_bo_unreserve(*bo_ptr); 411 return 0; 412 413 error: 414 amdgpu_bo_unreserve(*bo_ptr); 415 amdgpu_bo_unref(bo_ptr); 416 return r; 417 } 418 419 /** 420 * amdgpu_bo_free_kernel - free BO for kernel use 421 * 422 * @bo: amdgpu BO to free 423 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 424 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 425 * 426 * unmaps and unpin a BO for kernel internal use. 427 */ 428 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 429 void **cpu_addr) 430 { 431 if (*bo == NULL) 432 return; 433 434 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 435 if (cpu_addr) 436 amdgpu_bo_kunmap(*bo); 437 438 amdgpu_bo_unpin(*bo); 439 amdgpu_bo_unreserve(*bo); 440 } 441 amdgpu_bo_unref(bo); 442 443 if (gpu_addr) 444 *gpu_addr = 0; 445 446 if (cpu_addr) 447 *cpu_addr = NULL; 448 } 449 450 /* Validate bo size is bit bigger then the request domain */ 451 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 452 unsigned long size, u32 domain) 453 { 454 struct ttm_resource_manager *man = NULL; 455 456 /* 457 * If GTT is part of requested domains the check must succeed to 458 * allow fall back to GTT 459 */ 460 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 461 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 462 463 if (size < (man->size << PAGE_SHIFT)) 464 return true; 465 else 466 goto fail; 467 } 468 469 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 470 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 471 472 if (size < (man->size << PAGE_SHIFT)) 473 return true; 474 else 475 goto fail; 476 } 477 478 479 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 480 return true; 481 482 fail: 483 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 484 man->size << PAGE_SHIFT); 485 return false; 486 } 487 488 bool amdgpu_bo_support_uswc(u64 bo_flags) 489 { 490 491 #ifdef CONFIG_X86_32 492 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 493 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 494 */ 495 return false; 496 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 497 /* Don't try to enable write-combining when it can't work, or things 498 * may be slow 499 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 500 */ 501 502 #ifndef CONFIG_COMPILE_TEST 503 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 504 thanks to write-combining 505 #endif 506 507 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 508 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 509 "better performance thanks to write-combining\n"); 510 return false; 511 #else 512 /* For architectures that don't support WC memory, 513 * mask out the WC flag from the BO 514 */ 515 if (!drm_arch_can_wc_memory()) 516 return false; 517 518 return true; 519 #endif 520 } 521 522 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 523 struct amdgpu_bo_param *bp, 524 struct amdgpu_bo **bo_ptr) 525 { 526 struct ttm_operation_ctx ctx = { 527 .interruptible = (bp->type != ttm_bo_type_kernel), 528 .no_wait_gpu = bp->no_wait_gpu, 529 .resv = bp->resv, 530 .flags = bp->type != ttm_bo_type_kernel ? 531 TTM_OPT_FLAG_ALLOW_RES_EVICT : 0 532 }; 533 struct amdgpu_bo *bo; 534 unsigned long page_align, size = bp->size; 535 size_t acc_size; 536 int r; 537 538 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 539 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 540 /* GWS and OA don't need any alignment. */ 541 page_align = bp->byte_align; 542 size <<= PAGE_SHIFT; 543 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 544 /* Both size and alignment must be a multiple of 4. */ 545 page_align = ALIGN(bp->byte_align, 4); 546 size = ALIGN(size, 4) << PAGE_SHIFT; 547 } else { 548 /* Memory should be aligned at least to a page size. */ 549 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 550 size = ALIGN(size, PAGE_SIZE); 551 } 552 553 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 554 return -ENOMEM; 555 556 *bo_ptr = NULL; 557 558 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 559 sizeof(struct amdgpu_bo)); 560 561 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 562 if (bo == NULL) 563 return -ENOMEM; 564 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 565 INIT_LIST_HEAD(&bo->shadow_list); 566 bo->vm_bo = NULL; 567 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 568 bp->domain; 569 bo->allowed_domains = bo->preferred_domains; 570 if (bp->type != ttm_bo_type_kernel && 571 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 572 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 573 574 bo->flags = bp->flags; 575 576 if (!amdgpu_bo_support_uswc(bo->flags)) 577 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 578 579 bo->tbo.bdev = &adev->mman.bdev; 580 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 581 AMDGPU_GEM_DOMAIN_GDS)) 582 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 583 else 584 amdgpu_bo_placement_from_domain(bo, bp->domain); 585 if (bp->type == ttm_bo_type_kernel) 586 bo->tbo.priority = 1; 587 588 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 589 &bo->placement, page_align, &ctx, acc_size, 590 NULL, bp->resv, &amdgpu_bo_destroy); 591 if (unlikely(r != 0)) 592 return r; 593 594 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 595 bo->tbo.mem.mem_type == TTM_PL_VRAM && 596 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 597 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 598 ctx.bytes_moved); 599 else 600 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 601 602 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 603 bo->tbo.mem.mem_type == TTM_PL_VRAM) { 604 struct dma_fence *fence; 605 606 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 607 if (unlikely(r)) 608 goto fail_unreserve; 609 610 amdgpu_bo_fence(bo, fence, false); 611 dma_fence_put(bo->tbo.moving); 612 bo->tbo.moving = dma_fence_get(fence); 613 dma_fence_put(fence); 614 } 615 if (!bp->resv) 616 amdgpu_bo_unreserve(bo); 617 *bo_ptr = bo; 618 619 trace_amdgpu_bo_create(bo); 620 621 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 622 if (bp->type == ttm_bo_type_device) 623 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 624 625 return 0; 626 627 fail_unreserve: 628 if (!bp->resv) 629 dma_resv_unlock(bo->tbo.base.resv); 630 amdgpu_bo_unref(&bo); 631 return r; 632 } 633 634 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 635 unsigned long size, 636 struct amdgpu_bo *bo) 637 { 638 struct amdgpu_bo_param bp; 639 int r; 640 641 if (bo->shadow) 642 return 0; 643 644 memset(&bp, 0, sizeof(bp)); 645 bp.size = size; 646 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 647 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 648 AMDGPU_GEM_CREATE_SHADOW; 649 bp.type = ttm_bo_type_kernel; 650 bp.resv = bo->tbo.base.resv; 651 652 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 653 if (!r) { 654 bo->shadow->parent = amdgpu_bo_ref(bo); 655 mutex_lock(&adev->shadow_list_lock); 656 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 657 mutex_unlock(&adev->shadow_list_lock); 658 } 659 660 return r; 661 } 662 663 /** 664 * amdgpu_bo_create - create an &amdgpu_bo buffer object 665 * @adev: amdgpu device object 666 * @bp: parameters to be used for the buffer object 667 * @bo_ptr: pointer to the buffer object pointer 668 * 669 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 670 * shadow object. 671 * Shadow object is used to backup the original buffer object, and is always 672 * in GTT. 673 * 674 * Returns: 675 * 0 for success or a negative error code on failure. 676 */ 677 int amdgpu_bo_create(struct amdgpu_device *adev, 678 struct amdgpu_bo_param *bp, 679 struct amdgpu_bo **bo_ptr) 680 { 681 u64 flags = bp->flags; 682 int r; 683 684 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 685 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 686 if (r) 687 return r; 688 689 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 690 if (!bp->resv) 691 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 692 NULL)); 693 694 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 695 696 if (!bp->resv) 697 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 698 699 if (r) 700 amdgpu_bo_unref(bo_ptr); 701 } 702 703 return r; 704 } 705 706 /** 707 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 708 * @bo: pointer to the buffer object 709 * 710 * Sets placement according to domain; and changes placement and caching 711 * policy of the buffer object according to the placement. 712 * This is used for validating shadow bos. It calls ttm_bo_validate() to 713 * make sure the buffer is resident where it needs to be. 714 * 715 * Returns: 716 * 0 for success or a negative error code on failure. 717 */ 718 int amdgpu_bo_validate(struct amdgpu_bo *bo) 719 { 720 struct ttm_operation_ctx ctx = { false, false }; 721 uint32_t domain; 722 int r; 723 724 if (bo->pin_count) 725 return 0; 726 727 domain = bo->preferred_domains; 728 729 retry: 730 amdgpu_bo_placement_from_domain(bo, domain); 731 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 732 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 733 domain = bo->allowed_domains; 734 goto retry; 735 } 736 737 return r; 738 } 739 740 /** 741 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 742 * 743 * @shadow: &amdgpu_bo shadow to be restored 744 * @fence: dma_fence associated with the operation 745 * 746 * Copies a buffer object's shadow content back to the object. 747 * This is used for recovering a buffer from its shadow in case of a gpu 748 * reset where vram context may be lost. 749 * 750 * Returns: 751 * 0 for success or a negative error code on failure. 752 */ 753 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 754 755 { 756 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 757 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 758 uint64_t shadow_addr, parent_addr; 759 760 shadow_addr = amdgpu_bo_gpu_offset(shadow); 761 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 762 763 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 764 amdgpu_bo_size(shadow), NULL, fence, 765 true, false, false); 766 } 767 768 /** 769 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 770 * @bo: &amdgpu_bo buffer object to be mapped 771 * @ptr: kernel virtual address to be returned 772 * 773 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 774 * amdgpu_bo_kptr() to get the kernel virtual address. 775 * 776 * Returns: 777 * 0 for success or a negative error code on failure. 778 */ 779 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 780 { 781 void *kptr; 782 long r; 783 784 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 785 return -EPERM; 786 787 kptr = amdgpu_bo_kptr(bo); 788 if (kptr) { 789 if (ptr) 790 *ptr = kptr; 791 return 0; 792 } 793 794 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 795 MAX_SCHEDULE_TIMEOUT); 796 if (r < 0) 797 return r; 798 799 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 800 if (r) 801 return r; 802 803 if (ptr) 804 *ptr = amdgpu_bo_kptr(bo); 805 806 return 0; 807 } 808 809 /** 810 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 811 * @bo: &amdgpu_bo buffer object 812 * 813 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 814 * 815 * Returns: 816 * the virtual address of a buffer object area. 817 */ 818 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 819 { 820 bool is_iomem; 821 822 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 823 } 824 825 /** 826 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 827 * @bo: &amdgpu_bo buffer object to be unmapped 828 * 829 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 830 */ 831 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 832 { 833 if (bo->kmap.bo) 834 ttm_bo_kunmap(&bo->kmap); 835 } 836 837 /** 838 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 839 * @bo: &amdgpu_bo buffer object 840 * 841 * References the contained &ttm_buffer_object. 842 * 843 * Returns: 844 * a refcounted pointer to the &amdgpu_bo buffer object. 845 */ 846 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 847 { 848 if (bo == NULL) 849 return NULL; 850 851 ttm_bo_get(&bo->tbo); 852 return bo; 853 } 854 855 /** 856 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 857 * @bo: &amdgpu_bo buffer object 858 * 859 * Unreferences the contained &ttm_buffer_object and clear the pointer 860 */ 861 void amdgpu_bo_unref(struct amdgpu_bo **bo) 862 { 863 struct ttm_buffer_object *tbo; 864 865 if ((*bo) == NULL) 866 return; 867 868 tbo = &((*bo)->tbo); 869 ttm_bo_put(tbo); 870 *bo = NULL; 871 } 872 873 /** 874 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 875 * @bo: &amdgpu_bo buffer object to be pinned 876 * @domain: domain to be pinned to 877 * @min_offset: the start of requested address range 878 * @max_offset: the end of requested address range 879 * 880 * Pins the buffer object according to requested domain and address range. If 881 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 882 * pin_count and pin_size accordingly. 883 * 884 * Pinning means to lock pages in memory along with keeping them at a fixed 885 * offset. It is required when a buffer can not be moved, for example, when 886 * a display buffer is being scanned out. 887 * 888 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 889 * where to pin a buffer if there are specific restrictions on where a buffer 890 * must be located. 891 * 892 * Returns: 893 * 0 for success or a negative error code on failure. 894 */ 895 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 896 u64 min_offset, u64 max_offset) 897 { 898 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 899 struct ttm_operation_ctx ctx = { false, false }; 900 int r, i; 901 902 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 903 return -EPERM; 904 905 if (WARN_ON_ONCE(min_offset > max_offset)) 906 return -EINVAL; 907 908 /* A shared bo cannot be migrated to VRAM */ 909 if (bo->prime_shared_count) { 910 if (domain & AMDGPU_GEM_DOMAIN_GTT) 911 domain = AMDGPU_GEM_DOMAIN_GTT; 912 else 913 return -EINVAL; 914 } 915 916 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 917 * See function amdgpu_display_supported_domains() 918 */ 919 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 920 921 if (bo->pin_count) { 922 uint32_t mem_type = bo->tbo.mem.mem_type; 923 924 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 925 return -EINVAL; 926 927 bo->pin_count++; 928 929 if (max_offset != 0) { 930 u64 domain_start = amdgpu_ttm_domain_start(adev, 931 mem_type); 932 WARN_ON_ONCE(max_offset < 933 (amdgpu_bo_gpu_offset(bo) - domain_start)); 934 } 935 936 return 0; 937 } 938 939 if (bo->tbo.base.import_attach) 940 dma_buf_pin(bo->tbo.base.import_attach); 941 942 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 943 /* force to pin into visible video ram */ 944 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 945 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 946 amdgpu_bo_placement_from_domain(bo, domain); 947 for (i = 0; i < bo->placement.num_placement; i++) { 948 unsigned fpfn, lpfn; 949 950 fpfn = min_offset >> PAGE_SHIFT; 951 lpfn = max_offset >> PAGE_SHIFT; 952 953 if (fpfn > bo->placements[i].fpfn) 954 bo->placements[i].fpfn = fpfn; 955 if (!bo->placements[i].lpfn || 956 (lpfn && lpfn < bo->placements[i].lpfn)) 957 bo->placements[i].lpfn = lpfn; 958 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 959 } 960 961 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 962 if (unlikely(r)) { 963 dev_err(adev->dev, "%p pin failed\n", bo); 964 goto error; 965 } 966 967 bo->pin_count = 1; 968 969 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 970 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 971 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 972 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 973 &adev->visible_pin_size); 974 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 975 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 976 } 977 978 error: 979 return r; 980 } 981 982 /** 983 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 984 * @bo: &amdgpu_bo buffer object to be pinned 985 * @domain: domain to be pinned to 986 * 987 * A simple wrapper to amdgpu_bo_pin_restricted(). 988 * Provides a simpler API for buffers that do not have any strict restrictions 989 * on where a buffer must be located. 990 * 991 * Returns: 992 * 0 for success or a negative error code on failure. 993 */ 994 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 995 { 996 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 997 } 998 999 /** 1000 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 1001 * @bo: &amdgpu_bo buffer object to be unpinned 1002 * 1003 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 1004 * Changes placement and pin size accordingly. 1005 * 1006 * Returns: 1007 * 0 for success or a negative error code on failure. 1008 */ 1009 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 1010 { 1011 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1012 struct ttm_operation_ctx ctx = { false, false }; 1013 int r, i; 1014 1015 if (WARN_ON_ONCE(!bo->pin_count)) { 1016 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 1017 return 0; 1018 } 1019 bo->pin_count--; 1020 if (bo->pin_count) 1021 return 0; 1022 1023 amdgpu_bo_subtract_pin_size(bo); 1024 1025 if (bo->tbo.base.import_attach) 1026 dma_buf_unpin(bo->tbo.base.import_attach); 1027 1028 for (i = 0; i < bo->placement.num_placement; i++) { 1029 bo->placements[i].lpfn = 0; 1030 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 1031 } 1032 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1033 if (unlikely(r)) 1034 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 1035 1036 return r; 1037 } 1038 1039 /** 1040 * amdgpu_bo_evict_vram - evict VRAM buffers 1041 * @adev: amdgpu device object 1042 * 1043 * Evicts all VRAM buffers on the lru list of the memory type. 1044 * Mainly used for evicting vram at suspend time. 1045 * 1046 * Returns: 1047 * 0 for success or a negative error code on failure. 1048 */ 1049 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1050 { 1051 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1052 #ifndef CONFIG_HIBERNATION 1053 if (adev->flags & AMD_IS_APU) { 1054 /* Useless to evict on IGP chips */ 1055 return 0; 1056 } 1057 #endif 1058 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 1059 } 1060 1061 static const char *amdgpu_vram_names[] = { 1062 "UNKNOWN", 1063 "GDDR1", 1064 "DDR2", 1065 "GDDR3", 1066 "GDDR4", 1067 "GDDR5", 1068 "HBM", 1069 "DDR3", 1070 "DDR4", 1071 "GDDR6", 1072 }; 1073 1074 /** 1075 * amdgpu_bo_init - initialize memory manager 1076 * @adev: amdgpu device object 1077 * 1078 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1079 * 1080 * Returns: 1081 * 0 for success or a negative error code on failure. 1082 */ 1083 int amdgpu_bo_init(struct amdgpu_device *adev) 1084 { 1085 /* reserve PAT memory space to WC for VRAM */ 1086 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1087 adev->gmc.aper_size); 1088 1089 /* Add an MTRR for the VRAM */ 1090 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1091 adev->gmc.aper_size); 1092 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1093 adev->gmc.mc_vram_size >> 20, 1094 (unsigned long long)adev->gmc.aper_size >> 20); 1095 DRM_INFO("RAM width %dbits %s\n", 1096 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1097 return amdgpu_ttm_init(adev); 1098 } 1099 1100 /** 1101 * amdgpu_bo_late_init - late init 1102 * @adev: amdgpu device object 1103 * 1104 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1105 * initialization. 1106 * 1107 * Returns: 1108 * 0 for success or a negative error code on failure. 1109 */ 1110 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1111 { 1112 amdgpu_ttm_late_init(adev); 1113 1114 return 0; 1115 } 1116 1117 /** 1118 * amdgpu_bo_fini - tear down memory manager 1119 * @adev: amdgpu device object 1120 * 1121 * Reverses amdgpu_bo_init() to tear down memory manager. 1122 */ 1123 void amdgpu_bo_fini(struct amdgpu_device *adev) 1124 { 1125 amdgpu_ttm_fini(adev); 1126 arch_phys_wc_del(adev->gmc.vram_mtrr); 1127 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1128 } 1129 1130 /** 1131 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1132 * @bo: &amdgpu_bo buffer object 1133 * @vma: vma as input from the fbdev mmap method 1134 * 1135 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1136 * 1137 * Returns: 1138 * 0 for success or a negative error code on failure. 1139 */ 1140 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1141 struct vm_area_struct *vma) 1142 { 1143 if (vma->vm_pgoff != 0) 1144 return -EACCES; 1145 1146 return ttm_bo_mmap_obj(vma, &bo->tbo); 1147 } 1148 1149 /** 1150 * amdgpu_bo_set_tiling_flags - set tiling flags 1151 * @bo: &amdgpu_bo buffer object 1152 * @tiling_flags: new flags 1153 * 1154 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1155 * kernel driver to set the tiling flags on a buffer. 1156 * 1157 * Returns: 1158 * 0 for success or a negative error code on failure. 1159 */ 1160 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1161 { 1162 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1163 1164 if (adev->family <= AMDGPU_FAMILY_CZ && 1165 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1166 return -EINVAL; 1167 1168 bo->tiling_flags = tiling_flags; 1169 return 0; 1170 } 1171 1172 /** 1173 * amdgpu_bo_get_tiling_flags - get tiling flags 1174 * @bo: &amdgpu_bo buffer object 1175 * @tiling_flags: returned flags 1176 * 1177 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1178 * set the tiling flags on a buffer. 1179 */ 1180 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1181 { 1182 dma_resv_assert_held(bo->tbo.base.resv); 1183 1184 if (tiling_flags) 1185 *tiling_flags = bo->tiling_flags; 1186 } 1187 1188 /** 1189 * amdgpu_bo_set_metadata - set metadata 1190 * @bo: &amdgpu_bo buffer object 1191 * @metadata: new metadata 1192 * @metadata_size: size of the new metadata 1193 * @flags: flags of the new metadata 1194 * 1195 * Sets buffer object's metadata, its size and flags. 1196 * Used via GEM ioctl. 1197 * 1198 * Returns: 1199 * 0 for success or a negative error code on failure. 1200 */ 1201 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1202 uint32_t metadata_size, uint64_t flags) 1203 { 1204 void *buffer; 1205 1206 if (!metadata_size) { 1207 if (bo->metadata_size) { 1208 kfree(bo->metadata); 1209 bo->metadata = NULL; 1210 bo->metadata_size = 0; 1211 } 1212 return 0; 1213 } 1214 1215 if (metadata == NULL) 1216 return -EINVAL; 1217 1218 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1219 if (buffer == NULL) 1220 return -ENOMEM; 1221 1222 kfree(bo->metadata); 1223 bo->metadata_flags = flags; 1224 bo->metadata = buffer; 1225 bo->metadata_size = metadata_size; 1226 1227 return 0; 1228 } 1229 1230 /** 1231 * amdgpu_bo_get_metadata - get metadata 1232 * @bo: &amdgpu_bo buffer object 1233 * @buffer: returned metadata 1234 * @buffer_size: size of the buffer 1235 * @metadata_size: size of the returned metadata 1236 * @flags: flags of the returned metadata 1237 * 1238 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1239 * less than metadata_size. 1240 * Used via GEM ioctl. 1241 * 1242 * Returns: 1243 * 0 for success or a negative error code on failure. 1244 */ 1245 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1246 size_t buffer_size, uint32_t *metadata_size, 1247 uint64_t *flags) 1248 { 1249 if (!buffer && !metadata_size) 1250 return -EINVAL; 1251 1252 if (buffer) { 1253 if (buffer_size < bo->metadata_size) 1254 return -EINVAL; 1255 1256 if (bo->metadata_size) 1257 memcpy(buffer, bo->metadata, bo->metadata_size); 1258 } 1259 1260 if (metadata_size) 1261 *metadata_size = bo->metadata_size; 1262 if (flags) 1263 *flags = bo->metadata_flags; 1264 1265 return 0; 1266 } 1267 1268 /** 1269 * amdgpu_bo_move_notify - notification about a memory move 1270 * @bo: pointer to a buffer object 1271 * @evict: if this move is evicting the buffer from the graphics address space 1272 * @new_mem: new information of the bufer object 1273 * 1274 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1275 * bookkeeping. 1276 * TTM driver callback which is called when ttm moves a buffer. 1277 */ 1278 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1279 bool evict, 1280 struct ttm_resource *new_mem) 1281 { 1282 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1283 struct amdgpu_bo *abo; 1284 struct ttm_resource *old_mem = &bo->mem; 1285 1286 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1287 return; 1288 1289 abo = ttm_to_amdgpu_bo(bo); 1290 amdgpu_vm_bo_invalidate(adev, abo, evict); 1291 1292 amdgpu_bo_kunmap(abo); 1293 1294 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1295 bo->mem.mem_type != TTM_PL_SYSTEM) 1296 dma_buf_move_notify(abo->tbo.base.dma_buf); 1297 1298 /* remember the eviction */ 1299 if (evict) 1300 atomic64_inc(&adev->num_evictions); 1301 1302 /* update statistics */ 1303 if (!new_mem) 1304 return; 1305 1306 /* move_notify is called before move happens */ 1307 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1308 } 1309 1310 /** 1311 * amdgpu_bo_release_notify - notification about a BO being released 1312 * @bo: pointer to a buffer object 1313 * 1314 * Wipes VRAM buffers whose contents should not be leaked before the 1315 * memory is released. 1316 */ 1317 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1318 { 1319 struct dma_fence *fence = NULL; 1320 struct amdgpu_bo *abo; 1321 int r; 1322 1323 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1324 return; 1325 1326 abo = ttm_to_amdgpu_bo(bo); 1327 1328 if (abo->kfd_bo) 1329 amdgpu_amdkfd_unreserve_memory_limit(abo); 1330 1331 /* We only remove the fence if the resv has individualized. */ 1332 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1333 && bo->base.resv != &bo->base._resv); 1334 if (bo->base.resv == &bo->base._resv) 1335 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1336 1337 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1338 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1339 return; 1340 1341 dma_resv_lock(bo->base.resv, NULL); 1342 1343 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1344 if (!WARN_ON(r)) { 1345 amdgpu_bo_fence(abo, fence, false); 1346 dma_fence_put(fence); 1347 } 1348 1349 dma_resv_unlock(bo->base.resv); 1350 } 1351 1352 /** 1353 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1354 * @bo: pointer to a buffer object 1355 * 1356 * Notifies the driver we are taking a fault on this BO and have reserved it, 1357 * also performs bookkeeping. 1358 * TTM driver callback for dealing with vm faults. 1359 * 1360 * Returns: 1361 * 0 for success or a negative error code on failure. 1362 */ 1363 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1364 { 1365 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1366 struct ttm_operation_ctx ctx = { false, false }; 1367 struct amdgpu_bo *abo; 1368 unsigned long offset, size; 1369 int r; 1370 1371 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1372 return 0; 1373 1374 abo = ttm_to_amdgpu_bo(bo); 1375 1376 /* Remember that this BO was accessed by the CPU */ 1377 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1378 1379 if (bo->mem.mem_type != TTM_PL_VRAM) 1380 return 0; 1381 1382 size = bo->mem.num_pages << PAGE_SHIFT; 1383 offset = bo->mem.start << PAGE_SHIFT; 1384 if ((offset + size) <= adev->gmc.visible_vram_size) 1385 return 0; 1386 1387 /* Can't move a pinned BO to visible VRAM */ 1388 if (abo->pin_count > 0) 1389 return -EINVAL; 1390 1391 /* hurrah the memory is not visible ! */ 1392 atomic64_inc(&adev->num_vram_cpu_page_faults); 1393 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1394 AMDGPU_GEM_DOMAIN_GTT); 1395 1396 /* Avoid costly evictions; only set GTT as a busy placement */ 1397 abo->placement.num_busy_placement = 1; 1398 abo->placement.busy_placement = &abo->placements[1]; 1399 1400 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1401 if (unlikely(r != 0)) 1402 return r; 1403 1404 offset = bo->mem.start << PAGE_SHIFT; 1405 /* this should never happen */ 1406 if (bo->mem.mem_type == TTM_PL_VRAM && 1407 (offset + size) > adev->gmc.visible_vram_size) 1408 return -EINVAL; 1409 1410 return 0; 1411 } 1412 1413 /** 1414 * amdgpu_bo_fence - add fence to buffer object 1415 * 1416 * @bo: buffer object in question 1417 * @fence: fence to add 1418 * @shared: true if fence should be added shared 1419 * 1420 */ 1421 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1422 bool shared) 1423 { 1424 struct dma_resv *resv = bo->tbo.base.resv; 1425 1426 if (shared) 1427 dma_resv_add_shared_fence(resv, fence); 1428 else 1429 dma_resv_add_excl_fence(resv, fence); 1430 } 1431 1432 /** 1433 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1434 * 1435 * @adev: amdgpu device pointer 1436 * @resv: reservation object to sync to 1437 * @sync_mode: synchronization mode 1438 * @owner: fence owner 1439 * @intr: Whether the wait is interruptible 1440 * 1441 * Extract the fences from the reservation object and waits for them to finish. 1442 * 1443 * Returns: 1444 * 0 on success, errno otherwise. 1445 */ 1446 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1447 enum amdgpu_sync_mode sync_mode, void *owner, 1448 bool intr) 1449 { 1450 struct amdgpu_sync sync; 1451 int r; 1452 1453 amdgpu_sync_create(&sync); 1454 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1455 r = amdgpu_sync_wait(&sync, intr); 1456 amdgpu_sync_free(&sync); 1457 return r; 1458 } 1459 1460 /** 1461 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1462 * @bo: buffer object to wait for 1463 * @owner: fence owner 1464 * @intr: Whether the wait is interruptible 1465 * 1466 * Wrapper to wait for fences in a BO. 1467 * Returns: 1468 * 0 on success, errno otherwise. 1469 */ 1470 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1471 { 1472 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1473 1474 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1475 AMDGPU_SYNC_NE_OWNER, owner, intr); 1476 } 1477 1478 /** 1479 * amdgpu_bo_gpu_offset - return GPU offset of bo 1480 * @bo: amdgpu object for which we query the offset 1481 * 1482 * Note: object should either be pinned or reserved when calling this 1483 * function, it might be useful to add check for this for debugging. 1484 * 1485 * Returns: 1486 * current GPU offset of the object. 1487 */ 1488 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1489 { 1490 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1491 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1492 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); 1493 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1494 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1495 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1496 1497 return amdgpu_bo_gpu_offset_no_check(bo); 1498 } 1499 1500 /** 1501 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1502 * @bo: amdgpu object for which we query the offset 1503 * 1504 * Returns: 1505 * current GPU offset of the object without raising warnings. 1506 */ 1507 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1508 { 1509 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1510 uint64_t offset; 1511 1512 offset = (bo->tbo.mem.start << PAGE_SHIFT) + 1513 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 1514 1515 return amdgpu_gmc_sign_extend(offset); 1516 } 1517 1518 /** 1519 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1520 * @adev: amdgpu device object 1521 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1522 * 1523 * Returns: 1524 * Which of the allowed domains is preferred for pinning the BO for scanout. 1525 */ 1526 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1527 uint32_t domain) 1528 { 1529 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1530 domain = AMDGPU_GEM_DOMAIN_VRAM; 1531 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1532 domain = AMDGPU_GEM_DOMAIN_GTT; 1533 } 1534 return domain; 1535 } 1536