1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 40 41 int amdgpu_ttm_init(struct amdgpu_device *adev); 42 void amdgpu_ttm_fini(struct amdgpu_device *adev); 43 44 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, 45 struct ttm_mem_reg *mem) 46 { 47 u64 ret = 0; 48 if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) { 49 ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) > 50 adev->mc.visible_vram_size ? 51 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : 52 mem->size; 53 } 54 return ret; 55 } 56 57 static void amdgpu_update_memory_usage(struct amdgpu_device *adev, 58 struct ttm_mem_reg *old_mem, 59 struct ttm_mem_reg *new_mem) 60 { 61 u64 vis_size; 62 if (!adev) 63 return; 64 65 if (new_mem) { 66 switch (new_mem->mem_type) { 67 case TTM_PL_TT: 68 atomic64_add(new_mem->size, &adev->gtt_usage); 69 break; 70 case TTM_PL_VRAM: 71 atomic64_add(new_mem->size, &adev->vram_usage); 72 vis_size = amdgpu_get_vis_part_size(adev, new_mem); 73 atomic64_add(vis_size, &adev->vram_vis_usage); 74 break; 75 } 76 } 77 78 if (old_mem) { 79 switch (old_mem->mem_type) { 80 case TTM_PL_TT: 81 atomic64_sub(old_mem->size, &adev->gtt_usage); 82 break; 83 case TTM_PL_VRAM: 84 atomic64_sub(old_mem->size, &adev->vram_usage); 85 vis_size = amdgpu_get_vis_part_size(adev, old_mem); 86 atomic64_sub(vis_size, &adev->vram_vis_usage); 87 break; 88 } 89 } 90 } 91 92 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 93 { 94 struct amdgpu_bo *bo; 95 96 bo = container_of(tbo, struct amdgpu_bo, tbo); 97 98 amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); 99 100 mutex_lock(&bo->adev->gem.mutex); 101 list_del_init(&bo->list); 102 mutex_unlock(&bo->adev->gem.mutex); 103 drm_gem_object_release(&bo->gem_base); 104 amdgpu_bo_unref(&bo->parent); 105 kfree(bo->metadata); 106 kfree(bo); 107 } 108 109 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 110 { 111 if (bo->destroy == &amdgpu_ttm_bo_destroy) 112 return true; 113 return false; 114 } 115 116 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 117 struct ttm_placement *placement, 118 struct ttm_place *placements, 119 u32 domain, u64 flags) 120 { 121 u32 c = 0, i; 122 123 placement->placement = placements; 124 placement->busy_placement = placements; 125 126 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 127 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && 128 adev->mc.visible_vram_size < adev->mc.real_vram_size) { 129 placements[c].fpfn = 130 adev->mc.visible_vram_size >> PAGE_SHIFT; 131 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 132 TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN; 133 } 134 placements[c].fpfn = 0; 135 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 136 TTM_PL_FLAG_VRAM; 137 if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) 138 placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN; 139 } 140 141 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 142 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 143 placements[c].fpfn = 0; 144 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | 145 TTM_PL_FLAG_UNCACHED; 146 } else { 147 placements[c].fpfn = 0; 148 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 149 } 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 153 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 154 placements[c].fpfn = 0; 155 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | 156 TTM_PL_FLAG_UNCACHED; 157 } else { 158 placements[c].fpfn = 0; 159 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 160 } 161 } 162 163 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 164 placements[c].fpfn = 0; 165 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 166 AMDGPU_PL_FLAG_GDS; 167 } 168 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 169 placements[c].fpfn = 0; 170 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 171 AMDGPU_PL_FLAG_GWS; 172 } 173 if (domain & AMDGPU_GEM_DOMAIN_OA) { 174 placements[c].fpfn = 0; 175 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 176 AMDGPU_PL_FLAG_OA; 177 } 178 179 if (!c) { 180 placements[c].fpfn = 0; 181 placements[c++].flags = TTM_PL_MASK_CACHING | 182 TTM_PL_FLAG_SYSTEM; 183 } 184 placement->num_placement = c; 185 placement->num_busy_placement = c; 186 187 for (i = 0; i < c; i++) { 188 if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 189 (placements[i].flags & TTM_PL_FLAG_VRAM) && 190 !placements[i].fpfn) 191 placements[i].lpfn = 192 adev->mc.visible_vram_size >> PAGE_SHIFT; 193 else 194 placements[i].lpfn = 0; 195 } 196 } 197 198 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) 199 { 200 amdgpu_ttm_placement_init(rbo->adev, &rbo->placement, 201 rbo->placements, domain, rbo->flags); 202 } 203 204 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 205 struct ttm_placement *placement) 206 { 207 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 208 209 memcpy(bo->placements, placement->placement, 210 placement->num_placement * sizeof(struct ttm_place)); 211 bo->placement.num_placement = placement->num_placement; 212 bo->placement.num_busy_placement = placement->num_busy_placement; 213 bo->placement.placement = bo->placements; 214 bo->placement.busy_placement = bo->placements; 215 } 216 217 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 218 unsigned long size, int byte_align, 219 bool kernel, u32 domain, u64 flags, 220 struct sg_table *sg, 221 struct ttm_placement *placement, 222 struct reservation_object *resv, 223 struct amdgpu_bo **bo_ptr) 224 { 225 struct amdgpu_bo *bo; 226 enum ttm_bo_type type; 227 unsigned long page_align; 228 size_t acc_size; 229 int r; 230 231 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 232 size = ALIGN(size, PAGE_SIZE); 233 234 if (kernel) { 235 type = ttm_bo_type_kernel; 236 } else if (sg) { 237 type = ttm_bo_type_sg; 238 } else { 239 type = ttm_bo_type_device; 240 } 241 *bo_ptr = NULL; 242 243 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 244 sizeof(struct amdgpu_bo)); 245 246 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 247 if (bo == NULL) 248 return -ENOMEM; 249 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 250 if (unlikely(r)) { 251 kfree(bo); 252 return r; 253 } 254 bo->adev = adev; 255 INIT_LIST_HEAD(&bo->list); 256 INIT_LIST_HEAD(&bo->va); 257 bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | 258 AMDGPU_GEM_DOMAIN_GTT | 259 AMDGPU_GEM_DOMAIN_CPU | 260 AMDGPU_GEM_DOMAIN_GDS | 261 AMDGPU_GEM_DOMAIN_GWS | 262 AMDGPU_GEM_DOMAIN_OA); 263 bo->allowed_domains = bo->prefered_domains; 264 if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 265 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 266 267 bo->flags = flags; 268 269 /* For architectures that don't support WC memory, 270 * mask out the WC flag from the BO 271 */ 272 if (!drm_arch_can_wc_memory()) 273 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 274 275 amdgpu_fill_placement_to_bo(bo, placement); 276 /* Kernel allocation are uninterruptible */ 277 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 278 &bo->placement, page_align, !kernel, NULL, 279 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 280 if (unlikely(r != 0)) { 281 return r; 282 } 283 *bo_ptr = bo; 284 285 trace_amdgpu_bo_create(bo); 286 287 return 0; 288 } 289 290 int amdgpu_bo_create(struct amdgpu_device *adev, 291 unsigned long size, int byte_align, 292 bool kernel, u32 domain, u64 flags, 293 struct sg_table *sg, 294 struct reservation_object *resv, 295 struct amdgpu_bo **bo_ptr) 296 { 297 struct ttm_placement placement = {0}; 298 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 299 300 memset(&placements, 0, 301 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 302 303 amdgpu_ttm_placement_init(adev, &placement, 304 placements, domain, flags); 305 306 return amdgpu_bo_create_restricted(adev, size, byte_align, kernel, 307 domain, flags, sg, &placement, 308 resv, bo_ptr); 309 } 310 311 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 312 { 313 bool is_iomem; 314 int r; 315 316 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 317 return -EPERM; 318 319 if (bo->kptr) { 320 if (ptr) { 321 *ptr = bo->kptr; 322 } 323 return 0; 324 } 325 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 326 if (r) { 327 return r; 328 } 329 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 330 if (ptr) { 331 *ptr = bo->kptr; 332 } 333 return 0; 334 } 335 336 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 337 { 338 if (bo->kptr == NULL) 339 return; 340 bo->kptr = NULL; 341 ttm_bo_kunmap(&bo->kmap); 342 } 343 344 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 345 { 346 if (bo == NULL) 347 return NULL; 348 349 ttm_bo_reference(&bo->tbo); 350 return bo; 351 } 352 353 void amdgpu_bo_unref(struct amdgpu_bo **bo) 354 { 355 struct ttm_buffer_object *tbo; 356 357 if ((*bo) == NULL) 358 return; 359 360 tbo = &((*bo)->tbo); 361 ttm_bo_unref(&tbo); 362 if (tbo == NULL) 363 *bo = NULL; 364 } 365 366 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 367 u64 min_offset, u64 max_offset, 368 u64 *gpu_addr) 369 { 370 int r, i; 371 unsigned fpfn, lpfn; 372 373 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 374 return -EPERM; 375 376 if (WARN_ON_ONCE(min_offset > max_offset)) 377 return -EINVAL; 378 379 if (bo->pin_count) { 380 bo->pin_count++; 381 if (gpu_addr) 382 *gpu_addr = amdgpu_bo_gpu_offset(bo); 383 384 if (max_offset != 0) { 385 u64 domain_start; 386 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 387 domain_start = bo->adev->mc.vram_start; 388 else 389 domain_start = bo->adev->mc.gtt_start; 390 WARN_ON_ONCE(max_offset < 391 (amdgpu_bo_gpu_offset(bo) - domain_start)); 392 } 393 394 return 0; 395 } 396 amdgpu_ttm_placement_from_domain(bo, domain); 397 for (i = 0; i < bo->placement.num_placement; i++) { 398 /* force to pin into visible video ram */ 399 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 400 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 401 (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) { 402 if (WARN_ON_ONCE(min_offset > 403 bo->adev->mc.visible_vram_size)) 404 return -EINVAL; 405 fpfn = min_offset >> PAGE_SHIFT; 406 lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT; 407 } else { 408 fpfn = min_offset >> PAGE_SHIFT; 409 lpfn = max_offset >> PAGE_SHIFT; 410 } 411 if (fpfn > bo->placements[i].fpfn) 412 bo->placements[i].fpfn = fpfn; 413 if (!bo->placements[i].lpfn || 414 (lpfn && lpfn < bo->placements[i].lpfn)) 415 bo->placements[i].lpfn = lpfn; 416 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 417 } 418 419 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 420 if (likely(r == 0)) { 421 bo->pin_count = 1; 422 if (gpu_addr != NULL) 423 *gpu_addr = amdgpu_bo_gpu_offset(bo); 424 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 425 bo->adev->vram_pin_size += amdgpu_bo_size(bo); 426 else 427 bo->adev->gart_pin_size += amdgpu_bo_size(bo); 428 } else { 429 dev_err(bo->adev->dev, "%p pin failed\n", bo); 430 } 431 return r; 432 } 433 434 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 435 { 436 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 437 } 438 439 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 440 { 441 int r, i; 442 443 if (!bo->pin_count) { 444 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo); 445 return 0; 446 } 447 bo->pin_count--; 448 if (bo->pin_count) 449 return 0; 450 for (i = 0; i < bo->placement.num_placement; i++) { 451 bo->placements[i].lpfn = 0; 452 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 453 } 454 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 455 if (likely(r == 0)) { 456 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 457 bo->adev->vram_pin_size -= amdgpu_bo_size(bo); 458 else 459 bo->adev->gart_pin_size -= amdgpu_bo_size(bo); 460 } else { 461 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo); 462 } 463 return r; 464 } 465 466 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 467 { 468 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 469 if (0 && (adev->flags & AMD_IS_APU)) { 470 /* Useless to evict on IGP chips */ 471 return 0; 472 } 473 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 474 } 475 476 void amdgpu_bo_force_delete(struct amdgpu_device *adev) 477 { 478 struct amdgpu_bo *bo, *n; 479 480 if (list_empty(&adev->gem.objects)) { 481 return; 482 } 483 dev_err(adev->dev, "Userspace still has active objects !\n"); 484 list_for_each_entry_safe(bo, n, &adev->gem.objects, list) { 485 dev_err(adev->dev, "%p %p %lu %lu force free\n", 486 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 487 *((unsigned long *)&bo->gem_base.refcount)); 488 mutex_lock(&bo->adev->gem.mutex); 489 list_del_init(&bo->list); 490 mutex_unlock(&bo->adev->gem.mutex); 491 /* this should unref the ttm bo */ 492 drm_gem_object_unreference_unlocked(&bo->gem_base); 493 } 494 } 495 496 int amdgpu_bo_init(struct amdgpu_device *adev) 497 { 498 /* Add an MTRR for the VRAM */ 499 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 500 adev->mc.aper_size); 501 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 502 adev->mc.mc_vram_size >> 20, 503 (unsigned long long)adev->mc.aper_size >> 20); 504 DRM_INFO("RAM width %dbits DDR\n", 505 adev->mc.vram_width); 506 return amdgpu_ttm_init(adev); 507 } 508 509 void amdgpu_bo_fini(struct amdgpu_device *adev) 510 { 511 amdgpu_ttm_fini(adev); 512 arch_phys_wc_del(adev->mc.vram_mtrr); 513 } 514 515 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 516 struct vm_area_struct *vma) 517 { 518 return ttm_fbdev_mmap(vma, &bo->tbo); 519 } 520 521 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 522 { 523 if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 524 return -EINVAL; 525 526 bo->tiling_flags = tiling_flags; 527 return 0; 528 } 529 530 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 531 { 532 lockdep_assert_held(&bo->tbo.resv->lock.base); 533 534 if (tiling_flags) 535 *tiling_flags = bo->tiling_flags; 536 } 537 538 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 539 uint32_t metadata_size, uint64_t flags) 540 { 541 void *buffer; 542 543 if (!metadata_size) { 544 if (bo->metadata_size) { 545 kfree(bo->metadata); 546 bo->metadata_size = 0; 547 } 548 return 0; 549 } 550 551 if (metadata == NULL) 552 return -EINVAL; 553 554 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 555 if (buffer == NULL) 556 return -ENOMEM; 557 558 kfree(bo->metadata); 559 bo->metadata_flags = flags; 560 bo->metadata = buffer; 561 bo->metadata_size = metadata_size; 562 563 return 0; 564 } 565 566 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 567 size_t buffer_size, uint32_t *metadata_size, 568 uint64_t *flags) 569 { 570 if (!buffer && !metadata_size) 571 return -EINVAL; 572 573 if (buffer) { 574 if (buffer_size < bo->metadata_size) 575 return -EINVAL; 576 577 if (bo->metadata_size) 578 memcpy(buffer, bo->metadata, bo->metadata_size); 579 } 580 581 if (metadata_size) 582 *metadata_size = bo->metadata_size; 583 if (flags) 584 *flags = bo->metadata_flags; 585 586 return 0; 587 } 588 589 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 590 struct ttm_mem_reg *new_mem) 591 { 592 struct amdgpu_bo *rbo; 593 594 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 595 return; 596 597 rbo = container_of(bo, struct amdgpu_bo, tbo); 598 amdgpu_vm_bo_invalidate(rbo->adev, rbo); 599 600 /* update statistics */ 601 if (!new_mem) 602 return; 603 604 /* move_notify is called before move happens */ 605 amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem); 606 } 607 608 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 609 { 610 struct amdgpu_device *adev; 611 struct amdgpu_bo *abo; 612 unsigned long offset, size, lpfn; 613 int i, r; 614 615 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 616 return 0; 617 618 abo = container_of(bo, struct amdgpu_bo, tbo); 619 adev = abo->adev; 620 if (bo->mem.mem_type != TTM_PL_VRAM) 621 return 0; 622 623 size = bo->mem.num_pages << PAGE_SHIFT; 624 offset = bo->mem.start << PAGE_SHIFT; 625 if ((offset + size) <= adev->mc.visible_vram_size) 626 return 0; 627 628 /* hurrah the memory is not visible ! */ 629 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); 630 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 631 for (i = 0; i < abo->placement.num_placement; i++) { 632 /* Force into visible VRAM */ 633 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && 634 (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn)) 635 abo->placements[i].lpfn = lpfn; 636 } 637 r = ttm_bo_validate(bo, &abo->placement, false, false); 638 if (unlikely(r == -ENOMEM)) { 639 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 640 return ttm_bo_validate(bo, &abo->placement, false, false); 641 } else if (unlikely(r != 0)) { 642 return r; 643 } 644 645 offset = bo->mem.start << PAGE_SHIFT; 646 /* this should never happen */ 647 if ((offset + size) > adev->mc.visible_vram_size) 648 return -EINVAL; 649 650 return 0; 651 } 652 653 /** 654 * amdgpu_bo_fence - add fence to buffer object 655 * 656 * @bo: buffer object in question 657 * @fence: fence to add 658 * @shared: true if fence should be added shared 659 * 660 */ 661 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, 662 bool shared) 663 { 664 struct reservation_object *resv = bo->tbo.resv; 665 666 if (shared) 667 reservation_object_add_shared_fence(resv, fence); 668 else 669 reservation_object_add_excl_fence(resv, fence); 670 } 671