1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include <drm/amdgpu_drm.h>
36 #include <drm/drm_cache.h>
37 #include "amdgpu.h"
38 #include "amdgpu_trace.h"
39 
40 
41 int amdgpu_ttm_init(struct amdgpu_device *adev);
42 void amdgpu_ttm_fini(struct amdgpu_device *adev);
43 
44 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
45 						struct ttm_mem_reg *mem)
46 {
47 	u64 ret = 0;
48 	if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
49 		ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
50 			   adev->mc.visible_vram_size ?
51 			   adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
52 			   mem->size;
53 	}
54 	return ret;
55 }
56 
57 static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
58 		       struct ttm_mem_reg *old_mem,
59 		       struct ttm_mem_reg *new_mem)
60 {
61 	u64 vis_size;
62 	if (!adev)
63 		return;
64 
65 	if (new_mem) {
66 		switch (new_mem->mem_type) {
67 		case TTM_PL_TT:
68 			atomic64_add(new_mem->size, &adev->gtt_usage);
69 			break;
70 		case TTM_PL_VRAM:
71 			atomic64_add(new_mem->size, &adev->vram_usage);
72 			vis_size = amdgpu_get_vis_part_size(adev, new_mem);
73 			atomic64_add(vis_size, &adev->vram_vis_usage);
74 			break;
75 		}
76 	}
77 
78 	if (old_mem) {
79 		switch (old_mem->mem_type) {
80 		case TTM_PL_TT:
81 			atomic64_sub(old_mem->size, &adev->gtt_usage);
82 			break;
83 		case TTM_PL_VRAM:
84 			atomic64_sub(old_mem->size, &adev->vram_usage);
85 			vis_size = amdgpu_get_vis_part_size(adev, old_mem);
86 			atomic64_sub(vis_size, &adev->vram_vis_usage);
87 			break;
88 		}
89 	}
90 }
91 
92 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
93 {
94 	struct amdgpu_bo *bo;
95 
96 	bo = container_of(tbo, struct amdgpu_bo, tbo);
97 
98 	amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
99 
100 	drm_gem_object_release(&bo->gem_base);
101 	amdgpu_bo_unref(&bo->parent);
102 	kfree(bo->metadata);
103 	kfree(bo);
104 }
105 
106 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
107 {
108 	if (bo->destroy == &amdgpu_ttm_bo_destroy)
109 		return true;
110 	return false;
111 }
112 
113 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
114 				      struct ttm_placement *placement,
115 				      struct ttm_place *placements,
116 				      u32 domain, u64 flags)
117 {
118 	u32 c = 0, i;
119 
120 	placement->placement = placements;
121 	placement->busy_placement = placements;
122 
123 	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
124 		if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
125 			adev->mc.visible_vram_size < adev->mc.real_vram_size) {
126 			placements[c].fpfn =
127 				adev->mc.visible_vram_size >> PAGE_SHIFT;
128 			placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
129 				TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN;
130 		}
131 		placements[c].fpfn = 0;
132 		placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
133 			TTM_PL_FLAG_VRAM;
134 		if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
135 			placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;
136 	}
137 
138 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
139 		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
140 			placements[c].fpfn = 0;
141 			placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
142 				TTM_PL_FLAG_UNCACHED;
143 		} else {
144 			placements[c].fpfn = 0;
145 			placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
146 		}
147 	}
148 
149 	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
150 		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
151 			placements[c].fpfn = 0;
152 			placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
153 				TTM_PL_FLAG_UNCACHED;
154 		} else {
155 			placements[c].fpfn = 0;
156 			placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
157 		}
158 	}
159 
160 	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
161 		placements[c].fpfn = 0;
162 		placements[c++].flags = TTM_PL_FLAG_UNCACHED |
163 			AMDGPU_PL_FLAG_GDS;
164 	}
165 	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
166 		placements[c].fpfn = 0;
167 		placements[c++].flags = TTM_PL_FLAG_UNCACHED |
168 			AMDGPU_PL_FLAG_GWS;
169 	}
170 	if (domain & AMDGPU_GEM_DOMAIN_OA) {
171 		placements[c].fpfn = 0;
172 		placements[c++].flags = TTM_PL_FLAG_UNCACHED |
173 			AMDGPU_PL_FLAG_OA;
174 	}
175 
176 	if (!c) {
177 		placements[c].fpfn = 0;
178 		placements[c++].flags = TTM_PL_MASK_CACHING |
179 			TTM_PL_FLAG_SYSTEM;
180 	}
181 	placement->num_placement = c;
182 	placement->num_busy_placement = c;
183 
184 	for (i = 0; i < c; i++) {
185 		if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
186 			(placements[i].flags & TTM_PL_FLAG_VRAM) &&
187 			!placements[i].fpfn)
188 			placements[i].lpfn =
189 				adev->mc.visible_vram_size >> PAGE_SHIFT;
190 		else
191 			placements[i].lpfn = 0;
192 	}
193 }
194 
195 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
196 {
197 	amdgpu_ttm_placement_init(rbo->adev, &rbo->placement,
198 				  rbo->placements, domain, rbo->flags);
199 }
200 
201 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
202 					struct ttm_placement *placement)
203 {
204 	BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
205 
206 	memcpy(bo->placements, placement->placement,
207 	       placement->num_placement * sizeof(struct ttm_place));
208 	bo->placement.num_placement = placement->num_placement;
209 	bo->placement.num_busy_placement = placement->num_busy_placement;
210 	bo->placement.placement = bo->placements;
211 	bo->placement.busy_placement = bo->placements;
212 }
213 
214 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
215 				unsigned long size, int byte_align,
216 				bool kernel, u32 domain, u64 flags,
217 				struct sg_table *sg,
218 				struct ttm_placement *placement,
219 				struct reservation_object *resv,
220 				struct amdgpu_bo **bo_ptr)
221 {
222 	struct amdgpu_bo *bo;
223 	enum ttm_bo_type type;
224 	unsigned long page_align;
225 	size_t acc_size;
226 	int r;
227 
228 	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
229 	size = ALIGN(size, PAGE_SIZE);
230 
231 	if (kernel) {
232 		type = ttm_bo_type_kernel;
233 	} else if (sg) {
234 		type = ttm_bo_type_sg;
235 	} else {
236 		type = ttm_bo_type_device;
237 	}
238 	*bo_ptr = NULL;
239 
240 	acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
241 				       sizeof(struct amdgpu_bo));
242 
243 	bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
244 	if (bo == NULL)
245 		return -ENOMEM;
246 	r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
247 	if (unlikely(r)) {
248 		kfree(bo);
249 		return r;
250 	}
251 	bo->adev = adev;
252 	INIT_LIST_HEAD(&bo->list);
253 	INIT_LIST_HEAD(&bo->va);
254 	bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
255 					 AMDGPU_GEM_DOMAIN_GTT |
256 					 AMDGPU_GEM_DOMAIN_CPU |
257 					 AMDGPU_GEM_DOMAIN_GDS |
258 					 AMDGPU_GEM_DOMAIN_GWS |
259 					 AMDGPU_GEM_DOMAIN_OA);
260 	bo->allowed_domains = bo->prefered_domains;
261 	if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
262 		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
263 
264 	bo->flags = flags;
265 
266 	/* For architectures that don't support WC memory,
267 	 * mask out the WC flag from the BO
268 	 */
269 	if (!drm_arch_can_wc_memory())
270 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
271 
272 	amdgpu_fill_placement_to_bo(bo, placement);
273 	/* Kernel allocation are uninterruptible */
274 	r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
275 			&bo->placement, page_align, !kernel, NULL,
276 			acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
277 	if (unlikely(r != 0)) {
278 		return r;
279 	}
280 	*bo_ptr = bo;
281 
282 	trace_amdgpu_bo_create(bo);
283 
284 	return 0;
285 }
286 
287 int amdgpu_bo_create(struct amdgpu_device *adev,
288 		     unsigned long size, int byte_align,
289 		     bool kernel, u32 domain, u64 flags,
290 		     struct sg_table *sg,
291 		     struct reservation_object *resv,
292 		     struct amdgpu_bo **bo_ptr)
293 {
294 	struct ttm_placement placement = {0};
295 	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
296 
297 	memset(&placements, 0,
298 	       (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
299 
300 	amdgpu_ttm_placement_init(adev, &placement,
301 				  placements, domain, flags);
302 
303 	return amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
304 					   domain, flags, sg, &placement,
305 					   resv, bo_ptr);
306 }
307 
308 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
309 {
310 	bool is_iomem;
311 	long r;
312 
313 	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
314 		return -EPERM;
315 
316 	if (bo->kptr) {
317 		if (ptr) {
318 			*ptr = bo->kptr;
319 		}
320 		return 0;
321 	}
322 
323 	r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
324 						MAX_SCHEDULE_TIMEOUT);
325 	if (r < 0)
326 		return r;
327 
328 	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
329 	if (r)
330 		return r;
331 
332 	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
333 	if (ptr)
334 		*ptr = bo->kptr;
335 
336 	return 0;
337 }
338 
339 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
340 {
341 	if (bo->kptr == NULL)
342 		return;
343 	bo->kptr = NULL;
344 	ttm_bo_kunmap(&bo->kmap);
345 }
346 
347 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
348 {
349 	if (bo == NULL)
350 		return NULL;
351 
352 	ttm_bo_reference(&bo->tbo);
353 	return bo;
354 }
355 
356 void amdgpu_bo_unref(struct amdgpu_bo **bo)
357 {
358 	struct ttm_buffer_object *tbo;
359 
360 	if ((*bo) == NULL)
361 		return;
362 
363 	tbo = &((*bo)->tbo);
364 	ttm_bo_unref(&tbo);
365 	if (tbo == NULL)
366 		*bo = NULL;
367 }
368 
369 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
370 			     u64 min_offset, u64 max_offset,
371 			     u64 *gpu_addr)
372 {
373 	int r, i;
374 	unsigned fpfn, lpfn;
375 
376 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
377 		return -EPERM;
378 
379 	if (WARN_ON_ONCE(min_offset > max_offset))
380 		return -EINVAL;
381 
382 	if (bo->pin_count) {
383 		bo->pin_count++;
384 		if (gpu_addr)
385 			*gpu_addr = amdgpu_bo_gpu_offset(bo);
386 
387 		if (max_offset != 0) {
388 			u64 domain_start;
389 			if (domain == AMDGPU_GEM_DOMAIN_VRAM)
390 				domain_start = bo->adev->mc.vram_start;
391 			else
392 				domain_start = bo->adev->mc.gtt_start;
393 			WARN_ON_ONCE(max_offset <
394 				     (amdgpu_bo_gpu_offset(bo) - domain_start));
395 		}
396 
397 		return 0;
398 	}
399 	amdgpu_ttm_placement_from_domain(bo, domain);
400 	for (i = 0; i < bo->placement.num_placement; i++) {
401 		/* force to pin into visible video ram */
402 		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
403 		    !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
404 		    (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) {
405 			if (WARN_ON_ONCE(min_offset >
406 					 bo->adev->mc.visible_vram_size))
407 				return -EINVAL;
408 			fpfn = min_offset >> PAGE_SHIFT;
409 			lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
410 		} else {
411 			fpfn = min_offset >> PAGE_SHIFT;
412 			lpfn = max_offset >> PAGE_SHIFT;
413 		}
414 		if (fpfn > bo->placements[i].fpfn)
415 			bo->placements[i].fpfn = fpfn;
416 		if (!bo->placements[i].lpfn ||
417 		    (lpfn && lpfn < bo->placements[i].lpfn))
418 			bo->placements[i].lpfn = lpfn;
419 		bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
420 	}
421 
422 	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
423 	if (likely(r == 0)) {
424 		bo->pin_count = 1;
425 		if (gpu_addr != NULL)
426 			*gpu_addr = amdgpu_bo_gpu_offset(bo);
427 		if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
428 			bo->adev->vram_pin_size += amdgpu_bo_size(bo);
429 			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
430 				bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
431 		} else
432 			bo->adev->gart_pin_size += amdgpu_bo_size(bo);
433 	} else {
434 		dev_err(bo->adev->dev, "%p pin failed\n", bo);
435 	}
436 	return r;
437 }
438 
439 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
440 {
441 	return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
442 }
443 
444 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
445 {
446 	int r, i;
447 
448 	if (!bo->pin_count) {
449 		dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
450 		return 0;
451 	}
452 	bo->pin_count--;
453 	if (bo->pin_count)
454 		return 0;
455 	for (i = 0; i < bo->placement.num_placement; i++) {
456 		bo->placements[i].lpfn = 0;
457 		bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
458 	}
459 	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
460 	if (likely(r == 0)) {
461 		if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
462 			bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
463 			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
464 				bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
465 		} else
466 			bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
467 	} else {
468 		dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
469 	}
470 	return r;
471 }
472 
473 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
474 {
475 	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
476 	if (0 && (adev->flags & AMD_IS_APU)) {
477 		/* Useless to evict on IGP chips */
478 		return 0;
479 	}
480 	return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
481 }
482 
483 static const char *amdgpu_vram_names[] = {
484 	"UNKNOWN",
485 	"GDDR1",
486 	"DDR2",
487 	"GDDR3",
488 	"GDDR4",
489 	"GDDR5",
490 	"HBM",
491 	"DDR3"
492 };
493 
494 int amdgpu_bo_init(struct amdgpu_device *adev)
495 {
496 	/* Add an MTRR for the VRAM */
497 	adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
498 					      adev->mc.aper_size);
499 	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
500 		adev->mc.mc_vram_size >> 20,
501 		(unsigned long long)adev->mc.aper_size >> 20);
502 	DRM_INFO("RAM width %dbits %s\n",
503 		 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
504 	return amdgpu_ttm_init(adev);
505 }
506 
507 void amdgpu_bo_fini(struct amdgpu_device *adev)
508 {
509 	amdgpu_ttm_fini(adev);
510 	arch_phys_wc_del(adev->mc.vram_mtrr);
511 }
512 
513 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
514 			     struct vm_area_struct *vma)
515 {
516 	return ttm_fbdev_mmap(vma, &bo->tbo);
517 }
518 
519 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
520 {
521 	if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
522 		return -EINVAL;
523 
524 	bo->tiling_flags = tiling_flags;
525 	return 0;
526 }
527 
528 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
529 {
530 	lockdep_assert_held(&bo->tbo.resv->lock.base);
531 
532 	if (tiling_flags)
533 		*tiling_flags = bo->tiling_flags;
534 }
535 
536 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
537 			    uint32_t metadata_size, uint64_t flags)
538 {
539 	void *buffer;
540 
541 	if (!metadata_size) {
542 		if (bo->metadata_size) {
543 			kfree(bo->metadata);
544 			bo->metadata = NULL;
545 			bo->metadata_size = 0;
546 		}
547 		return 0;
548 	}
549 
550 	if (metadata == NULL)
551 		return -EINVAL;
552 
553 	buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
554 	if (buffer == NULL)
555 		return -ENOMEM;
556 
557 	kfree(bo->metadata);
558 	bo->metadata_flags = flags;
559 	bo->metadata = buffer;
560 	bo->metadata_size = metadata_size;
561 
562 	return 0;
563 }
564 
565 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
566 			   size_t buffer_size, uint32_t *metadata_size,
567 			   uint64_t *flags)
568 {
569 	if (!buffer && !metadata_size)
570 		return -EINVAL;
571 
572 	if (buffer) {
573 		if (buffer_size < bo->metadata_size)
574 			return -EINVAL;
575 
576 		if (bo->metadata_size)
577 			memcpy(buffer, bo->metadata, bo->metadata_size);
578 	}
579 
580 	if (metadata_size)
581 		*metadata_size = bo->metadata_size;
582 	if (flags)
583 		*flags = bo->metadata_flags;
584 
585 	return 0;
586 }
587 
588 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
589 			   struct ttm_mem_reg *new_mem)
590 {
591 	struct amdgpu_bo *rbo;
592 
593 	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
594 		return;
595 
596 	rbo = container_of(bo, struct amdgpu_bo, tbo);
597 	amdgpu_vm_bo_invalidate(rbo->adev, rbo);
598 
599 	/* update statistics */
600 	if (!new_mem)
601 		return;
602 
603 	/* move_notify is called before move happens */
604 	amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
605 }
606 
607 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
608 {
609 	struct amdgpu_device *adev;
610 	struct amdgpu_bo *abo;
611 	unsigned long offset, size, lpfn;
612 	int i, r;
613 
614 	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
615 		return 0;
616 
617 	abo = container_of(bo, struct amdgpu_bo, tbo);
618 	adev = abo->adev;
619 	if (bo->mem.mem_type != TTM_PL_VRAM)
620 		return 0;
621 
622 	size = bo->mem.num_pages << PAGE_SHIFT;
623 	offset = bo->mem.start << PAGE_SHIFT;
624 	if ((offset + size) <= adev->mc.visible_vram_size)
625 		return 0;
626 
627 	/* Can't move a pinned BO to visible VRAM */
628 	if (abo->pin_count > 0)
629 		return -EINVAL;
630 
631 	/* hurrah the memory is not visible ! */
632 	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
633 	lpfn =	adev->mc.visible_vram_size >> PAGE_SHIFT;
634 	for (i = 0; i < abo->placement.num_placement; i++) {
635 		/* Force into visible VRAM */
636 		if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
637 		    (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn))
638 			abo->placements[i].lpfn = lpfn;
639 	}
640 	r = ttm_bo_validate(bo, &abo->placement, false, false);
641 	if (unlikely(r == -ENOMEM)) {
642 		amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
643 		return ttm_bo_validate(bo, &abo->placement, false, false);
644 	} else if (unlikely(r != 0)) {
645 		return r;
646 	}
647 
648 	offset = bo->mem.start << PAGE_SHIFT;
649 	/* this should never happen */
650 	if ((offset + size) > adev->mc.visible_vram_size)
651 		return -EINVAL;
652 
653 	return 0;
654 }
655 
656 /**
657  * amdgpu_bo_fence - add fence to buffer object
658  *
659  * @bo: buffer object in question
660  * @fence: fence to add
661  * @shared: true if fence should be added shared
662  *
663  */
664 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
665 		     bool shared)
666 {
667 	struct reservation_object *resv = bo->tbo.resv;
668 
669 	if (shared)
670 		reservation_object_add_shared_fence(resv, fence);
671 	else
672 		reservation_object_add_excl_fence(resv, fence);
673 }
674