1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 40 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 41 { 42 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 43 struct amdgpu_bo *bo; 44 45 bo = container_of(tbo, struct amdgpu_bo, tbo); 46 47 amdgpu_bo_kunmap(bo); 48 49 drm_gem_object_release(&bo->gem_base); 50 amdgpu_bo_unref(&bo->parent); 51 if (!list_empty(&bo->shadow_list)) { 52 mutex_lock(&adev->shadow_list_lock); 53 list_del_init(&bo->shadow_list); 54 mutex_unlock(&adev->shadow_list_lock); 55 } 56 kfree(bo->metadata); 57 kfree(bo); 58 } 59 60 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 61 { 62 if (bo->destroy == &amdgpu_ttm_bo_destroy) 63 return true; 64 return false; 65 } 66 67 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 68 struct ttm_placement *placement, 69 struct ttm_place *places, 70 u32 domain, u64 flags) 71 { 72 u32 c = 0; 73 74 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 75 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 76 77 places[c].fpfn = 0; 78 places[c].lpfn = 0; 79 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 80 TTM_PL_FLAG_VRAM; 81 82 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 83 places[c].lpfn = visible_pfn; 84 else 85 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 86 87 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 88 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 89 c++; 90 } 91 92 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 93 places[c].fpfn = 0; 94 places[c].lpfn = 0; 95 places[c].flags = TTM_PL_FLAG_TT; 96 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 97 places[c].flags |= TTM_PL_FLAG_WC | 98 TTM_PL_FLAG_UNCACHED; 99 else 100 places[c].flags |= TTM_PL_FLAG_CACHED; 101 c++; 102 } 103 104 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 105 places[c].fpfn = 0; 106 places[c].lpfn = 0; 107 places[c].flags = TTM_PL_FLAG_SYSTEM; 108 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 109 places[c].flags |= TTM_PL_FLAG_WC | 110 TTM_PL_FLAG_UNCACHED; 111 else 112 places[c].flags |= TTM_PL_FLAG_CACHED; 113 c++; 114 } 115 116 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 117 places[c].fpfn = 0; 118 places[c].lpfn = 0; 119 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 120 c++; 121 } 122 123 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 124 places[c].fpfn = 0; 125 places[c].lpfn = 0; 126 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 127 c++; 128 } 129 130 if (domain & AMDGPU_GEM_DOMAIN_OA) { 131 places[c].fpfn = 0; 132 places[c].lpfn = 0; 133 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 134 c++; 135 } 136 137 if (!c) { 138 places[c].fpfn = 0; 139 places[c].lpfn = 0; 140 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 141 c++; 142 } 143 144 placement->num_placement = c; 145 placement->placement = places; 146 147 placement->num_busy_placement = c; 148 placement->busy_placement = places; 149 } 150 151 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 152 { 153 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 154 155 amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements, 156 domain, abo->flags); 157 } 158 159 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 160 struct ttm_placement *placement) 161 { 162 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 163 164 memcpy(bo->placements, placement->placement, 165 placement->num_placement * sizeof(struct ttm_place)); 166 bo->placement.num_placement = placement->num_placement; 167 bo->placement.num_busy_placement = placement->num_busy_placement; 168 bo->placement.placement = bo->placements; 169 bo->placement.busy_placement = bo->placements; 170 } 171 172 /** 173 * amdgpu_bo_create_reserved - create reserved BO for kernel use 174 * 175 * @adev: amdgpu device object 176 * @size: size for the new BO 177 * @align: alignment for the new BO 178 * @domain: where to place it 179 * @bo_ptr: resulting BO 180 * @gpu_addr: GPU addr of the pinned BO 181 * @cpu_addr: optional CPU address mapping 182 * 183 * Allocates and pins a BO for kernel internal use, and returns it still 184 * reserved. 185 * 186 * Returns 0 on success, negative error code otherwise. 187 */ 188 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 189 unsigned long size, int align, 190 u32 domain, struct amdgpu_bo **bo_ptr, 191 u64 *gpu_addr, void **cpu_addr) 192 { 193 bool free = false; 194 int r; 195 196 if (!*bo_ptr) { 197 r = amdgpu_bo_create(adev, size, align, true, domain, 198 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 199 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 200 NULL, NULL, 0, bo_ptr); 201 if (r) { 202 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 203 r); 204 return r; 205 } 206 free = true; 207 } 208 209 r = amdgpu_bo_reserve(*bo_ptr, false); 210 if (r) { 211 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 212 goto error_free; 213 } 214 215 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr); 216 if (r) { 217 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 218 goto error_unreserve; 219 } 220 221 if (cpu_addr) { 222 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 223 if (r) { 224 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 225 goto error_unreserve; 226 } 227 } 228 229 return 0; 230 231 error_unreserve: 232 amdgpu_bo_unreserve(*bo_ptr); 233 234 error_free: 235 if (free) 236 amdgpu_bo_unref(bo_ptr); 237 238 return r; 239 } 240 241 /** 242 * amdgpu_bo_create_kernel - create BO for kernel use 243 * 244 * @adev: amdgpu device object 245 * @size: size for the new BO 246 * @align: alignment for the new BO 247 * @domain: where to place it 248 * @bo_ptr: resulting BO 249 * @gpu_addr: GPU addr of the pinned BO 250 * @cpu_addr: optional CPU address mapping 251 * 252 * Allocates and pins a BO for kernel internal use. 253 * 254 * Returns 0 on success, negative error code otherwise. 255 */ 256 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 257 unsigned long size, int align, 258 u32 domain, struct amdgpu_bo **bo_ptr, 259 u64 *gpu_addr, void **cpu_addr) 260 { 261 int r; 262 263 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 264 gpu_addr, cpu_addr); 265 266 if (r) 267 return r; 268 269 amdgpu_bo_unreserve(*bo_ptr); 270 271 return 0; 272 } 273 274 /** 275 * amdgpu_bo_free_kernel - free BO for kernel use 276 * 277 * @bo: amdgpu BO to free 278 * 279 * unmaps and unpin a BO for kernel internal use. 280 */ 281 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 282 void **cpu_addr) 283 { 284 if (*bo == NULL) 285 return; 286 287 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 288 if (cpu_addr) 289 amdgpu_bo_kunmap(*bo); 290 291 amdgpu_bo_unpin(*bo); 292 amdgpu_bo_unreserve(*bo); 293 } 294 amdgpu_bo_unref(bo); 295 296 if (gpu_addr) 297 *gpu_addr = 0; 298 299 if (cpu_addr) 300 *cpu_addr = NULL; 301 } 302 303 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 304 unsigned long size, int byte_align, 305 bool kernel, u32 domain, u64 flags, 306 struct sg_table *sg, 307 struct ttm_placement *placement, 308 struct reservation_object *resv, 309 uint64_t init_value, 310 struct amdgpu_bo **bo_ptr) 311 { 312 struct amdgpu_bo *bo; 313 enum ttm_bo_type type; 314 unsigned long page_align; 315 u64 initial_bytes_moved, bytes_moved; 316 size_t acc_size; 317 int r; 318 319 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 320 size = ALIGN(size, PAGE_SIZE); 321 322 if (kernel) { 323 type = ttm_bo_type_kernel; 324 } else if (sg) { 325 type = ttm_bo_type_sg; 326 } else { 327 type = ttm_bo_type_device; 328 } 329 *bo_ptr = NULL; 330 331 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 332 sizeof(struct amdgpu_bo)); 333 334 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 335 if (bo == NULL) 336 return -ENOMEM; 337 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 338 if (unlikely(r)) { 339 kfree(bo); 340 return r; 341 } 342 INIT_LIST_HEAD(&bo->shadow_list); 343 INIT_LIST_HEAD(&bo->va); 344 bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | 345 AMDGPU_GEM_DOMAIN_GTT | 346 AMDGPU_GEM_DOMAIN_CPU | 347 AMDGPU_GEM_DOMAIN_GDS | 348 AMDGPU_GEM_DOMAIN_GWS | 349 AMDGPU_GEM_DOMAIN_OA); 350 bo->allowed_domains = bo->preferred_domains; 351 if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 352 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 353 354 bo->flags = flags; 355 356 #ifdef CONFIG_X86_32 357 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 358 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 359 */ 360 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 361 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 362 /* Don't try to enable write-combining when it can't work, or things 363 * may be slow 364 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 365 */ 366 367 #ifndef CONFIG_COMPILE_TEST 368 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 369 thanks to write-combining 370 #endif 371 372 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 373 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 374 "better performance thanks to write-combining\n"); 375 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 376 #else 377 /* For architectures that don't support WC memory, 378 * mask out the WC flag from the BO 379 */ 380 if (!drm_arch_can_wc_memory()) 381 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 382 #endif 383 384 amdgpu_fill_placement_to_bo(bo, placement); 385 /* Kernel allocation are uninterruptible */ 386 387 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); 388 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, 389 &bo->placement, page_align, !kernel, NULL, 390 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 391 bytes_moved = atomic64_read(&adev->num_bytes_moved) - 392 initial_bytes_moved; 393 if (adev->mc.visible_vram_size < adev->mc.real_vram_size && 394 bo->tbo.mem.mem_type == TTM_PL_VRAM && 395 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) 396 amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved); 397 else 398 amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0); 399 400 if (unlikely(r != 0)) 401 return r; 402 403 if (kernel) 404 bo->tbo.priority = 1; 405 406 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 407 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 408 struct dma_fence *fence; 409 410 r = amdgpu_fill_buffer(bo, init_value, bo->tbo.resv, &fence); 411 if (unlikely(r)) 412 goto fail_unreserve; 413 414 amdgpu_bo_fence(bo, fence, false); 415 dma_fence_put(bo->tbo.moving); 416 bo->tbo.moving = dma_fence_get(fence); 417 dma_fence_put(fence); 418 } 419 if (!resv) 420 amdgpu_bo_unreserve(bo); 421 *bo_ptr = bo; 422 423 trace_amdgpu_bo_create(bo); 424 425 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 426 if (type == ttm_bo_type_device) 427 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 428 429 return 0; 430 431 fail_unreserve: 432 if (!resv) 433 ww_mutex_unlock(&bo->tbo.resv->lock); 434 amdgpu_bo_unref(&bo); 435 return r; 436 } 437 438 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 439 unsigned long size, int byte_align, 440 struct amdgpu_bo *bo) 441 { 442 struct ttm_placement placement = {0}; 443 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 444 int r; 445 446 if (bo->shadow) 447 return 0; 448 449 bo->flags |= AMDGPU_GEM_CREATE_SHADOW; 450 memset(&placements, 0, 451 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 452 453 amdgpu_ttm_placement_init(adev, &placement, 454 placements, AMDGPU_GEM_DOMAIN_GTT, 455 AMDGPU_GEM_CREATE_CPU_GTT_USWC); 456 457 r = amdgpu_bo_create_restricted(adev, size, byte_align, true, 458 AMDGPU_GEM_DOMAIN_GTT, 459 AMDGPU_GEM_CREATE_CPU_GTT_USWC, 460 NULL, &placement, 461 bo->tbo.resv, 462 0, 463 &bo->shadow); 464 if (!r) { 465 bo->shadow->parent = amdgpu_bo_ref(bo); 466 mutex_lock(&adev->shadow_list_lock); 467 list_add_tail(&bo->shadow_list, &adev->shadow_list); 468 mutex_unlock(&adev->shadow_list_lock); 469 } 470 471 return r; 472 } 473 474 /* init_value will only take effect when flags contains 475 * AMDGPU_GEM_CREATE_VRAM_CLEARED. 476 */ 477 int amdgpu_bo_create(struct amdgpu_device *adev, 478 unsigned long size, int byte_align, 479 bool kernel, u32 domain, u64 flags, 480 struct sg_table *sg, 481 struct reservation_object *resv, 482 uint64_t init_value, 483 struct amdgpu_bo **bo_ptr) 484 { 485 struct ttm_placement placement = {0}; 486 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 487 int r; 488 489 memset(&placements, 0, 490 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 491 492 amdgpu_ttm_placement_init(adev, &placement, 493 placements, domain, flags); 494 495 r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, 496 domain, flags, sg, &placement, 497 resv, init_value, bo_ptr); 498 if (r) 499 return r; 500 501 if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) { 502 if (!resv) { 503 r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL); 504 WARN_ON(r != 0); 505 } 506 507 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr)); 508 509 if (!resv) 510 ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock); 511 512 if (r) 513 amdgpu_bo_unref(bo_ptr); 514 } 515 516 return r; 517 } 518 519 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 520 struct amdgpu_ring *ring, 521 struct amdgpu_bo *bo, 522 struct reservation_object *resv, 523 struct dma_fence **fence, 524 bool direct) 525 526 { 527 struct amdgpu_bo *shadow = bo->shadow; 528 uint64_t bo_addr, shadow_addr; 529 int r; 530 531 if (!shadow) 532 return -EINVAL; 533 534 bo_addr = amdgpu_bo_gpu_offset(bo); 535 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 536 537 r = reservation_object_reserve_shared(bo->tbo.resv); 538 if (r) 539 goto err; 540 541 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr, 542 amdgpu_bo_size(bo), resv, fence, 543 direct, false); 544 if (!r) 545 amdgpu_bo_fence(bo, *fence, true); 546 547 err: 548 return r; 549 } 550 551 int amdgpu_bo_validate(struct amdgpu_bo *bo) 552 { 553 uint32_t domain; 554 int r; 555 556 if (bo->pin_count) 557 return 0; 558 559 domain = bo->preferred_domains; 560 561 retry: 562 amdgpu_ttm_placement_from_domain(bo, domain); 563 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 564 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 565 domain = bo->allowed_domains; 566 goto retry; 567 } 568 569 return r; 570 } 571 572 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 573 struct amdgpu_ring *ring, 574 struct amdgpu_bo *bo, 575 struct reservation_object *resv, 576 struct dma_fence **fence, 577 bool direct) 578 579 { 580 struct amdgpu_bo *shadow = bo->shadow; 581 uint64_t bo_addr, shadow_addr; 582 int r; 583 584 if (!shadow) 585 return -EINVAL; 586 587 bo_addr = amdgpu_bo_gpu_offset(bo); 588 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 589 590 r = reservation_object_reserve_shared(bo->tbo.resv); 591 if (r) 592 goto err; 593 594 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr, 595 amdgpu_bo_size(bo), resv, fence, 596 direct, false); 597 if (!r) 598 amdgpu_bo_fence(bo, *fence, true); 599 600 err: 601 return r; 602 } 603 604 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 605 { 606 void *kptr; 607 long r; 608 609 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 610 return -EPERM; 611 612 kptr = amdgpu_bo_kptr(bo); 613 if (kptr) { 614 if (ptr) 615 *ptr = kptr; 616 return 0; 617 } 618 619 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 620 MAX_SCHEDULE_TIMEOUT); 621 if (r < 0) 622 return r; 623 624 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 625 if (r) 626 return r; 627 628 if (ptr) 629 *ptr = amdgpu_bo_kptr(bo); 630 631 return 0; 632 } 633 634 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 635 { 636 bool is_iomem; 637 638 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 639 } 640 641 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 642 { 643 if (bo->kmap.bo) 644 ttm_bo_kunmap(&bo->kmap); 645 } 646 647 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 648 { 649 if (bo == NULL) 650 return NULL; 651 652 ttm_bo_reference(&bo->tbo); 653 return bo; 654 } 655 656 void amdgpu_bo_unref(struct amdgpu_bo **bo) 657 { 658 struct ttm_buffer_object *tbo; 659 660 if ((*bo) == NULL) 661 return; 662 663 tbo = &((*bo)->tbo); 664 ttm_bo_unref(&tbo); 665 if (tbo == NULL) 666 *bo = NULL; 667 } 668 669 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 670 u64 min_offset, u64 max_offset, 671 u64 *gpu_addr) 672 { 673 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 674 int r, i; 675 unsigned fpfn, lpfn; 676 677 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 678 return -EPERM; 679 680 if (WARN_ON_ONCE(min_offset > max_offset)) 681 return -EINVAL; 682 683 /* A shared bo cannot be migrated to VRAM */ 684 if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM)) 685 return -EINVAL; 686 687 if (bo->pin_count) { 688 uint32_t mem_type = bo->tbo.mem.mem_type; 689 690 if (domain != amdgpu_mem_type_to_domain(mem_type)) 691 return -EINVAL; 692 693 bo->pin_count++; 694 if (gpu_addr) 695 *gpu_addr = amdgpu_bo_gpu_offset(bo); 696 697 if (max_offset != 0) { 698 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 699 WARN_ON_ONCE(max_offset < 700 (amdgpu_bo_gpu_offset(bo) - domain_start)); 701 } 702 703 return 0; 704 } 705 706 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 707 amdgpu_ttm_placement_from_domain(bo, domain); 708 for (i = 0; i < bo->placement.num_placement; i++) { 709 /* force to pin into visible video ram */ 710 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 711 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 712 (!max_offset || max_offset > 713 adev->mc.visible_vram_size)) { 714 if (WARN_ON_ONCE(min_offset > 715 adev->mc.visible_vram_size)) 716 return -EINVAL; 717 fpfn = min_offset >> PAGE_SHIFT; 718 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 719 } else { 720 fpfn = min_offset >> PAGE_SHIFT; 721 lpfn = max_offset >> PAGE_SHIFT; 722 } 723 if (fpfn > bo->placements[i].fpfn) 724 bo->placements[i].fpfn = fpfn; 725 if (!bo->placements[i].lpfn || 726 (lpfn && lpfn < bo->placements[i].lpfn)) 727 bo->placements[i].lpfn = lpfn; 728 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 729 } 730 731 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 732 if (unlikely(r)) { 733 dev_err(adev->dev, "%p pin failed\n", bo); 734 goto error; 735 } 736 737 bo->pin_count = 1; 738 if (gpu_addr != NULL) { 739 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); 740 if (unlikely(r)) { 741 dev_err(adev->dev, "%p bind failed\n", bo); 742 goto error; 743 } 744 *gpu_addr = amdgpu_bo_gpu_offset(bo); 745 } 746 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 747 adev->vram_pin_size += amdgpu_bo_size(bo); 748 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 749 adev->invisible_pin_size += amdgpu_bo_size(bo); 750 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 751 adev->gart_pin_size += amdgpu_bo_size(bo); 752 } 753 754 error: 755 return r; 756 } 757 758 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 759 { 760 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 761 } 762 763 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 764 { 765 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 766 int r, i; 767 768 if (!bo->pin_count) { 769 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 770 return 0; 771 } 772 bo->pin_count--; 773 if (bo->pin_count) 774 return 0; 775 for (i = 0; i < bo->placement.num_placement; i++) { 776 bo->placements[i].lpfn = 0; 777 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 778 } 779 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 780 if (unlikely(r)) { 781 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 782 goto error; 783 } 784 785 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 786 adev->vram_pin_size -= amdgpu_bo_size(bo); 787 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 788 adev->invisible_pin_size -= amdgpu_bo_size(bo); 789 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 790 adev->gart_pin_size -= amdgpu_bo_size(bo); 791 } 792 793 error: 794 return r; 795 } 796 797 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 798 { 799 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 800 if (0 && (adev->flags & AMD_IS_APU)) { 801 /* Useless to evict on IGP chips */ 802 return 0; 803 } 804 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 805 } 806 807 static const char *amdgpu_vram_names[] = { 808 "UNKNOWN", 809 "GDDR1", 810 "DDR2", 811 "GDDR3", 812 "GDDR4", 813 "GDDR5", 814 "HBM", 815 "DDR3" 816 }; 817 818 int amdgpu_bo_init(struct amdgpu_device *adev) 819 { 820 /* reserve PAT memory space to WC for VRAM */ 821 arch_io_reserve_memtype_wc(adev->mc.aper_base, 822 adev->mc.aper_size); 823 824 /* Add an MTRR for the VRAM */ 825 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 826 adev->mc.aper_size); 827 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 828 adev->mc.mc_vram_size >> 20, 829 (unsigned long long)adev->mc.aper_size >> 20); 830 DRM_INFO("RAM width %dbits %s\n", 831 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); 832 return amdgpu_ttm_init(adev); 833 } 834 835 void amdgpu_bo_fini(struct amdgpu_device *adev) 836 { 837 amdgpu_ttm_fini(adev); 838 arch_phys_wc_del(adev->mc.vram_mtrr); 839 arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size); 840 } 841 842 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 843 struct vm_area_struct *vma) 844 { 845 return ttm_fbdev_mmap(vma, &bo->tbo); 846 } 847 848 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 849 { 850 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 851 852 if (adev->family <= AMDGPU_FAMILY_CZ && 853 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 854 return -EINVAL; 855 856 bo->tiling_flags = tiling_flags; 857 return 0; 858 } 859 860 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 861 { 862 lockdep_assert_held(&bo->tbo.resv->lock.base); 863 864 if (tiling_flags) 865 *tiling_flags = bo->tiling_flags; 866 } 867 868 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 869 uint32_t metadata_size, uint64_t flags) 870 { 871 void *buffer; 872 873 if (!metadata_size) { 874 if (bo->metadata_size) { 875 kfree(bo->metadata); 876 bo->metadata = NULL; 877 bo->metadata_size = 0; 878 } 879 return 0; 880 } 881 882 if (metadata == NULL) 883 return -EINVAL; 884 885 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 886 if (buffer == NULL) 887 return -ENOMEM; 888 889 kfree(bo->metadata); 890 bo->metadata_flags = flags; 891 bo->metadata = buffer; 892 bo->metadata_size = metadata_size; 893 894 return 0; 895 } 896 897 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 898 size_t buffer_size, uint32_t *metadata_size, 899 uint64_t *flags) 900 { 901 if (!buffer && !metadata_size) 902 return -EINVAL; 903 904 if (buffer) { 905 if (buffer_size < bo->metadata_size) 906 return -EINVAL; 907 908 if (bo->metadata_size) 909 memcpy(buffer, bo->metadata, bo->metadata_size); 910 } 911 912 if (metadata_size) 913 *metadata_size = bo->metadata_size; 914 if (flags) 915 *flags = bo->metadata_flags; 916 917 return 0; 918 } 919 920 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 921 bool evict, 922 struct ttm_mem_reg *new_mem) 923 { 924 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 925 struct amdgpu_bo *abo; 926 struct ttm_mem_reg *old_mem = &bo->mem; 927 928 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 929 return; 930 931 abo = container_of(bo, struct amdgpu_bo, tbo); 932 amdgpu_vm_bo_invalidate(adev, abo); 933 934 amdgpu_bo_kunmap(abo); 935 936 /* remember the eviction */ 937 if (evict) 938 atomic64_inc(&adev->num_evictions); 939 940 /* update statistics */ 941 if (!new_mem) 942 return; 943 944 /* move_notify is called before move happens */ 945 trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 946 } 947 948 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 949 { 950 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 951 struct amdgpu_bo *abo; 952 unsigned long offset, size; 953 int r; 954 955 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 956 return 0; 957 958 abo = container_of(bo, struct amdgpu_bo, tbo); 959 960 /* Remember that this BO was accessed by the CPU */ 961 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 962 963 if (bo->mem.mem_type != TTM_PL_VRAM) 964 return 0; 965 966 size = bo->mem.num_pages << PAGE_SHIFT; 967 offset = bo->mem.start << PAGE_SHIFT; 968 if ((offset + size) <= adev->mc.visible_vram_size) 969 return 0; 970 971 /* Can't move a pinned BO to visible VRAM */ 972 if (abo->pin_count > 0) 973 return -EINVAL; 974 975 /* hurrah the memory is not visible ! */ 976 atomic64_inc(&adev->num_vram_cpu_page_faults); 977 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 978 AMDGPU_GEM_DOMAIN_GTT); 979 980 /* Avoid costly evictions; only set GTT as a busy placement */ 981 abo->placement.num_busy_placement = 1; 982 abo->placement.busy_placement = &abo->placements[1]; 983 984 r = ttm_bo_validate(bo, &abo->placement, false, false); 985 if (unlikely(r != 0)) 986 return r; 987 988 offset = bo->mem.start << PAGE_SHIFT; 989 /* this should never happen */ 990 if (bo->mem.mem_type == TTM_PL_VRAM && 991 (offset + size) > adev->mc.visible_vram_size) 992 return -EINVAL; 993 994 return 0; 995 } 996 997 /** 998 * amdgpu_bo_fence - add fence to buffer object 999 * 1000 * @bo: buffer object in question 1001 * @fence: fence to add 1002 * @shared: true if fence should be added shared 1003 * 1004 */ 1005 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1006 bool shared) 1007 { 1008 struct reservation_object *resv = bo->tbo.resv; 1009 1010 if (shared) 1011 reservation_object_add_shared_fence(resv, fence); 1012 else 1013 reservation_object_add_excl_fence(resv, fence); 1014 } 1015 1016 /** 1017 * amdgpu_bo_gpu_offset - return GPU offset of bo 1018 * @bo: amdgpu object for which we query the offset 1019 * 1020 * Returns current GPU offset of the object. 1021 * 1022 * Note: object should either be pinned or reserved when calling this 1023 * function, it might be useful to add check for this for debugging. 1024 */ 1025 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1026 { 1027 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1028 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && 1029 !amdgpu_ttm_is_bound(bo->tbo.ttm)); 1030 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 1031 !bo->pin_count); 1032 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1033 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1034 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1035 1036 return bo->tbo.offset; 1037 } 1038