1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/amdgpu_drm.h> 37 #include <drm/drm_cache.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 #include "amdgpu_amdkfd.h" 41 42 /** 43 * DOC: amdgpu_object 44 * 45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 46 * represents memory used by driver (VRAM, system memory, etc.). The driver 47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 48 * to create/destroy/set buffer object which are then managed by the kernel TTM 49 * memory manager. 50 * The interfaces are also used internally by kernel clients, including gfx, 51 * uvd, etc. for kernel managed allocations used by the GPU. 52 * 53 */ 54 55 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 56 { 57 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 58 59 amdgpu_bo_kunmap(bo); 60 61 if (bo->tbo.base.import_attach) 62 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 63 drm_gem_object_release(&bo->tbo.base); 64 amdgpu_bo_unref(&bo->parent); 65 kvfree(bo); 66 } 67 68 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 69 { 70 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 71 struct amdgpu_bo_user *ubo; 72 73 ubo = to_amdgpu_bo_user(bo); 74 kfree(ubo->metadata); 75 amdgpu_bo_destroy(tbo); 76 } 77 78 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 79 { 80 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 81 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 82 struct amdgpu_bo_vm *vmbo; 83 84 vmbo = to_amdgpu_bo_vm(bo); 85 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 86 if (!list_empty(&vmbo->shadow_list)) { 87 mutex_lock(&adev->shadow_list_lock); 88 list_del_init(&vmbo->shadow_list); 89 mutex_unlock(&adev->shadow_list_lock); 90 } 91 92 amdgpu_bo_destroy(tbo); 93 } 94 95 /** 96 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 97 * @bo: buffer object to be checked 98 * 99 * Uses destroy function associated with the object to determine if this is 100 * an &amdgpu_bo. 101 * 102 * Returns: 103 * true if the object belongs to &amdgpu_bo, false if not. 104 */ 105 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 106 { 107 if (bo->destroy == &amdgpu_bo_destroy || 108 bo->destroy == &amdgpu_bo_user_destroy || 109 bo->destroy == &amdgpu_bo_vm_destroy) 110 return true; 111 112 return false; 113 } 114 115 /** 116 * amdgpu_bo_placement_from_domain - set buffer's placement 117 * @abo: &amdgpu_bo buffer object whose placement is to be set 118 * @domain: requested domain 119 * 120 * Sets buffer's placement according to requested domain and the buffer's 121 * flags. 122 */ 123 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 124 { 125 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 126 struct ttm_placement *placement = &abo->placement; 127 struct ttm_place *places = abo->placements; 128 u64 flags = abo->flags; 129 u32 c = 0; 130 131 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 132 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 133 134 places[c].fpfn = 0; 135 places[c].lpfn = 0; 136 places[c].mem_type = TTM_PL_VRAM; 137 places[c].flags = 0; 138 139 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 140 places[c].lpfn = visible_pfn; 141 else 142 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 143 144 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 145 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 146 c++; 147 } 148 149 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 150 places[c].fpfn = 0; 151 places[c].lpfn = 0; 152 places[c].mem_type = 153 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 154 AMDGPU_PL_PREEMPT : TTM_PL_TT; 155 places[c].flags = 0; 156 c++; 157 } 158 159 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 160 places[c].fpfn = 0; 161 places[c].lpfn = 0; 162 places[c].mem_type = TTM_PL_SYSTEM; 163 places[c].flags = 0; 164 c++; 165 } 166 167 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 168 places[c].fpfn = 0; 169 places[c].lpfn = 0; 170 places[c].mem_type = AMDGPU_PL_GDS; 171 places[c].flags = 0; 172 c++; 173 } 174 175 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 176 places[c].fpfn = 0; 177 places[c].lpfn = 0; 178 places[c].mem_type = AMDGPU_PL_GWS; 179 places[c].flags = 0; 180 c++; 181 } 182 183 if (domain & AMDGPU_GEM_DOMAIN_OA) { 184 places[c].fpfn = 0; 185 places[c].lpfn = 0; 186 places[c].mem_type = AMDGPU_PL_OA; 187 places[c].flags = 0; 188 c++; 189 } 190 191 if (!c) { 192 places[c].fpfn = 0; 193 places[c].lpfn = 0; 194 places[c].mem_type = TTM_PL_SYSTEM; 195 places[c].flags = 0; 196 c++; 197 } 198 199 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 200 201 placement->num_placement = c; 202 placement->placement = places; 203 204 placement->num_busy_placement = c; 205 placement->busy_placement = places; 206 } 207 208 /** 209 * amdgpu_bo_create_reserved - create reserved BO for kernel use 210 * 211 * @adev: amdgpu device object 212 * @size: size for the new BO 213 * @align: alignment for the new BO 214 * @domain: where to place it 215 * @bo_ptr: used to initialize BOs in structures 216 * @gpu_addr: GPU addr of the pinned BO 217 * @cpu_addr: optional CPU address mapping 218 * 219 * Allocates and pins a BO for kernel internal use, and returns it still 220 * reserved. 221 * 222 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 223 * 224 * Returns: 225 * 0 on success, negative error code otherwise. 226 */ 227 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 228 unsigned long size, int align, 229 u32 domain, struct amdgpu_bo **bo_ptr, 230 u64 *gpu_addr, void **cpu_addr) 231 { 232 struct amdgpu_bo_param bp; 233 bool free = false; 234 int r; 235 236 if (!size) { 237 amdgpu_bo_unref(bo_ptr); 238 return 0; 239 } 240 241 memset(&bp, 0, sizeof(bp)); 242 bp.size = size; 243 bp.byte_align = align; 244 bp.domain = domain; 245 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 246 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 247 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 248 bp.type = ttm_bo_type_kernel; 249 bp.resv = NULL; 250 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 251 252 if (!*bo_ptr) { 253 r = amdgpu_bo_create(adev, &bp, bo_ptr); 254 if (r) { 255 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 256 r); 257 return r; 258 } 259 free = true; 260 } 261 262 r = amdgpu_bo_reserve(*bo_ptr, false); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 265 goto error_free; 266 } 267 268 r = amdgpu_bo_pin(*bo_ptr, domain); 269 if (r) { 270 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 271 goto error_unreserve; 272 } 273 274 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 275 if (r) { 276 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 277 goto error_unpin; 278 } 279 280 if (gpu_addr) 281 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 282 283 if (cpu_addr) { 284 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 285 if (r) { 286 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 287 goto error_unpin; 288 } 289 } 290 291 return 0; 292 293 error_unpin: 294 amdgpu_bo_unpin(*bo_ptr); 295 error_unreserve: 296 amdgpu_bo_unreserve(*bo_ptr); 297 298 error_free: 299 if (free) 300 amdgpu_bo_unref(bo_ptr); 301 302 return r; 303 } 304 305 /** 306 * amdgpu_bo_create_kernel - create BO for kernel use 307 * 308 * @adev: amdgpu device object 309 * @size: size for the new BO 310 * @align: alignment for the new BO 311 * @domain: where to place it 312 * @bo_ptr: used to initialize BOs in structures 313 * @gpu_addr: GPU addr of the pinned BO 314 * @cpu_addr: optional CPU address mapping 315 * 316 * Allocates and pins a BO for kernel internal use. 317 * 318 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 319 * 320 * Returns: 321 * 0 on success, negative error code otherwise. 322 */ 323 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 324 unsigned long size, int align, 325 u32 domain, struct amdgpu_bo **bo_ptr, 326 u64 *gpu_addr, void **cpu_addr) 327 { 328 int r; 329 330 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 331 gpu_addr, cpu_addr); 332 333 if (r) 334 return r; 335 336 if (*bo_ptr) 337 amdgpu_bo_unreserve(*bo_ptr); 338 339 return 0; 340 } 341 342 /** 343 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 344 * 345 * @adev: amdgpu device object 346 * @offset: offset of the BO 347 * @size: size of the BO 348 * @domain: where to place it 349 * @bo_ptr: used to initialize BOs in structures 350 * @cpu_addr: optional CPU address mapping 351 * 352 * Creates a kernel BO at a specific offset in the address space of the domain. 353 * 354 * Returns: 355 * 0 on success, negative error code otherwise. 356 */ 357 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 358 uint64_t offset, uint64_t size, uint32_t domain, 359 struct amdgpu_bo **bo_ptr, void **cpu_addr) 360 { 361 struct ttm_operation_ctx ctx = { false, false }; 362 unsigned int i; 363 int r; 364 365 offset &= PAGE_MASK; 366 size = ALIGN(size, PAGE_SIZE); 367 368 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 369 NULL, cpu_addr); 370 if (r) 371 return r; 372 373 if ((*bo_ptr) == NULL) 374 return 0; 375 376 /* 377 * Remove the original mem node and create a new one at the request 378 * position. 379 */ 380 if (cpu_addr) 381 amdgpu_bo_kunmap(*bo_ptr); 382 383 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 384 385 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 386 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 387 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 388 } 389 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 390 &(*bo_ptr)->tbo.resource, &ctx); 391 if (r) 392 goto error; 393 394 if (cpu_addr) { 395 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 396 if (r) 397 goto error; 398 } 399 400 amdgpu_bo_unreserve(*bo_ptr); 401 return 0; 402 403 error: 404 amdgpu_bo_unreserve(*bo_ptr); 405 amdgpu_bo_unref(bo_ptr); 406 return r; 407 } 408 409 /** 410 * amdgpu_bo_free_kernel - free BO for kernel use 411 * 412 * @bo: amdgpu BO to free 413 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 414 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 415 * 416 * unmaps and unpin a BO for kernel internal use. 417 */ 418 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 419 void **cpu_addr) 420 { 421 if (*bo == NULL) 422 return; 423 424 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 425 if (cpu_addr) 426 amdgpu_bo_kunmap(*bo); 427 428 amdgpu_bo_unpin(*bo); 429 amdgpu_bo_unreserve(*bo); 430 } 431 amdgpu_bo_unref(bo); 432 433 if (gpu_addr) 434 *gpu_addr = 0; 435 436 if (cpu_addr) 437 *cpu_addr = NULL; 438 } 439 440 /* Validate bo size is bit bigger then the request domain */ 441 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 442 unsigned long size, u32 domain) 443 { 444 struct ttm_resource_manager *man = NULL; 445 446 /* 447 * If GTT is part of requested domains the check must succeed to 448 * allow fall back to GTT 449 */ 450 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 451 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 452 453 if (size < (man->size << PAGE_SHIFT)) 454 return true; 455 else 456 goto fail; 457 } 458 459 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 460 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 461 462 if (size < (man->size << PAGE_SHIFT)) 463 return true; 464 else 465 goto fail; 466 } 467 468 469 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 470 return true; 471 472 fail: 473 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 474 man->size << PAGE_SHIFT); 475 return false; 476 } 477 478 bool amdgpu_bo_support_uswc(u64 bo_flags) 479 { 480 481 #ifdef CONFIG_X86_32 482 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 483 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 484 */ 485 return false; 486 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 487 /* Don't try to enable write-combining when it can't work, or things 488 * may be slow 489 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 490 */ 491 492 #ifndef CONFIG_COMPILE_TEST 493 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 494 thanks to write-combining 495 #endif 496 497 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 498 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 499 "better performance thanks to write-combining\n"); 500 return false; 501 #else 502 /* For architectures that don't support WC memory, 503 * mask out the WC flag from the BO 504 */ 505 if (!drm_arch_can_wc_memory()) 506 return false; 507 508 return true; 509 #endif 510 } 511 512 /** 513 * amdgpu_bo_create - create an &amdgpu_bo buffer object 514 * @adev: amdgpu device object 515 * @bp: parameters to be used for the buffer object 516 * @bo_ptr: pointer to the buffer object pointer 517 * 518 * Creates an &amdgpu_bo buffer object. 519 * 520 * Returns: 521 * 0 for success or a negative error code on failure. 522 */ 523 int amdgpu_bo_create(struct amdgpu_device *adev, 524 struct amdgpu_bo_param *bp, 525 struct amdgpu_bo **bo_ptr) 526 { 527 struct ttm_operation_ctx ctx = { 528 .interruptible = (bp->type != ttm_bo_type_kernel), 529 .no_wait_gpu = bp->no_wait_gpu, 530 /* We opt to avoid OOM on system pages allocations */ 531 .gfp_retry_mayfail = true, 532 .allow_res_evict = bp->type != ttm_bo_type_kernel, 533 .resv = bp->resv 534 }; 535 struct amdgpu_bo *bo; 536 unsigned long page_align, size = bp->size; 537 int r; 538 539 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 540 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 541 /* GWS and OA don't need any alignment. */ 542 page_align = bp->byte_align; 543 size <<= PAGE_SHIFT; 544 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 545 /* Both size and alignment must be a multiple of 4. */ 546 page_align = ALIGN(bp->byte_align, 4); 547 size = ALIGN(size, 4) << PAGE_SHIFT; 548 } else { 549 /* Memory should be aligned at least to a page size. */ 550 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 551 size = ALIGN(size, PAGE_SIZE); 552 } 553 554 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 555 return -ENOMEM; 556 557 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 558 559 *bo_ptr = NULL; 560 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 561 if (bo == NULL) 562 return -ENOMEM; 563 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 564 bo->vm_bo = NULL; 565 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 566 bp->domain; 567 bo->allowed_domains = bo->preferred_domains; 568 if (bp->type != ttm_bo_type_kernel && 569 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 570 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 571 572 bo->flags = bp->flags; 573 574 if (!amdgpu_bo_support_uswc(bo->flags)) 575 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 576 577 bo->tbo.bdev = &adev->mman.bdev; 578 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 579 AMDGPU_GEM_DOMAIN_GDS)) 580 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 581 else 582 amdgpu_bo_placement_from_domain(bo, bp->domain); 583 if (bp->type == ttm_bo_type_kernel) 584 bo->tbo.priority = 1; 585 586 if (!bp->destroy) 587 bp->destroy = &amdgpu_bo_destroy; 588 589 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 590 &bo->placement, page_align, &ctx, NULL, 591 bp->resv, bp->destroy); 592 if (unlikely(r != 0)) 593 return r; 594 595 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 596 bo->tbo.resource->mem_type == TTM_PL_VRAM && 597 bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 598 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 599 ctx.bytes_moved); 600 else 601 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 602 603 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 604 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 605 struct dma_fence *fence; 606 607 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 608 if (unlikely(r)) 609 goto fail_unreserve; 610 611 amdgpu_bo_fence(bo, fence, false); 612 dma_fence_put(bo->tbo.moving); 613 bo->tbo.moving = dma_fence_get(fence); 614 dma_fence_put(fence); 615 } 616 if (!bp->resv) 617 amdgpu_bo_unreserve(bo); 618 *bo_ptr = bo; 619 620 trace_amdgpu_bo_create(bo); 621 622 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 623 if (bp->type == ttm_bo_type_device) 624 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 625 626 return 0; 627 628 fail_unreserve: 629 if (!bp->resv) 630 dma_resv_unlock(bo->tbo.base.resv); 631 amdgpu_bo_unref(&bo); 632 return r; 633 } 634 635 /** 636 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 637 * @adev: amdgpu device object 638 * @bp: parameters to be used for the buffer object 639 * @ubo_ptr: pointer to the buffer object pointer 640 * 641 * Create a BO to be used by user application; 642 * 643 * Returns: 644 * 0 for success or a negative error code on failure. 645 */ 646 647 int amdgpu_bo_create_user(struct amdgpu_device *adev, 648 struct amdgpu_bo_param *bp, 649 struct amdgpu_bo_user **ubo_ptr) 650 { 651 struct amdgpu_bo *bo_ptr; 652 int r; 653 654 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 655 bp->destroy = &amdgpu_bo_user_destroy; 656 r = amdgpu_bo_create(adev, bp, &bo_ptr); 657 if (r) 658 return r; 659 660 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 661 return r; 662 } 663 664 /** 665 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 666 * @adev: amdgpu device object 667 * @bp: parameters to be used for the buffer object 668 * @vmbo_ptr: pointer to the buffer object pointer 669 * 670 * Create a BO to be for GPUVM. 671 * 672 * Returns: 673 * 0 for success or a negative error code on failure. 674 */ 675 676 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 677 struct amdgpu_bo_param *bp, 678 struct amdgpu_bo_vm **vmbo_ptr) 679 { 680 struct amdgpu_bo *bo_ptr; 681 int r; 682 683 /* bo_ptr_size will be determined by the caller and it depends on 684 * num of amdgpu_vm_pt entries. 685 */ 686 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 687 bp->destroy = &amdgpu_bo_vm_destroy; 688 r = amdgpu_bo_create(adev, bp, &bo_ptr); 689 if (r) 690 return r; 691 692 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 693 INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list); 694 return r; 695 } 696 697 /** 698 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 699 * 700 * @vmbo: BO that will be inserted into the shadow list 701 * 702 * Insert a BO to the shadow list. 703 */ 704 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 705 { 706 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 707 708 mutex_lock(&adev->shadow_list_lock); 709 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 710 mutex_unlock(&adev->shadow_list_lock); 711 } 712 713 /** 714 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 715 * 716 * @shadow: &amdgpu_bo shadow to be restored 717 * @fence: dma_fence associated with the operation 718 * 719 * Copies a buffer object's shadow content back to the object. 720 * This is used for recovering a buffer from its shadow in case of a gpu 721 * reset where vram context may be lost. 722 * 723 * Returns: 724 * 0 for success or a negative error code on failure. 725 */ 726 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 727 728 { 729 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 730 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 731 uint64_t shadow_addr, parent_addr; 732 733 shadow_addr = amdgpu_bo_gpu_offset(shadow); 734 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 735 736 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 737 amdgpu_bo_size(shadow), NULL, fence, 738 true, false, false); 739 } 740 741 /** 742 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 743 * @bo: &amdgpu_bo buffer object to be mapped 744 * @ptr: kernel virtual address to be returned 745 * 746 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 747 * amdgpu_bo_kptr() to get the kernel virtual address. 748 * 749 * Returns: 750 * 0 for success or a negative error code on failure. 751 */ 752 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 753 { 754 void *kptr; 755 long r; 756 757 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 758 return -EPERM; 759 760 kptr = amdgpu_bo_kptr(bo); 761 if (kptr) { 762 if (ptr) 763 *ptr = kptr; 764 return 0; 765 } 766 767 r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false, 768 MAX_SCHEDULE_TIMEOUT); 769 if (r < 0) 770 return r; 771 772 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap); 773 if (r) 774 return r; 775 776 if (ptr) 777 *ptr = amdgpu_bo_kptr(bo); 778 779 return 0; 780 } 781 782 /** 783 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 784 * @bo: &amdgpu_bo buffer object 785 * 786 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 787 * 788 * Returns: 789 * the virtual address of a buffer object area. 790 */ 791 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 792 { 793 bool is_iomem; 794 795 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 796 } 797 798 /** 799 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 800 * @bo: &amdgpu_bo buffer object to be unmapped 801 * 802 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 803 */ 804 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 805 { 806 if (bo->kmap.bo) 807 ttm_bo_kunmap(&bo->kmap); 808 } 809 810 /** 811 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 812 * @bo: &amdgpu_bo buffer object 813 * 814 * References the contained &ttm_buffer_object. 815 * 816 * Returns: 817 * a refcounted pointer to the &amdgpu_bo buffer object. 818 */ 819 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 820 { 821 if (bo == NULL) 822 return NULL; 823 824 ttm_bo_get(&bo->tbo); 825 return bo; 826 } 827 828 /** 829 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 830 * @bo: &amdgpu_bo buffer object 831 * 832 * Unreferences the contained &ttm_buffer_object and clear the pointer 833 */ 834 void amdgpu_bo_unref(struct amdgpu_bo **bo) 835 { 836 struct ttm_buffer_object *tbo; 837 838 if ((*bo) == NULL) 839 return; 840 841 tbo = &((*bo)->tbo); 842 ttm_bo_put(tbo); 843 *bo = NULL; 844 } 845 846 /** 847 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 848 * @bo: &amdgpu_bo buffer object to be pinned 849 * @domain: domain to be pinned to 850 * @min_offset: the start of requested address range 851 * @max_offset: the end of requested address range 852 * 853 * Pins the buffer object according to requested domain and address range. If 854 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 855 * pin_count and pin_size accordingly. 856 * 857 * Pinning means to lock pages in memory along with keeping them at a fixed 858 * offset. It is required when a buffer can not be moved, for example, when 859 * a display buffer is being scanned out. 860 * 861 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 862 * where to pin a buffer if there are specific restrictions on where a buffer 863 * must be located. 864 * 865 * Returns: 866 * 0 for success or a negative error code on failure. 867 */ 868 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 869 u64 min_offset, u64 max_offset) 870 { 871 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 872 struct ttm_operation_ctx ctx = { false, false }; 873 int r, i; 874 875 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 876 return -EPERM; 877 878 if (WARN_ON_ONCE(min_offset > max_offset)) 879 return -EINVAL; 880 881 /* A shared bo cannot be migrated to VRAM */ 882 if (bo->tbo.base.import_attach) { 883 if (domain & AMDGPU_GEM_DOMAIN_GTT) 884 domain = AMDGPU_GEM_DOMAIN_GTT; 885 else 886 return -EINVAL; 887 } 888 889 if (bo->tbo.pin_count) { 890 uint32_t mem_type = bo->tbo.resource->mem_type; 891 uint32_t mem_flags = bo->tbo.resource->placement; 892 893 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 894 return -EINVAL; 895 896 if ((mem_type == TTM_PL_VRAM) && 897 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 898 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 899 return -EINVAL; 900 901 ttm_bo_pin(&bo->tbo); 902 903 if (max_offset != 0) { 904 u64 domain_start = amdgpu_ttm_domain_start(adev, 905 mem_type); 906 WARN_ON_ONCE(max_offset < 907 (amdgpu_bo_gpu_offset(bo) - domain_start)); 908 } 909 910 return 0; 911 } 912 913 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 914 * See function amdgpu_display_supported_domains() 915 */ 916 domain = amdgpu_bo_get_preferred_domain(adev, domain); 917 918 if (bo->tbo.base.import_attach) 919 dma_buf_pin(bo->tbo.base.import_attach); 920 921 /* force to pin into visible video ram */ 922 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 923 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 924 amdgpu_bo_placement_from_domain(bo, domain); 925 for (i = 0; i < bo->placement.num_placement; i++) { 926 unsigned fpfn, lpfn; 927 928 fpfn = min_offset >> PAGE_SHIFT; 929 lpfn = max_offset >> PAGE_SHIFT; 930 931 if (fpfn > bo->placements[i].fpfn) 932 bo->placements[i].fpfn = fpfn; 933 if (!bo->placements[i].lpfn || 934 (lpfn && lpfn < bo->placements[i].lpfn)) 935 bo->placements[i].lpfn = lpfn; 936 } 937 938 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 939 if (unlikely(r)) { 940 dev_err(adev->dev, "%p pin failed\n", bo); 941 goto error; 942 } 943 944 ttm_bo_pin(&bo->tbo); 945 946 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 947 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 948 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 949 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 950 &adev->visible_pin_size); 951 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 952 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 953 } 954 955 error: 956 return r; 957 } 958 959 /** 960 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 961 * @bo: &amdgpu_bo buffer object to be pinned 962 * @domain: domain to be pinned to 963 * 964 * A simple wrapper to amdgpu_bo_pin_restricted(). 965 * Provides a simpler API for buffers that do not have any strict restrictions 966 * on where a buffer must be located. 967 * 968 * Returns: 969 * 0 for success or a negative error code on failure. 970 */ 971 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 972 { 973 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 974 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 975 } 976 977 /** 978 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 979 * @bo: &amdgpu_bo buffer object to be unpinned 980 * 981 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 982 * Changes placement and pin size accordingly. 983 * 984 * Returns: 985 * 0 for success or a negative error code on failure. 986 */ 987 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 988 { 989 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 990 991 ttm_bo_unpin(&bo->tbo); 992 if (bo->tbo.pin_count) 993 return; 994 995 if (bo->tbo.base.import_attach) 996 dma_buf_unpin(bo->tbo.base.import_attach); 997 998 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 999 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1000 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1001 &adev->visible_pin_size); 1002 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1003 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1004 } 1005 } 1006 1007 static const char *amdgpu_vram_names[] = { 1008 "UNKNOWN", 1009 "GDDR1", 1010 "DDR2", 1011 "GDDR3", 1012 "GDDR4", 1013 "GDDR5", 1014 "HBM", 1015 "DDR3", 1016 "DDR4", 1017 "GDDR6", 1018 "DDR5" 1019 }; 1020 1021 /** 1022 * amdgpu_bo_init - initialize memory manager 1023 * @adev: amdgpu device object 1024 * 1025 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1026 * 1027 * Returns: 1028 * 0 for success or a negative error code on failure. 1029 */ 1030 int amdgpu_bo_init(struct amdgpu_device *adev) 1031 { 1032 /* On A+A platform, VRAM can be mapped as WB */ 1033 if (!adev->gmc.xgmi.connected_to_cpu) { 1034 /* reserve PAT memory space to WC for VRAM */ 1035 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1036 adev->gmc.aper_size); 1037 1038 /* Add an MTRR for the VRAM */ 1039 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1040 adev->gmc.aper_size); 1041 } 1042 1043 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1044 adev->gmc.mc_vram_size >> 20, 1045 (unsigned long long)adev->gmc.aper_size >> 20); 1046 DRM_INFO("RAM width %dbits %s\n", 1047 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1048 return amdgpu_ttm_init(adev); 1049 } 1050 1051 /** 1052 * amdgpu_bo_fini - tear down memory manager 1053 * @adev: amdgpu device object 1054 * 1055 * Reverses amdgpu_bo_init() to tear down memory manager. 1056 */ 1057 void amdgpu_bo_fini(struct amdgpu_device *adev) 1058 { 1059 amdgpu_ttm_fini(adev); 1060 } 1061 1062 /** 1063 * amdgpu_bo_set_tiling_flags - set tiling flags 1064 * @bo: &amdgpu_bo buffer object 1065 * @tiling_flags: new flags 1066 * 1067 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1068 * kernel driver to set the tiling flags on a buffer. 1069 * 1070 * Returns: 1071 * 0 for success or a negative error code on failure. 1072 */ 1073 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1074 { 1075 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1076 struct amdgpu_bo_user *ubo; 1077 1078 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1079 if (adev->family <= AMDGPU_FAMILY_CZ && 1080 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1081 return -EINVAL; 1082 1083 ubo = to_amdgpu_bo_user(bo); 1084 ubo->tiling_flags = tiling_flags; 1085 return 0; 1086 } 1087 1088 /** 1089 * amdgpu_bo_get_tiling_flags - get tiling flags 1090 * @bo: &amdgpu_bo buffer object 1091 * @tiling_flags: returned flags 1092 * 1093 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1094 * set the tiling flags on a buffer. 1095 */ 1096 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1097 { 1098 struct amdgpu_bo_user *ubo; 1099 1100 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1101 dma_resv_assert_held(bo->tbo.base.resv); 1102 ubo = to_amdgpu_bo_user(bo); 1103 1104 if (tiling_flags) 1105 *tiling_flags = ubo->tiling_flags; 1106 } 1107 1108 /** 1109 * amdgpu_bo_set_metadata - set metadata 1110 * @bo: &amdgpu_bo buffer object 1111 * @metadata: new metadata 1112 * @metadata_size: size of the new metadata 1113 * @flags: flags of the new metadata 1114 * 1115 * Sets buffer object's metadata, its size and flags. 1116 * Used via GEM ioctl. 1117 * 1118 * Returns: 1119 * 0 for success or a negative error code on failure. 1120 */ 1121 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1122 uint32_t metadata_size, uint64_t flags) 1123 { 1124 struct amdgpu_bo_user *ubo; 1125 void *buffer; 1126 1127 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1128 ubo = to_amdgpu_bo_user(bo); 1129 if (!metadata_size) { 1130 if (ubo->metadata_size) { 1131 kfree(ubo->metadata); 1132 ubo->metadata = NULL; 1133 ubo->metadata_size = 0; 1134 } 1135 return 0; 1136 } 1137 1138 if (metadata == NULL) 1139 return -EINVAL; 1140 1141 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1142 if (buffer == NULL) 1143 return -ENOMEM; 1144 1145 kfree(ubo->metadata); 1146 ubo->metadata_flags = flags; 1147 ubo->metadata = buffer; 1148 ubo->metadata_size = metadata_size; 1149 1150 return 0; 1151 } 1152 1153 /** 1154 * amdgpu_bo_get_metadata - get metadata 1155 * @bo: &amdgpu_bo buffer object 1156 * @buffer: returned metadata 1157 * @buffer_size: size of the buffer 1158 * @metadata_size: size of the returned metadata 1159 * @flags: flags of the returned metadata 1160 * 1161 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1162 * less than metadata_size. 1163 * Used via GEM ioctl. 1164 * 1165 * Returns: 1166 * 0 for success or a negative error code on failure. 1167 */ 1168 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1169 size_t buffer_size, uint32_t *metadata_size, 1170 uint64_t *flags) 1171 { 1172 struct amdgpu_bo_user *ubo; 1173 1174 if (!buffer && !metadata_size) 1175 return -EINVAL; 1176 1177 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1178 ubo = to_amdgpu_bo_user(bo); 1179 if (metadata_size) 1180 *metadata_size = ubo->metadata_size; 1181 1182 if (buffer) { 1183 if (buffer_size < ubo->metadata_size) 1184 return -EINVAL; 1185 1186 if (ubo->metadata_size) 1187 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1188 } 1189 1190 if (flags) 1191 *flags = ubo->metadata_flags; 1192 1193 return 0; 1194 } 1195 1196 /** 1197 * amdgpu_bo_move_notify - notification about a memory move 1198 * @bo: pointer to a buffer object 1199 * @evict: if this move is evicting the buffer from the graphics address space 1200 * @new_mem: new information of the bufer object 1201 * 1202 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1203 * bookkeeping. 1204 * TTM driver callback which is called when ttm moves a buffer. 1205 */ 1206 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1207 bool evict, 1208 struct ttm_resource *new_mem) 1209 { 1210 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1211 struct amdgpu_bo *abo; 1212 struct ttm_resource *old_mem = bo->resource; 1213 1214 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1215 return; 1216 1217 abo = ttm_to_amdgpu_bo(bo); 1218 amdgpu_vm_bo_invalidate(adev, abo, evict); 1219 1220 amdgpu_bo_kunmap(abo); 1221 1222 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1223 bo->resource->mem_type != TTM_PL_SYSTEM) 1224 dma_buf_move_notify(abo->tbo.base.dma_buf); 1225 1226 /* remember the eviction */ 1227 if (evict) 1228 atomic64_inc(&adev->num_evictions); 1229 1230 /* update statistics */ 1231 if (!new_mem) 1232 return; 1233 1234 /* move_notify is called before move happens */ 1235 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1236 } 1237 1238 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, 1239 uint64_t *gtt_mem, uint64_t *cpu_mem) 1240 { 1241 unsigned int domain; 1242 1243 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1244 switch (domain) { 1245 case AMDGPU_GEM_DOMAIN_VRAM: 1246 *vram_mem += amdgpu_bo_size(bo); 1247 break; 1248 case AMDGPU_GEM_DOMAIN_GTT: 1249 *gtt_mem += amdgpu_bo_size(bo); 1250 break; 1251 case AMDGPU_GEM_DOMAIN_CPU: 1252 default: 1253 *cpu_mem += amdgpu_bo_size(bo); 1254 break; 1255 } 1256 } 1257 1258 /** 1259 * amdgpu_bo_release_notify - notification about a BO being released 1260 * @bo: pointer to a buffer object 1261 * 1262 * Wipes VRAM buffers whose contents should not be leaked before the 1263 * memory is released. 1264 */ 1265 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1266 { 1267 struct dma_fence *fence = NULL; 1268 struct amdgpu_bo *abo; 1269 int r; 1270 1271 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1272 return; 1273 1274 abo = ttm_to_amdgpu_bo(bo); 1275 1276 if (abo->kfd_bo) 1277 amdgpu_amdkfd_release_notify(abo); 1278 1279 /* We only remove the fence if the resv has individualized. */ 1280 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1281 && bo->base.resv != &bo->base._resv); 1282 if (bo->base.resv == &bo->base._resv) 1283 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1284 1285 if (bo->resource->mem_type != TTM_PL_VRAM || 1286 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1287 return; 1288 1289 dma_resv_lock(bo->base.resv, NULL); 1290 1291 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1292 if (!WARN_ON(r)) { 1293 amdgpu_bo_fence(abo, fence, false); 1294 dma_fence_put(fence); 1295 } 1296 1297 dma_resv_unlock(bo->base.resv); 1298 } 1299 1300 /** 1301 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1302 * @bo: pointer to a buffer object 1303 * 1304 * Notifies the driver we are taking a fault on this BO and have reserved it, 1305 * also performs bookkeeping. 1306 * TTM driver callback for dealing with vm faults. 1307 * 1308 * Returns: 1309 * 0 for success or a negative error code on failure. 1310 */ 1311 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1312 { 1313 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1314 struct ttm_operation_ctx ctx = { false, false }; 1315 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1316 unsigned long offset; 1317 int r; 1318 1319 /* Remember that this BO was accessed by the CPU */ 1320 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1321 1322 if (bo->resource->mem_type != TTM_PL_VRAM) 1323 return 0; 1324 1325 offset = bo->resource->start << PAGE_SHIFT; 1326 if ((offset + bo->base.size) <= adev->gmc.visible_vram_size) 1327 return 0; 1328 1329 /* Can't move a pinned BO to visible VRAM */ 1330 if (abo->tbo.pin_count > 0) 1331 return VM_FAULT_SIGBUS; 1332 1333 /* hurrah the memory is not visible ! */ 1334 atomic64_inc(&adev->num_vram_cpu_page_faults); 1335 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1336 AMDGPU_GEM_DOMAIN_GTT); 1337 1338 /* Avoid costly evictions; only set GTT as a busy placement */ 1339 abo->placement.num_busy_placement = 1; 1340 abo->placement.busy_placement = &abo->placements[1]; 1341 1342 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1343 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1344 return VM_FAULT_NOPAGE; 1345 else if (unlikely(r)) 1346 return VM_FAULT_SIGBUS; 1347 1348 offset = bo->resource->start << PAGE_SHIFT; 1349 /* this should never happen */ 1350 if (bo->resource->mem_type == TTM_PL_VRAM && 1351 (offset + bo->base.size) > adev->gmc.visible_vram_size) 1352 return VM_FAULT_SIGBUS; 1353 1354 ttm_bo_move_to_lru_tail_unlocked(bo); 1355 return 0; 1356 } 1357 1358 /** 1359 * amdgpu_bo_fence - add fence to buffer object 1360 * 1361 * @bo: buffer object in question 1362 * @fence: fence to add 1363 * @shared: true if fence should be added shared 1364 * 1365 */ 1366 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1367 bool shared) 1368 { 1369 struct dma_resv *resv = bo->tbo.base.resv; 1370 1371 if (shared) 1372 dma_resv_add_shared_fence(resv, fence); 1373 else 1374 dma_resv_add_excl_fence(resv, fence); 1375 } 1376 1377 /** 1378 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1379 * 1380 * @adev: amdgpu device pointer 1381 * @resv: reservation object to sync to 1382 * @sync_mode: synchronization mode 1383 * @owner: fence owner 1384 * @intr: Whether the wait is interruptible 1385 * 1386 * Extract the fences from the reservation object and waits for them to finish. 1387 * 1388 * Returns: 1389 * 0 on success, errno otherwise. 1390 */ 1391 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1392 enum amdgpu_sync_mode sync_mode, void *owner, 1393 bool intr) 1394 { 1395 struct amdgpu_sync sync; 1396 int r; 1397 1398 amdgpu_sync_create(&sync); 1399 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1400 r = amdgpu_sync_wait(&sync, intr); 1401 amdgpu_sync_free(&sync); 1402 return r; 1403 } 1404 1405 /** 1406 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1407 * @bo: buffer object to wait for 1408 * @owner: fence owner 1409 * @intr: Whether the wait is interruptible 1410 * 1411 * Wrapper to wait for fences in a BO. 1412 * Returns: 1413 * 0 on success, errno otherwise. 1414 */ 1415 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1416 { 1417 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1418 1419 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1420 AMDGPU_SYNC_NE_OWNER, owner, intr); 1421 } 1422 1423 /** 1424 * amdgpu_bo_gpu_offset - return GPU offset of bo 1425 * @bo: amdgpu object for which we query the offset 1426 * 1427 * Note: object should either be pinned or reserved when calling this 1428 * function, it might be useful to add check for this for debugging. 1429 * 1430 * Returns: 1431 * current GPU offset of the object. 1432 */ 1433 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1434 { 1435 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1436 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1437 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1438 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1439 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1440 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1441 1442 return amdgpu_bo_gpu_offset_no_check(bo); 1443 } 1444 1445 /** 1446 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1447 * @bo: amdgpu object for which we query the offset 1448 * 1449 * Returns: 1450 * current GPU offset of the object without raising warnings. 1451 */ 1452 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1453 { 1454 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1455 uint64_t offset; 1456 1457 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1458 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1459 1460 return amdgpu_gmc_sign_extend(offset); 1461 } 1462 1463 /** 1464 * amdgpu_bo_get_preferred_domain - get preferred domain 1465 * @adev: amdgpu device object 1466 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1467 * 1468 * Returns: 1469 * Which of the allowed domains is preferred for allocating the BO. 1470 */ 1471 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1472 uint32_t domain) 1473 { 1474 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1475 domain = AMDGPU_GEM_DOMAIN_VRAM; 1476 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1477 domain = AMDGPU_GEM_DOMAIN_GTT; 1478 } 1479 return domain; 1480 } 1481 1482 #if defined(CONFIG_DEBUG_FS) 1483 #define amdgpu_bo_print_flag(m, bo, flag) \ 1484 do { \ 1485 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1486 seq_printf((m), " " #flag); \ 1487 } \ 1488 } while (0) 1489 1490 /** 1491 * amdgpu_bo_print_info - print BO info in debugfs file 1492 * 1493 * @id: Index or Id of the BO 1494 * @bo: Requested BO for printing info 1495 * @m: debugfs file 1496 * 1497 * Print BO information in debugfs file 1498 * 1499 * Returns: 1500 * Size of the BO in bytes. 1501 */ 1502 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1503 { 1504 struct dma_buf_attachment *attachment; 1505 struct dma_buf *dma_buf; 1506 unsigned int domain; 1507 const char *placement; 1508 unsigned int pin_count; 1509 u64 size; 1510 1511 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1512 switch (domain) { 1513 case AMDGPU_GEM_DOMAIN_VRAM: 1514 placement = "VRAM"; 1515 break; 1516 case AMDGPU_GEM_DOMAIN_GTT: 1517 placement = " GTT"; 1518 break; 1519 case AMDGPU_GEM_DOMAIN_CPU: 1520 default: 1521 placement = " CPU"; 1522 break; 1523 } 1524 1525 size = amdgpu_bo_size(bo); 1526 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1527 id, size, placement); 1528 1529 pin_count = READ_ONCE(bo->tbo.pin_count); 1530 if (pin_count) 1531 seq_printf(m, " pin count %d", pin_count); 1532 1533 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1534 attachment = READ_ONCE(bo->tbo.base.import_attach); 1535 1536 if (attachment) 1537 seq_printf(m, " imported from %p", dma_buf); 1538 else if (dma_buf) 1539 seq_printf(m, " exported as %p", dma_buf); 1540 1541 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1542 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1543 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1544 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1545 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1546 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1547 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1548 1549 seq_puts(m, "\n"); 1550 1551 return size; 1552 } 1553 #endif 1554