1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/amdgpu_drm.h> 37 #include <drm/drm_cache.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 #include "amdgpu_amdkfd.h" 41 42 /** 43 * DOC: amdgpu_object 44 * 45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 46 * represents memory used by driver (VRAM, system memory, etc.). The driver 47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 48 * to create/destroy/set buffer object which are then managed by the kernel TTM 49 * memory manager. 50 * The interfaces are also used internally by kernel clients, including gfx, 51 * uvd, etc. for kernel managed allocations used by the GPU. 52 * 53 */ 54 55 /** 56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 57 * 58 * @bo: &amdgpu_bo buffer object 59 * 60 * This function is called when a BO stops being pinned, and updates the 61 * &amdgpu_device pin_size values accordingly. 62 */ 63 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 64 { 65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 66 67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 70 &adev->visible_pin_size); 71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 73 } 74 } 75 76 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 77 { 78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 80 81 if (bo->tbo.pin_count > 0) 82 amdgpu_bo_subtract_pin_size(bo); 83 84 amdgpu_bo_kunmap(bo); 85 86 if (bo->tbo.base.import_attach) 87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 88 drm_gem_object_release(&bo->tbo.base); 89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 90 if (!list_empty(&bo->shadow_list)) { 91 mutex_lock(&adev->shadow_list_lock); 92 list_del_init(&bo->shadow_list); 93 mutex_unlock(&adev->shadow_list_lock); 94 } 95 amdgpu_bo_unref(&bo->parent); 96 97 kfree(bo->metadata); 98 kfree(bo); 99 } 100 101 /** 102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 103 * @bo: buffer object to be checked 104 * 105 * Uses destroy function associated with the object to determine if this is 106 * an &amdgpu_bo. 107 * 108 * Returns: 109 * true if the object belongs to &amdgpu_bo, false if not. 110 */ 111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 112 { 113 if (bo->destroy == &amdgpu_bo_destroy) 114 return true; 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 137 places[c].fpfn = 0; 138 places[c].lpfn = 0; 139 places[c].mem_type = TTM_PL_VRAM; 140 places[c].flags = 0; 141 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 places[c].lpfn = visible_pfn; 144 else 145 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 146 147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 149 c++; 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 places[c].fpfn = 0; 154 places[c].lpfn = 0; 155 places[c].mem_type = TTM_PL_TT; 156 places[c].flags = 0; 157 c++; 158 } 159 160 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 161 places[c].fpfn = 0; 162 places[c].lpfn = 0; 163 places[c].mem_type = TTM_PL_SYSTEM; 164 places[c].flags = 0; 165 c++; 166 } 167 168 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 169 places[c].fpfn = 0; 170 places[c].lpfn = 0; 171 places[c].mem_type = AMDGPU_PL_GDS; 172 places[c].flags = 0; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].mem_type = AMDGPU_PL_GWS; 180 places[c].flags = 0; 181 c++; 182 } 183 184 if (domain & AMDGPU_GEM_DOMAIN_OA) { 185 places[c].fpfn = 0; 186 places[c].lpfn = 0; 187 places[c].mem_type = AMDGPU_PL_OA; 188 places[c].flags = 0; 189 c++; 190 } 191 192 if (!c) { 193 places[c].fpfn = 0; 194 places[c].lpfn = 0; 195 places[c].mem_type = TTM_PL_SYSTEM; 196 places[c].flags = 0; 197 c++; 198 } 199 200 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 201 202 placement->num_placement = c; 203 placement->placement = places; 204 205 placement->num_busy_placement = c; 206 placement->busy_placement = places; 207 } 208 209 /** 210 * amdgpu_bo_create_reserved - create reserved BO for kernel use 211 * 212 * @adev: amdgpu device object 213 * @size: size for the new BO 214 * @align: alignment for the new BO 215 * @domain: where to place it 216 * @bo_ptr: used to initialize BOs in structures 217 * @gpu_addr: GPU addr of the pinned BO 218 * @cpu_addr: optional CPU address mapping 219 * 220 * Allocates and pins a BO for kernel internal use, and returns it still 221 * reserved. 222 * 223 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 224 * 225 * Returns: 226 * 0 on success, negative error code otherwise. 227 */ 228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 229 unsigned long size, int align, 230 u32 domain, struct amdgpu_bo **bo_ptr, 231 u64 *gpu_addr, void **cpu_addr) 232 { 233 struct amdgpu_bo_param bp; 234 bool free = false; 235 int r; 236 237 if (!size) { 238 amdgpu_bo_unref(bo_ptr); 239 return 0; 240 } 241 242 memset(&bp, 0, sizeof(bp)); 243 bp.size = size; 244 bp.byte_align = align; 245 bp.domain = domain; 246 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 247 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 248 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 249 bp.type = ttm_bo_type_kernel; 250 bp.resv = NULL; 251 252 if (!*bo_ptr) { 253 r = amdgpu_bo_create(adev, &bp, bo_ptr); 254 if (r) { 255 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 256 r); 257 return r; 258 } 259 free = true; 260 } 261 262 r = amdgpu_bo_reserve(*bo_ptr, false); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 265 goto error_free; 266 } 267 268 r = amdgpu_bo_pin(*bo_ptr, domain); 269 if (r) { 270 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 271 goto error_unreserve; 272 } 273 274 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 275 if (r) { 276 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 277 goto error_unpin; 278 } 279 280 if (gpu_addr) 281 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 282 283 if (cpu_addr) { 284 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 285 if (r) { 286 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 287 goto error_unpin; 288 } 289 } 290 291 return 0; 292 293 error_unpin: 294 amdgpu_bo_unpin(*bo_ptr); 295 error_unreserve: 296 amdgpu_bo_unreserve(*bo_ptr); 297 298 error_free: 299 if (free) 300 amdgpu_bo_unref(bo_ptr); 301 302 return r; 303 } 304 305 /** 306 * amdgpu_bo_create_kernel - create BO for kernel use 307 * 308 * @adev: amdgpu device object 309 * @size: size for the new BO 310 * @align: alignment for the new BO 311 * @domain: where to place it 312 * @bo_ptr: used to initialize BOs in structures 313 * @gpu_addr: GPU addr of the pinned BO 314 * @cpu_addr: optional CPU address mapping 315 * 316 * Allocates and pins a BO for kernel internal use. 317 * 318 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 319 * 320 * Returns: 321 * 0 on success, negative error code otherwise. 322 */ 323 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 324 unsigned long size, int align, 325 u32 domain, struct amdgpu_bo **bo_ptr, 326 u64 *gpu_addr, void **cpu_addr) 327 { 328 int r; 329 330 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 331 gpu_addr, cpu_addr); 332 333 if (r) 334 return r; 335 336 if (*bo_ptr) 337 amdgpu_bo_unreserve(*bo_ptr); 338 339 return 0; 340 } 341 342 /** 343 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 344 * 345 * @adev: amdgpu device object 346 * @offset: offset of the BO 347 * @size: size of the BO 348 * @domain: where to place it 349 * @bo_ptr: used to initialize BOs in structures 350 * @cpu_addr: optional CPU address mapping 351 * 352 * Creates a kernel BO at a specific offset in the address space of the domain. 353 * 354 * Returns: 355 * 0 on success, negative error code otherwise. 356 */ 357 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 358 uint64_t offset, uint64_t size, uint32_t domain, 359 struct amdgpu_bo **bo_ptr, void **cpu_addr) 360 { 361 struct ttm_operation_ctx ctx = { false, false }; 362 unsigned int i; 363 int r; 364 365 offset &= PAGE_MASK; 366 size = ALIGN(size, PAGE_SIZE); 367 368 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 369 NULL, cpu_addr); 370 if (r) 371 return r; 372 373 if ((*bo_ptr) == NULL) 374 return 0; 375 376 /* 377 * Remove the original mem node and create a new one at the request 378 * position. 379 */ 380 if (cpu_addr) 381 amdgpu_bo_kunmap(*bo_ptr); 382 383 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); 384 385 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 386 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 387 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 388 } 389 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 390 &(*bo_ptr)->tbo.mem, &ctx); 391 if (r) 392 goto error; 393 394 if (cpu_addr) { 395 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 396 if (r) 397 goto error; 398 } 399 400 amdgpu_bo_unreserve(*bo_ptr); 401 return 0; 402 403 error: 404 amdgpu_bo_unreserve(*bo_ptr); 405 amdgpu_bo_unref(bo_ptr); 406 return r; 407 } 408 409 /** 410 * amdgpu_bo_free_kernel - free BO for kernel use 411 * 412 * @bo: amdgpu BO to free 413 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 414 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 415 * 416 * unmaps and unpin a BO for kernel internal use. 417 */ 418 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 419 void **cpu_addr) 420 { 421 if (*bo == NULL) 422 return; 423 424 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 425 if (cpu_addr) 426 amdgpu_bo_kunmap(*bo); 427 428 amdgpu_bo_unpin(*bo); 429 amdgpu_bo_unreserve(*bo); 430 } 431 amdgpu_bo_unref(bo); 432 433 if (gpu_addr) 434 *gpu_addr = 0; 435 436 if (cpu_addr) 437 *cpu_addr = NULL; 438 } 439 440 /* Validate bo size is bit bigger then the request domain */ 441 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 442 unsigned long size, u32 domain) 443 { 444 struct ttm_resource_manager *man = NULL; 445 446 /* 447 * If GTT is part of requested domains the check must succeed to 448 * allow fall back to GTT 449 */ 450 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 451 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 452 453 if (size < (man->size << PAGE_SHIFT)) 454 return true; 455 else 456 goto fail; 457 } 458 459 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 460 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 461 462 if (size < (man->size << PAGE_SHIFT)) 463 return true; 464 else 465 goto fail; 466 } 467 468 469 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 470 return true; 471 472 fail: 473 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 474 man->size << PAGE_SHIFT); 475 return false; 476 } 477 478 bool amdgpu_bo_support_uswc(u64 bo_flags) 479 { 480 481 #ifdef CONFIG_X86_32 482 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 483 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 484 */ 485 return false; 486 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 487 /* Don't try to enable write-combining when it can't work, or things 488 * may be slow 489 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 490 */ 491 492 #ifndef CONFIG_COMPILE_TEST 493 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 494 thanks to write-combining 495 #endif 496 497 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 498 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 499 "better performance thanks to write-combining\n"); 500 return false; 501 #else 502 /* For architectures that don't support WC memory, 503 * mask out the WC flag from the BO 504 */ 505 if (!drm_arch_can_wc_memory()) 506 return false; 507 508 return true; 509 #endif 510 } 511 512 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 513 struct amdgpu_bo_param *bp, 514 struct amdgpu_bo **bo_ptr) 515 { 516 struct ttm_operation_ctx ctx = { 517 .interruptible = (bp->type != ttm_bo_type_kernel), 518 .no_wait_gpu = bp->no_wait_gpu, 519 /* We opt to avoid OOM on system pages allocations */ 520 .gfp_retry_mayfail = true, 521 .allow_res_evict = bp->type != ttm_bo_type_kernel, 522 .resv = bp->resv 523 }; 524 struct amdgpu_bo *bo; 525 unsigned long page_align, size = bp->size; 526 int r; 527 528 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 529 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 530 /* GWS and OA don't need any alignment. */ 531 page_align = bp->byte_align; 532 size <<= PAGE_SHIFT; 533 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 534 /* Both size and alignment must be a multiple of 4. */ 535 page_align = ALIGN(bp->byte_align, 4); 536 size = ALIGN(size, 4) << PAGE_SHIFT; 537 } else { 538 /* Memory should be aligned at least to a page size. */ 539 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 540 size = ALIGN(size, PAGE_SIZE); 541 } 542 543 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 544 return -ENOMEM; 545 546 *bo_ptr = NULL; 547 548 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 549 if (bo == NULL) 550 return -ENOMEM; 551 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 552 INIT_LIST_HEAD(&bo->shadow_list); 553 bo->vm_bo = NULL; 554 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 555 bp->domain; 556 bo->allowed_domains = bo->preferred_domains; 557 if (bp->type != ttm_bo_type_kernel && 558 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 559 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 560 561 bo->flags = bp->flags; 562 563 if (!amdgpu_bo_support_uswc(bo->flags)) 564 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 565 566 bo->tbo.bdev = &adev->mman.bdev; 567 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 568 AMDGPU_GEM_DOMAIN_GDS)) 569 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 570 else 571 amdgpu_bo_placement_from_domain(bo, bp->domain); 572 if (bp->type == ttm_bo_type_kernel) 573 bo->tbo.priority = 1; 574 575 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 576 &bo->placement, page_align, &ctx, NULL, 577 bp->resv, &amdgpu_bo_destroy); 578 if (unlikely(r != 0)) 579 return r; 580 581 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 582 bo->tbo.mem.mem_type == TTM_PL_VRAM && 583 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 584 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 585 ctx.bytes_moved); 586 else 587 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 588 589 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 590 bo->tbo.mem.mem_type == TTM_PL_VRAM) { 591 struct dma_fence *fence; 592 593 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 594 if (unlikely(r)) 595 goto fail_unreserve; 596 597 amdgpu_bo_fence(bo, fence, false); 598 dma_fence_put(bo->tbo.moving); 599 bo->tbo.moving = dma_fence_get(fence); 600 dma_fence_put(fence); 601 } 602 if (!bp->resv) 603 amdgpu_bo_unreserve(bo); 604 *bo_ptr = bo; 605 606 trace_amdgpu_bo_create(bo); 607 608 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 609 if (bp->type == ttm_bo_type_device) 610 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 611 612 return 0; 613 614 fail_unreserve: 615 if (!bp->resv) 616 dma_resv_unlock(bo->tbo.base.resv); 617 amdgpu_bo_unref(&bo); 618 return r; 619 } 620 621 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 622 unsigned long size, 623 struct amdgpu_bo *bo) 624 { 625 struct amdgpu_bo_param bp; 626 int r; 627 628 if (bo->shadow) 629 return 0; 630 631 memset(&bp, 0, sizeof(bp)); 632 bp.size = size; 633 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 634 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 635 AMDGPU_GEM_CREATE_SHADOW; 636 bp.type = ttm_bo_type_kernel; 637 bp.resv = bo->tbo.base.resv; 638 639 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 640 if (!r) { 641 bo->shadow->parent = amdgpu_bo_ref(bo); 642 mutex_lock(&adev->shadow_list_lock); 643 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 644 mutex_unlock(&adev->shadow_list_lock); 645 } 646 647 return r; 648 } 649 650 /** 651 * amdgpu_bo_create - create an &amdgpu_bo buffer object 652 * @adev: amdgpu device object 653 * @bp: parameters to be used for the buffer object 654 * @bo_ptr: pointer to the buffer object pointer 655 * 656 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 657 * shadow object. 658 * Shadow object is used to backup the original buffer object, and is always 659 * in GTT. 660 * 661 * Returns: 662 * 0 for success or a negative error code on failure. 663 */ 664 int amdgpu_bo_create(struct amdgpu_device *adev, 665 struct amdgpu_bo_param *bp, 666 struct amdgpu_bo **bo_ptr) 667 { 668 u64 flags = bp->flags; 669 int r; 670 671 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 672 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 673 if (r) 674 return r; 675 676 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 677 if (!bp->resv) 678 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 679 NULL)); 680 681 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 682 683 if (!bp->resv) 684 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 685 686 if (r) 687 amdgpu_bo_unref(bo_ptr); 688 } 689 690 return r; 691 } 692 693 /** 694 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 695 * @bo: pointer to the buffer object 696 * 697 * Sets placement according to domain; and changes placement and caching 698 * policy of the buffer object according to the placement. 699 * This is used for validating shadow bos. It calls ttm_bo_validate() to 700 * make sure the buffer is resident where it needs to be. 701 * 702 * Returns: 703 * 0 for success or a negative error code on failure. 704 */ 705 int amdgpu_bo_validate(struct amdgpu_bo *bo) 706 { 707 struct ttm_operation_ctx ctx = { false, false }; 708 uint32_t domain; 709 int r; 710 711 if (bo->tbo.pin_count) 712 return 0; 713 714 domain = bo->preferred_domains; 715 716 retry: 717 amdgpu_bo_placement_from_domain(bo, domain); 718 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 719 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 720 domain = bo->allowed_domains; 721 goto retry; 722 } 723 724 return r; 725 } 726 727 /** 728 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 729 * 730 * @shadow: &amdgpu_bo shadow to be restored 731 * @fence: dma_fence associated with the operation 732 * 733 * Copies a buffer object's shadow content back to the object. 734 * This is used for recovering a buffer from its shadow in case of a gpu 735 * reset where vram context may be lost. 736 * 737 * Returns: 738 * 0 for success or a negative error code on failure. 739 */ 740 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 741 742 { 743 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 744 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 745 uint64_t shadow_addr, parent_addr; 746 747 shadow_addr = amdgpu_bo_gpu_offset(shadow); 748 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 749 750 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 751 amdgpu_bo_size(shadow), NULL, fence, 752 true, false, false); 753 } 754 755 /** 756 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 757 * @bo: &amdgpu_bo buffer object to be mapped 758 * @ptr: kernel virtual address to be returned 759 * 760 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 761 * amdgpu_bo_kptr() to get the kernel virtual address. 762 * 763 * Returns: 764 * 0 for success or a negative error code on failure. 765 */ 766 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 767 { 768 void *kptr; 769 long r; 770 771 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 772 return -EPERM; 773 774 kptr = amdgpu_bo_kptr(bo); 775 if (kptr) { 776 if (ptr) 777 *ptr = kptr; 778 return 0; 779 } 780 781 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 782 MAX_SCHEDULE_TIMEOUT); 783 if (r < 0) 784 return r; 785 786 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.mem.num_pages, &bo->kmap); 787 if (r) 788 return r; 789 790 if (ptr) 791 *ptr = amdgpu_bo_kptr(bo); 792 793 return 0; 794 } 795 796 /** 797 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 798 * @bo: &amdgpu_bo buffer object 799 * 800 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 801 * 802 * Returns: 803 * the virtual address of a buffer object area. 804 */ 805 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 806 { 807 bool is_iomem; 808 809 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 810 } 811 812 /** 813 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 814 * @bo: &amdgpu_bo buffer object to be unmapped 815 * 816 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 817 */ 818 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 819 { 820 if (bo->kmap.bo) 821 ttm_bo_kunmap(&bo->kmap); 822 } 823 824 /** 825 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 826 * @bo: &amdgpu_bo buffer object 827 * 828 * References the contained &ttm_buffer_object. 829 * 830 * Returns: 831 * a refcounted pointer to the &amdgpu_bo buffer object. 832 */ 833 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 834 { 835 if (bo == NULL) 836 return NULL; 837 838 ttm_bo_get(&bo->tbo); 839 return bo; 840 } 841 842 /** 843 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 844 * @bo: &amdgpu_bo buffer object 845 * 846 * Unreferences the contained &ttm_buffer_object and clear the pointer 847 */ 848 void amdgpu_bo_unref(struct amdgpu_bo **bo) 849 { 850 struct ttm_buffer_object *tbo; 851 852 if ((*bo) == NULL) 853 return; 854 855 tbo = &((*bo)->tbo); 856 ttm_bo_put(tbo); 857 *bo = NULL; 858 } 859 860 /** 861 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 862 * @bo: &amdgpu_bo buffer object to be pinned 863 * @domain: domain to be pinned to 864 * @min_offset: the start of requested address range 865 * @max_offset: the end of requested address range 866 * 867 * Pins the buffer object according to requested domain and address range. If 868 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 869 * pin_count and pin_size accordingly. 870 * 871 * Pinning means to lock pages in memory along with keeping them at a fixed 872 * offset. It is required when a buffer can not be moved, for example, when 873 * a display buffer is being scanned out. 874 * 875 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 876 * where to pin a buffer if there are specific restrictions on where a buffer 877 * must be located. 878 * 879 * Returns: 880 * 0 for success or a negative error code on failure. 881 */ 882 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 883 u64 min_offset, u64 max_offset) 884 { 885 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 886 struct ttm_operation_ctx ctx = { false, false }; 887 int r, i; 888 889 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 890 return -EPERM; 891 892 if (WARN_ON_ONCE(min_offset > max_offset)) 893 return -EINVAL; 894 895 /* A shared bo cannot be migrated to VRAM */ 896 if (bo->prime_shared_count || bo->tbo.base.import_attach) { 897 if (domain & AMDGPU_GEM_DOMAIN_GTT) 898 domain = AMDGPU_GEM_DOMAIN_GTT; 899 else 900 return -EINVAL; 901 } 902 903 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 904 * See function amdgpu_display_supported_domains() 905 */ 906 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 907 908 if (bo->tbo.pin_count) { 909 uint32_t mem_type = bo->tbo.mem.mem_type; 910 uint32_t mem_flags = bo->tbo.mem.placement; 911 912 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 913 return -EINVAL; 914 915 if ((mem_type == TTM_PL_VRAM) && 916 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 917 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 918 return -EINVAL; 919 920 ttm_bo_pin(&bo->tbo); 921 922 if (max_offset != 0) { 923 u64 domain_start = amdgpu_ttm_domain_start(adev, 924 mem_type); 925 WARN_ON_ONCE(max_offset < 926 (amdgpu_bo_gpu_offset(bo) - domain_start)); 927 } 928 929 return 0; 930 } 931 932 if (bo->tbo.base.import_attach) 933 dma_buf_pin(bo->tbo.base.import_attach); 934 935 /* force to pin into visible video ram */ 936 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 937 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 938 amdgpu_bo_placement_from_domain(bo, domain); 939 for (i = 0; i < bo->placement.num_placement; i++) { 940 unsigned fpfn, lpfn; 941 942 fpfn = min_offset >> PAGE_SHIFT; 943 lpfn = max_offset >> PAGE_SHIFT; 944 945 if (fpfn > bo->placements[i].fpfn) 946 bo->placements[i].fpfn = fpfn; 947 if (!bo->placements[i].lpfn || 948 (lpfn && lpfn < bo->placements[i].lpfn)) 949 bo->placements[i].lpfn = lpfn; 950 } 951 952 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 953 if (unlikely(r)) { 954 dev_err(adev->dev, "%p pin failed\n", bo); 955 goto error; 956 } 957 958 ttm_bo_pin(&bo->tbo); 959 960 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 961 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 962 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 963 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 964 &adev->visible_pin_size); 965 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 966 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 967 } 968 969 error: 970 return r; 971 } 972 973 /** 974 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 975 * @bo: &amdgpu_bo buffer object to be pinned 976 * @domain: domain to be pinned to 977 * 978 * A simple wrapper to amdgpu_bo_pin_restricted(). 979 * Provides a simpler API for buffers that do not have any strict restrictions 980 * on where a buffer must be located. 981 * 982 * Returns: 983 * 0 for success or a negative error code on failure. 984 */ 985 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 986 { 987 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 988 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 989 } 990 991 /** 992 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 993 * @bo: &amdgpu_bo buffer object to be unpinned 994 * 995 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 996 * Changes placement and pin size accordingly. 997 * 998 * Returns: 999 * 0 for success or a negative error code on failure. 1000 */ 1001 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1002 { 1003 ttm_bo_unpin(&bo->tbo); 1004 if (bo->tbo.pin_count) 1005 return; 1006 1007 amdgpu_bo_subtract_pin_size(bo); 1008 1009 if (bo->tbo.base.import_attach) 1010 dma_buf_unpin(bo->tbo.base.import_attach); 1011 } 1012 1013 /** 1014 * amdgpu_bo_evict_vram - evict VRAM buffers 1015 * @adev: amdgpu device object 1016 * 1017 * Evicts all VRAM buffers on the lru list of the memory type. 1018 * Mainly used for evicting vram at suspend time. 1019 * 1020 * Returns: 1021 * 0 for success or a negative error code on failure. 1022 */ 1023 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1024 { 1025 struct ttm_resource_manager *man; 1026 1027 if (adev->in_s3 && (adev->flags & AMD_IS_APU)) { 1028 /* No need to evict vram on APUs for suspend to ram */ 1029 return 0; 1030 } 1031 1032 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1033 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 1034 } 1035 1036 static const char *amdgpu_vram_names[] = { 1037 "UNKNOWN", 1038 "GDDR1", 1039 "DDR2", 1040 "GDDR3", 1041 "GDDR4", 1042 "GDDR5", 1043 "HBM", 1044 "DDR3", 1045 "DDR4", 1046 "GDDR6", 1047 "DDR5" 1048 }; 1049 1050 /** 1051 * amdgpu_bo_init - initialize memory manager 1052 * @adev: amdgpu device object 1053 * 1054 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1055 * 1056 * Returns: 1057 * 0 for success or a negative error code on failure. 1058 */ 1059 int amdgpu_bo_init(struct amdgpu_device *adev) 1060 { 1061 /* On A+A platform, VRAM can be mapped as WB */ 1062 if (!adev->gmc.xgmi.connected_to_cpu) { 1063 /* reserve PAT memory space to WC for VRAM */ 1064 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1065 adev->gmc.aper_size); 1066 1067 /* Add an MTRR for the VRAM */ 1068 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1069 adev->gmc.aper_size); 1070 } 1071 1072 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1073 adev->gmc.mc_vram_size >> 20, 1074 (unsigned long long)adev->gmc.aper_size >> 20); 1075 DRM_INFO("RAM width %dbits %s\n", 1076 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1077 return amdgpu_ttm_init(adev); 1078 } 1079 1080 /** 1081 * amdgpu_bo_fini - tear down memory manager 1082 * @adev: amdgpu device object 1083 * 1084 * Reverses amdgpu_bo_init() to tear down memory manager. 1085 */ 1086 void amdgpu_bo_fini(struct amdgpu_device *adev) 1087 { 1088 amdgpu_ttm_fini(adev); 1089 if (!adev->gmc.xgmi.connected_to_cpu) { 1090 arch_phys_wc_del(adev->gmc.vram_mtrr); 1091 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1092 } 1093 } 1094 1095 /** 1096 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1097 * @bo: &amdgpu_bo buffer object 1098 * @vma: vma as input from the fbdev mmap method 1099 * 1100 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1101 * 1102 * Returns: 1103 * 0 for success or a negative error code on failure. 1104 */ 1105 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1106 struct vm_area_struct *vma) 1107 { 1108 if (vma->vm_pgoff != 0) 1109 return -EACCES; 1110 1111 return ttm_bo_mmap_obj(vma, &bo->tbo); 1112 } 1113 1114 /** 1115 * amdgpu_bo_set_tiling_flags - set tiling flags 1116 * @bo: &amdgpu_bo buffer object 1117 * @tiling_flags: new flags 1118 * 1119 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1120 * kernel driver to set the tiling flags on a buffer. 1121 * 1122 * Returns: 1123 * 0 for success or a negative error code on failure. 1124 */ 1125 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1126 { 1127 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1128 1129 if (adev->family <= AMDGPU_FAMILY_CZ && 1130 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1131 return -EINVAL; 1132 1133 bo->tiling_flags = tiling_flags; 1134 return 0; 1135 } 1136 1137 /** 1138 * amdgpu_bo_get_tiling_flags - get tiling flags 1139 * @bo: &amdgpu_bo buffer object 1140 * @tiling_flags: returned flags 1141 * 1142 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1143 * set the tiling flags on a buffer. 1144 */ 1145 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1146 { 1147 dma_resv_assert_held(bo->tbo.base.resv); 1148 1149 if (tiling_flags) 1150 *tiling_flags = bo->tiling_flags; 1151 } 1152 1153 /** 1154 * amdgpu_bo_set_metadata - set metadata 1155 * @bo: &amdgpu_bo buffer object 1156 * @metadata: new metadata 1157 * @metadata_size: size of the new metadata 1158 * @flags: flags of the new metadata 1159 * 1160 * Sets buffer object's metadata, its size and flags. 1161 * Used via GEM ioctl. 1162 * 1163 * Returns: 1164 * 0 for success or a negative error code on failure. 1165 */ 1166 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1167 uint32_t metadata_size, uint64_t flags) 1168 { 1169 void *buffer; 1170 1171 if (!metadata_size) { 1172 if (bo->metadata_size) { 1173 kfree(bo->metadata); 1174 bo->metadata = NULL; 1175 bo->metadata_size = 0; 1176 } 1177 return 0; 1178 } 1179 1180 if (metadata == NULL) 1181 return -EINVAL; 1182 1183 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1184 if (buffer == NULL) 1185 return -ENOMEM; 1186 1187 kfree(bo->metadata); 1188 bo->metadata_flags = flags; 1189 bo->metadata = buffer; 1190 bo->metadata_size = metadata_size; 1191 1192 return 0; 1193 } 1194 1195 /** 1196 * amdgpu_bo_get_metadata - get metadata 1197 * @bo: &amdgpu_bo buffer object 1198 * @buffer: returned metadata 1199 * @buffer_size: size of the buffer 1200 * @metadata_size: size of the returned metadata 1201 * @flags: flags of the returned metadata 1202 * 1203 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1204 * less than metadata_size. 1205 * Used via GEM ioctl. 1206 * 1207 * Returns: 1208 * 0 for success or a negative error code on failure. 1209 */ 1210 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1211 size_t buffer_size, uint32_t *metadata_size, 1212 uint64_t *flags) 1213 { 1214 if (!buffer && !metadata_size) 1215 return -EINVAL; 1216 1217 if (buffer) { 1218 if (buffer_size < bo->metadata_size) 1219 return -EINVAL; 1220 1221 if (bo->metadata_size) 1222 memcpy(buffer, bo->metadata, bo->metadata_size); 1223 } 1224 1225 if (metadata_size) 1226 *metadata_size = bo->metadata_size; 1227 if (flags) 1228 *flags = bo->metadata_flags; 1229 1230 return 0; 1231 } 1232 1233 /** 1234 * amdgpu_bo_move_notify - notification about a memory move 1235 * @bo: pointer to a buffer object 1236 * @evict: if this move is evicting the buffer from the graphics address space 1237 * @new_mem: new information of the bufer object 1238 * 1239 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1240 * bookkeeping. 1241 * TTM driver callback which is called when ttm moves a buffer. 1242 */ 1243 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1244 bool evict, 1245 struct ttm_resource *new_mem) 1246 { 1247 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1248 struct amdgpu_bo *abo; 1249 struct ttm_resource *old_mem = &bo->mem; 1250 1251 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1252 return; 1253 1254 abo = ttm_to_amdgpu_bo(bo); 1255 amdgpu_vm_bo_invalidate(adev, abo, evict); 1256 1257 amdgpu_bo_kunmap(abo); 1258 1259 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1260 bo->mem.mem_type != TTM_PL_SYSTEM) 1261 dma_buf_move_notify(abo->tbo.base.dma_buf); 1262 1263 /* remember the eviction */ 1264 if (evict) 1265 atomic64_inc(&adev->num_evictions); 1266 1267 /* update statistics */ 1268 if (!new_mem) 1269 return; 1270 1271 /* move_notify is called before move happens */ 1272 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1273 } 1274 1275 /** 1276 * amdgpu_bo_release_notify - notification about a BO being released 1277 * @bo: pointer to a buffer object 1278 * 1279 * Wipes VRAM buffers whose contents should not be leaked before the 1280 * memory is released. 1281 */ 1282 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1283 { 1284 struct dma_fence *fence = NULL; 1285 struct amdgpu_bo *abo; 1286 int r; 1287 1288 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1289 return; 1290 1291 abo = ttm_to_amdgpu_bo(bo); 1292 1293 if (abo->kfd_bo) 1294 amdgpu_amdkfd_unreserve_memory_limit(abo); 1295 1296 /* We only remove the fence if the resv has individualized. */ 1297 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1298 && bo->base.resv != &bo->base._resv); 1299 if (bo->base.resv == &bo->base._resv) 1300 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1301 1302 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1303 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1304 return; 1305 1306 dma_resv_lock(bo->base.resv, NULL); 1307 1308 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1309 if (!WARN_ON(r)) { 1310 amdgpu_bo_fence(abo, fence, false); 1311 dma_fence_put(fence); 1312 } 1313 1314 dma_resv_unlock(bo->base.resv); 1315 } 1316 1317 /** 1318 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1319 * @bo: pointer to a buffer object 1320 * 1321 * Notifies the driver we are taking a fault on this BO and have reserved it, 1322 * also performs bookkeeping. 1323 * TTM driver callback for dealing with vm faults. 1324 * 1325 * Returns: 1326 * 0 for success or a negative error code on failure. 1327 */ 1328 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1329 { 1330 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1331 struct ttm_operation_ctx ctx = { false, false }; 1332 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1333 unsigned long offset, size; 1334 int r; 1335 1336 /* Remember that this BO was accessed by the CPU */ 1337 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1338 1339 if (bo->mem.mem_type != TTM_PL_VRAM) 1340 return 0; 1341 1342 size = bo->mem.num_pages << PAGE_SHIFT; 1343 offset = bo->mem.start << PAGE_SHIFT; 1344 if ((offset + size) <= adev->gmc.visible_vram_size) 1345 return 0; 1346 1347 /* Can't move a pinned BO to visible VRAM */ 1348 if (abo->tbo.pin_count > 0) 1349 return VM_FAULT_SIGBUS; 1350 1351 /* hurrah the memory is not visible ! */ 1352 atomic64_inc(&adev->num_vram_cpu_page_faults); 1353 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1354 AMDGPU_GEM_DOMAIN_GTT); 1355 1356 /* Avoid costly evictions; only set GTT as a busy placement */ 1357 abo->placement.num_busy_placement = 1; 1358 abo->placement.busy_placement = &abo->placements[1]; 1359 1360 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1361 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1362 return VM_FAULT_NOPAGE; 1363 else if (unlikely(r)) 1364 return VM_FAULT_SIGBUS; 1365 1366 offset = bo->mem.start << PAGE_SHIFT; 1367 /* this should never happen */ 1368 if (bo->mem.mem_type == TTM_PL_VRAM && 1369 (offset + size) > adev->gmc.visible_vram_size) 1370 return VM_FAULT_SIGBUS; 1371 1372 ttm_bo_move_to_lru_tail_unlocked(bo); 1373 return 0; 1374 } 1375 1376 /** 1377 * amdgpu_bo_fence - add fence to buffer object 1378 * 1379 * @bo: buffer object in question 1380 * @fence: fence to add 1381 * @shared: true if fence should be added shared 1382 * 1383 */ 1384 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1385 bool shared) 1386 { 1387 struct dma_resv *resv = bo->tbo.base.resv; 1388 1389 if (shared) 1390 dma_resv_add_shared_fence(resv, fence); 1391 else 1392 dma_resv_add_excl_fence(resv, fence); 1393 } 1394 1395 /** 1396 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1397 * 1398 * @adev: amdgpu device pointer 1399 * @resv: reservation object to sync to 1400 * @sync_mode: synchronization mode 1401 * @owner: fence owner 1402 * @intr: Whether the wait is interruptible 1403 * 1404 * Extract the fences from the reservation object and waits for them to finish. 1405 * 1406 * Returns: 1407 * 0 on success, errno otherwise. 1408 */ 1409 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1410 enum amdgpu_sync_mode sync_mode, void *owner, 1411 bool intr) 1412 { 1413 struct amdgpu_sync sync; 1414 int r; 1415 1416 amdgpu_sync_create(&sync); 1417 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1418 r = amdgpu_sync_wait(&sync, intr); 1419 amdgpu_sync_free(&sync); 1420 return r; 1421 } 1422 1423 /** 1424 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1425 * @bo: buffer object to wait for 1426 * @owner: fence owner 1427 * @intr: Whether the wait is interruptible 1428 * 1429 * Wrapper to wait for fences in a BO. 1430 * Returns: 1431 * 0 on success, errno otherwise. 1432 */ 1433 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1434 { 1435 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1436 1437 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1438 AMDGPU_SYNC_NE_OWNER, owner, intr); 1439 } 1440 1441 /** 1442 * amdgpu_bo_gpu_offset - return GPU offset of bo 1443 * @bo: amdgpu object for which we query the offset 1444 * 1445 * Note: object should either be pinned or reserved when calling this 1446 * function, it might be useful to add check for this for debugging. 1447 * 1448 * Returns: 1449 * current GPU offset of the object. 1450 */ 1451 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1452 { 1453 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1454 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1455 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1456 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1457 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1458 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1459 1460 return amdgpu_bo_gpu_offset_no_check(bo); 1461 } 1462 1463 /** 1464 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1465 * @bo: amdgpu object for which we query the offset 1466 * 1467 * Returns: 1468 * current GPU offset of the object without raising warnings. 1469 */ 1470 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1471 { 1472 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1473 uint64_t offset; 1474 1475 offset = (bo->tbo.mem.start << PAGE_SHIFT) + 1476 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 1477 1478 return amdgpu_gmc_sign_extend(offset); 1479 } 1480 1481 /** 1482 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1483 * @adev: amdgpu device object 1484 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1485 * 1486 * Returns: 1487 * Which of the allowed domains is preferred for pinning the BO for scanout. 1488 */ 1489 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1490 uint32_t domain) 1491 { 1492 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1493 domain = AMDGPU_GEM_DOMAIN_VRAM; 1494 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1495 domain = AMDGPU_GEM_DOMAIN_GTT; 1496 } 1497 return domain; 1498 } 1499 1500 #if defined(CONFIG_DEBUG_FS) 1501 #define amdgpu_bo_print_flag(m, bo, flag) \ 1502 do { \ 1503 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1504 seq_printf((m), " " #flag); \ 1505 } \ 1506 } while (0) 1507 1508 /** 1509 * amdgpu_bo_print_info - print BO info in debugfs file 1510 * 1511 * @id: Index or Id of the BO 1512 * @bo: Requested BO for printing info 1513 * @m: debugfs file 1514 * 1515 * Print BO information in debugfs file 1516 * 1517 * Returns: 1518 * Size of the BO in bytes. 1519 */ 1520 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1521 { 1522 struct dma_buf_attachment *attachment; 1523 struct dma_buf *dma_buf; 1524 unsigned int domain; 1525 const char *placement; 1526 unsigned int pin_count; 1527 u64 size; 1528 1529 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 1530 switch (domain) { 1531 case AMDGPU_GEM_DOMAIN_VRAM: 1532 placement = "VRAM"; 1533 break; 1534 case AMDGPU_GEM_DOMAIN_GTT: 1535 placement = " GTT"; 1536 break; 1537 case AMDGPU_GEM_DOMAIN_CPU: 1538 default: 1539 placement = " CPU"; 1540 break; 1541 } 1542 1543 size = amdgpu_bo_size(bo); 1544 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1545 id, size, placement); 1546 1547 pin_count = READ_ONCE(bo->tbo.pin_count); 1548 if (pin_count) 1549 seq_printf(m, " pin count %d", pin_count); 1550 1551 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1552 attachment = READ_ONCE(bo->tbo.base.import_attach); 1553 1554 if (attachment) 1555 seq_printf(m, " imported from %p", dma_buf); 1556 else if (dma_buf) 1557 seq_printf(m, " exported as %p", dma_buf); 1558 1559 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1560 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1561 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1562 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1563 amdgpu_bo_print_flag(m, bo, SHADOW); 1564 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1565 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1566 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1567 1568 seq_puts(m, "\n"); 1569 1570 return size; 1571 } 1572 #endif 1573