1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 59 60 amdgpu_bo_kunmap(bo); 61 62 if (bo->tbo.base.import_attach) 63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 64 drm_gem_object_release(&bo->tbo.base); 65 amdgpu_bo_unref(&bo->parent); 66 kvfree(bo); 67 } 68 69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 70 { 71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 72 struct amdgpu_bo_user *ubo; 73 74 ubo = to_amdgpu_bo_user(bo); 75 kfree(ubo->metadata); 76 amdgpu_bo_destroy(tbo); 77 } 78 79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 82 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 83 struct amdgpu_bo_vm *vmbo; 84 85 vmbo = to_amdgpu_bo_vm(bo); 86 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 87 if (!list_empty(&vmbo->shadow_list)) { 88 mutex_lock(&adev->shadow_list_lock); 89 list_del_init(&vmbo->shadow_list); 90 mutex_unlock(&adev->shadow_list_lock); 91 } 92 93 amdgpu_bo_destroy(tbo); 94 } 95 96 /** 97 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 98 * @bo: buffer object to be checked 99 * 100 * Uses destroy function associated with the object to determine if this is 101 * an &amdgpu_bo. 102 * 103 * Returns: 104 * true if the object belongs to &amdgpu_bo, false if not. 105 */ 106 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 107 { 108 if (bo->destroy == &amdgpu_bo_destroy || 109 bo->destroy == &amdgpu_bo_user_destroy || 110 bo->destroy == &amdgpu_bo_vm_destroy) 111 return true; 112 113 return false; 114 } 115 116 /** 117 * amdgpu_bo_placement_from_domain - set buffer's placement 118 * @abo: &amdgpu_bo buffer object whose placement is to be set 119 * @domain: requested domain 120 * 121 * Sets buffer's placement according to requested domain and the buffer's 122 * flags. 123 */ 124 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 125 { 126 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 127 struct ttm_placement *placement = &abo->placement; 128 struct ttm_place *places = abo->placements; 129 u64 flags = abo->flags; 130 u32 c = 0; 131 132 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 133 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 134 135 places[c].fpfn = 0; 136 places[c].lpfn = 0; 137 places[c].mem_type = TTM_PL_VRAM; 138 places[c].flags = 0; 139 140 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 141 places[c].lpfn = visible_pfn; 142 else 143 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 144 145 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 146 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 147 c++; 148 } 149 150 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 151 places[c].fpfn = 0; 152 places[c].lpfn = 0; 153 places[c].mem_type = 154 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 155 AMDGPU_PL_PREEMPT : TTM_PL_TT; 156 places[c].flags = 0; 157 c++; 158 } 159 160 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 161 places[c].fpfn = 0; 162 places[c].lpfn = 0; 163 places[c].mem_type = TTM_PL_SYSTEM; 164 places[c].flags = 0; 165 c++; 166 } 167 168 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 169 places[c].fpfn = 0; 170 places[c].lpfn = 0; 171 places[c].mem_type = AMDGPU_PL_GDS; 172 places[c].flags = 0; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].mem_type = AMDGPU_PL_GWS; 180 places[c].flags = 0; 181 c++; 182 } 183 184 if (domain & AMDGPU_GEM_DOMAIN_OA) { 185 places[c].fpfn = 0; 186 places[c].lpfn = 0; 187 places[c].mem_type = AMDGPU_PL_OA; 188 places[c].flags = 0; 189 c++; 190 } 191 192 if (!c) { 193 places[c].fpfn = 0; 194 places[c].lpfn = 0; 195 places[c].mem_type = TTM_PL_SYSTEM; 196 places[c].flags = 0; 197 c++; 198 } 199 200 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 201 202 placement->num_placement = c; 203 placement->placement = places; 204 205 placement->num_busy_placement = c; 206 placement->busy_placement = places; 207 } 208 209 /** 210 * amdgpu_bo_create_reserved - create reserved BO for kernel use 211 * 212 * @adev: amdgpu device object 213 * @size: size for the new BO 214 * @align: alignment for the new BO 215 * @domain: where to place it 216 * @bo_ptr: used to initialize BOs in structures 217 * @gpu_addr: GPU addr of the pinned BO 218 * @cpu_addr: optional CPU address mapping 219 * 220 * Allocates and pins a BO for kernel internal use, and returns it still 221 * reserved. 222 * 223 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 224 * 225 * Returns: 226 * 0 on success, negative error code otherwise. 227 */ 228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 229 unsigned long size, int align, 230 u32 domain, struct amdgpu_bo **bo_ptr, 231 u64 *gpu_addr, void **cpu_addr) 232 { 233 struct amdgpu_bo_param bp; 234 bool free = false; 235 int r; 236 237 if (!size) { 238 amdgpu_bo_unref(bo_ptr); 239 return 0; 240 } 241 242 memset(&bp, 0, sizeof(bp)); 243 bp.size = size; 244 bp.byte_align = align; 245 bp.domain = domain; 246 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 247 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 248 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 249 bp.type = ttm_bo_type_kernel; 250 bp.resv = NULL; 251 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 252 253 if (!*bo_ptr) { 254 r = amdgpu_bo_create(adev, &bp, bo_ptr); 255 if (r) { 256 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 257 r); 258 return r; 259 } 260 free = true; 261 } 262 263 r = amdgpu_bo_reserve(*bo_ptr, false); 264 if (r) { 265 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 266 goto error_free; 267 } 268 269 r = amdgpu_bo_pin(*bo_ptr, domain); 270 if (r) { 271 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 272 goto error_unreserve; 273 } 274 275 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 276 if (r) { 277 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 278 goto error_unpin; 279 } 280 281 if (gpu_addr) 282 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 283 284 if (cpu_addr) { 285 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 286 if (r) { 287 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 288 goto error_unpin; 289 } 290 } 291 292 return 0; 293 294 error_unpin: 295 amdgpu_bo_unpin(*bo_ptr); 296 error_unreserve: 297 amdgpu_bo_unreserve(*bo_ptr); 298 299 error_free: 300 if (free) 301 amdgpu_bo_unref(bo_ptr); 302 303 return r; 304 } 305 306 /** 307 * amdgpu_bo_create_kernel - create BO for kernel use 308 * 309 * @adev: amdgpu device object 310 * @size: size for the new BO 311 * @align: alignment for the new BO 312 * @domain: where to place it 313 * @bo_ptr: used to initialize BOs in structures 314 * @gpu_addr: GPU addr of the pinned BO 315 * @cpu_addr: optional CPU address mapping 316 * 317 * Allocates and pins a BO for kernel internal use. 318 * 319 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 320 * 321 * Returns: 322 * 0 on success, negative error code otherwise. 323 */ 324 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 325 unsigned long size, int align, 326 u32 domain, struct amdgpu_bo **bo_ptr, 327 u64 *gpu_addr, void **cpu_addr) 328 { 329 int r; 330 331 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 332 gpu_addr, cpu_addr); 333 334 if (r) 335 return r; 336 337 if (*bo_ptr) 338 amdgpu_bo_unreserve(*bo_ptr); 339 340 return 0; 341 } 342 343 /** 344 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 345 * 346 * @adev: amdgpu device object 347 * @offset: offset of the BO 348 * @size: size of the BO 349 * @domain: where to place it 350 * @bo_ptr: used to initialize BOs in structures 351 * @cpu_addr: optional CPU address mapping 352 * 353 * Creates a kernel BO at a specific offset in the address space of the domain. 354 * 355 * Returns: 356 * 0 on success, negative error code otherwise. 357 */ 358 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 359 uint64_t offset, uint64_t size, uint32_t domain, 360 struct amdgpu_bo **bo_ptr, void **cpu_addr) 361 { 362 struct ttm_operation_ctx ctx = { false, false }; 363 unsigned int i; 364 int r; 365 366 offset &= PAGE_MASK; 367 size = ALIGN(size, PAGE_SIZE); 368 369 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 370 NULL, cpu_addr); 371 if (r) 372 return r; 373 374 if ((*bo_ptr) == NULL) 375 return 0; 376 377 /* 378 * Remove the original mem node and create a new one at the request 379 * position. 380 */ 381 if (cpu_addr) 382 amdgpu_bo_kunmap(*bo_ptr); 383 384 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 385 386 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 387 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 388 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 389 } 390 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 391 &(*bo_ptr)->tbo.resource, &ctx); 392 if (r) 393 goto error; 394 395 if (cpu_addr) { 396 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 397 if (r) 398 goto error; 399 } 400 401 amdgpu_bo_unreserve(*bo_ptr); 402 return 0; 403 404 error: 405 amdgpu_bo_unreserve(*bo_ptr); 406 amdgpu_bo_unref(bo_ptr); 407 return r; 408 } 409 410 /** 411 * amdgpu_bo_free_kernel - free BO for kernel use 412 * 413 * @bo: amdgpu BO to free 414 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 415 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 416 * 417 * unmaps and unpin a BO for kernel internal use. 418 */ 419 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 420 void **cpu_addr) 421 { 422 if (*bo == NULL) 423 return; 424 425 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 426 if (cpu_addr) 427 amdgpu_bo_kunmap(*bo); 428 429 amdgpu_bo_unpin(*bo); 430 amdgpu_bo_unreserve(*bo); 431 } 432 amdgpu_bo_unref(bo); 433 434 if (gpu_addr) 435 *gpu_addr = 0; 436 437 if (cpu_addr) 438 *cpu_addr = NULL; 439 } 440 441 /* Validate bo size is bit bigger then the request domain */ 442 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 443 unsigned long size, u32 domain) 444 { 445 struct ttm_resource_manager *man = NULL; 446 447 /* 448 * If GTT is part of requested domains the check must succeed to 449 * allow fall back to GTT 450 */ 451 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 452 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 453 454 if (size < man->size) 455 return true; 456 else 457 goto fail; 458 } 459 460 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 461 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 462 463 if (size < man->size) 464 return true; 465 else 466 goto fail; 467 } 468 469 470 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 471 return true; 472 473 fail: 474 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 475 man->size << PAGE_SHIFT); 476 return false; 477 } 478 479 bool amdgpu_bo_support_uswc(u64 bo_flags) 480 { 481 482 #ifdef CONFIG_X86_32 483 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 484 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 485 */ 486 return false; 487 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 488 /* Don't try to enable write-combining when it can't work, or things 489 * may be slow 490 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 491 */ 492 493 #ifndef CONFIG_COMPILE_TEST 494 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 495 thanks to write-combining 496 #endif 497 498 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 499 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 500 "better performance thanks to write-combining\n"); 501 return false; 502 #else 503 /* For architectures that don't support WC memory, 504 * mask out the WC flag from the BO 505 */ 506 if (!drm_arch_can_wc_memory()) 507 return false; 508 509 return true; 510 #endif 511 } 512 513 /** 514 * amdgpu_bo_create - create an &amdgpu_bo buffer object 515 * @adev: amdgpu device object 516 * @bp: parameters to be used for the buffer object 517 * @bo_ptr: pointer to the buffer object pointer 518 * 519 * Creates an &amdgpu_bo buffer object. 520 * 521 * Returns: 522 * 0 for success or a negative error code on failure. 523 */ 524 int amdgpu_bo_create(struct amdgpu_device *adev, 525 struct amdgpu_bo_param *bp, 526 struct amdgpu_bo **bo_ptr) 527 { 528 struct ttm_operation_ctx ctx = { 529 .interruptible = (bp->type != ttm_bo_type_kernel), 530 .no_wait_gpu = bp->no_wait_gpu, 531 /* We opt to avoid OOM on system pages allocations */ 532 .gfp_retry_mayfail = true, 533 .allow_res_evict = bp->type != ttm_bo_type_kernel, 534 .resv = bp->resv 535 }; 536 struct amdgpu_bo *bo; 537 unsigned long page_align, size = bp->size; 538 int r; 539 540 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 541 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 542 /* GWS and OA don't need any alignment. */ 543 page_align = bp->byte_align; 544 size <<= PAGE_SHIFT; 545 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 546 /* Both size and alignment must be a multiple of 4. */ 547 page_align = ALIGN(bp->byte_align, 4); 548 size = ALIGN(size, 4) << PAGE_SHIFT; 549 } else { 550 /* Memory should be aligned at least to a page size. */ 551 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 552 size = ALIGN(size, PAGE_SIZE); 553 } 554 555 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 556 return -ENOMEM; 557 558 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 559 560 *bo_ptr = NULL; 561 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 562 if (bo == NULL) 563 return -ENOMEM; 564 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 565 bo->vm_bo = NULL; 566 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 567 bp->domain; 568 bo->allowed_domains = bo->preferred_domains; 569 if (bp->type != ttm_bo_type_kernel && 570 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 571 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 572 573 bo->flags = bp->flags; 574 575 if (!amdgpu_bo_support_uswc(bo->flags)) 576 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 577 578 if (adev->ras_enabled) 579 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 580 581 bo->tbo.bdev = &adev->mman.bdev; 582 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 583 AMDGPU_GEM_DOMAIN_GDS)) 584 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 585 else 586 amdgpu_bo_placement_from_domain(bo, bp->domain); 587 if (bp->type == ttm_bo_type_kernel) 588 bo->tbo.priority = 1; 589 590 if (!bp->destroy) 591 bp->destroy = &amdgpu_bo_destroy; 592 593 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 594 &bo->placement, page_align, &ctx, NULL, 595 bp->resv, bp->destroy); 596 if (unlikely(r != 0)) 597 return r; 598 599 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 600 bo->tbo.resource->mem_type == TTM_PL_VRAM && 601 bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 602 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 603 ctx.bytes_moved); 604 else 605 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 606 607 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 608 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 609 struct dma_fence *fence; 610 611 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 612 if (unlikely(r)) 613 goto fail_unreserve; 614 615 dma_resv_add_fence(bo->tbo.base.resv, fence, 616 DMA_RESV_USAGE_KERNEL); 617 dma_fence_put(fence); 618 } 619 if (!bp->resv) 620 amdgpu_bo_unreserve(bo); 621 *bo_ptr = bo; 622 623 trace_amdgpu_bo_create(bo); 624 625 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 626 if (bp->type == ttm_bo_type_device) 627 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 628 629 return 0; 630 631 fail_unreserve: 632 if (!bp->resv) 633 dma_resv_unlock(bo->tbo.base.resv); 634 amdgpu_bo_unref(&bo); 635 return r; 636 } 637 638 /** 639 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 640 * @adev: amdgpu device object 641 * @bp: parameters to be used for the buffer object 642 * @ubo_ptr: pointer to the buffer object pointer 643 * 644 * Create a BO to be used by user application; 645 * 646 * Returns: 647 * 0 for success or a negative error code on failure. 648 */ 649 650 int amdgpu_bo_create_user(struct amdgpu_device *adev, 651 struct amdgpu_bo_param *bp, 652 struct amdgpu_bo_user **ubo_ptr) 653 { 654 struct amdgpu_bo *bo_ptr; 655 int r; 656 657 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 658 bp->destroy = &amdgpu_bo_user_destroy; 659 r = amdgpu_bo_create(adev, bp, &bo_ptr); 660 if (r) 661 return r; 662 663 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 664 return r; 665 } 666 667 /** 668 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 669 * @adev: amdgpu device object 670 * @bp: parameters to be used for the buffer object 671 * @vmbo_ptr: pointer to the buffer object pointer 672 * 673 * Create a BO to be for GPUVM. 674 * 675 * Returns: 676 * 0 for success or a negative error code on failure. 677 */ 678 679 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 680 struct amdgpu_bo_param *bp, 681 struct amdgpu_bo_vm **vmbo_ptr) 682 { 683 struct amdgpu_bo *bo_ptr; 684 int r; 685 686 /* bo_ptr_size will be determined by the caller and it depends on 687 * num of amdgpu_vm_pt entries. 688 */ 689 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 690 bp->destroy = &amdgpu_bo_vm_destroy; 691 r = amdgpu_bo_create(adev, bp, &bo_ptr); 692 if (r) 693 return r; 694 695 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 696 INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list); 697 return r; 698 } 699 700 /** 701 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 702 * 703 * @vmbo: BO that will be inserted into the shadow list 704 * 705 * Insert a BO to the shadow list. 706 */ 707 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 708 { 709 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 710 711 mutex_lock(&adev->shadow_list_lock); 712 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 713 mutex_unlock(&adev->shadow_list_lock); 714 } 715 716 /** 717 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 718 * 719 * @shadow: &amdgpu_bo shadow to be restored 720 * @fence: dma_fence associated with the operation 721 * 722 * Copies a buffer object's shadow content back to the object. 723 * This is used for recovering a buffer from its shadow in case of a gpu 724 * reset where vram context may be lost. 725 * 726 * Returns: 727 * 0 for success or a negative error code on failure. 728 */ 729 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 730 731 { 732 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 733 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 734 uint64_t shadow_addr, parent_addr; 735 736 shadow_addr = amdgpu_bo_gpu_offset(shadow); 737 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 738 739 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 740 amdgpu_bo_size(shadow), NULL, fence, 741 true, false, false); 742 } 743 744 /** 745 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 746 * @bo: &amdgpu_bo buffer object to be mapped 747 * @ptr: kernel virtual address to be returned 748 * 749 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 750 * amdgpu_bo_kptr() to get the kernel virtual address. 751 * 752 * Returns: 753 * 0 for success or a negative error code on failure. 754 */ 755 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 756 { 757 void *kptr; 758 long r; 759 760 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 761 return -EPERM; 762 763 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 764 false, MAX_SCHEDULE_TIMEOUT); 765 if (r < 0) 766 return r; 767 768 kptr = amdgpu_bo_kptr(bo); 769 if (kptr) { 770 if (ptr) 771 *ptr = kptr; 772 return 0; 773 } 774 775 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap); 776 if (r) 777 return r; 778 779 if (ptr) 780 *ptr = amdgpu_bo_kptr(bo); 781 782 return 0; 783 } 784 785 /** 786 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 787 * @bo: &amdgpu_bo buffer object 788 * 789 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 790 * 791 * Returns: 792 * the virtual address of a buffer object area. 793 */ 794 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 795 { 796 bool is_iomem; 797 798 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 799 } 800 801 /** 802 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 803 * @bo: &amdgpu_bo buffer object to be unmapped 804 * 805 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 806 */ 807 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 808 { 809 if (bo->kmap.bo) 810 ttm_bo_kunmap(&bo->kmap); 811 } 812 813 /** 814 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 815 * @bo: &amdgpu_bo buffer object 816 * 817 * References the contained &ttm_buffer_object. 818 * 819 * Returns: 820 * a refcounted pointer to the &amdgpu_bo buffer object. 821 */ 822 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 823 { 824 if (bo == NULL) 825 return NULL; 826 827 ttm_bo_get(&bo->tbo); 828 return bo; 829 } 830 831 /** 832 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 833 * @bo: &amdgpu_bo buffer object 834 * 835 * Unreferences the contained &ttm_buffer_object and clear the pointer 836 */ 837 void amdgpu_bo_unref(struct amdgpu_bo **bo) 838 { 839 struct ttm_buffer_object *tbo; 840 841 if ((*bo) == NULL) 842 return; 843 844 tbo = &((*bo)->tbo); 845 ttm_bo_put(tbo); 846 *bo = NULL; 847 } 848 849 /** 850 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 851 * @bo: &amdgpu_bo buffer object to be pinned 852 * @domain: domain to be pinned to 853 * @min_offset: the start of requested address range 854 * @max_offset: the end of requested address range 855 * 856 * Pins the buffer object according to requested domain and address range. If 857 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 858 * pin_count and pin_size accordingly. 859 * 860 * Pinning means to lock pages in memory along with keeping them at a fixed 861 * offset. It is required when a buffer can not be moved, for example, when 862 * a display buffer is being scanned out. 863 * 864 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 865 * where to pin a buffer if there are specific restrictions on where a buffer 866 * must be located. 867 * 868 * Returns: 869 * 0 for success or a negative error code on failure. 870 */ 871 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 872 u64 min_offset, u64 max_offset) 873 { 874 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 875 struct ttm_operation_ctx ctx = { false, false }; 876 int r, i; 877 878 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 879 return -EPERM; 880 881 if (WARN_ON_ONCE(min_offset > max_offset)) 882 return -EINVAL; 883 884 /* A shared bo cannot be migrated to VRAM */ 885 if (bo->tbo.base.import_attach) { 886 if (domain & AMDGPU_GEM_DOMAIN_GTT) 887 domain = AMDGPU_GEM_DOMAIN_GTT; 888 else 889 return -EINVAL; 890 } 891 892 if (bo->tbo.pin_count) { 893 uint32_t mem_type = bo->tbo.resource->mem_type; 894 uint32_t mem_flags = bo->tbo.resource->placement; 895 896 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 897 return -EINVAL; 898 899 if ((mem_type == TTM_PL_VRAM) && 900 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 901 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 902 return -EINVAL; 903 904 ttm_bo_pin(&bo->tbo); 905 906 if (max_offset != 0) { 907 u64 domain_start = amdgpu_ttm_domain_start(adev, 908 mem_type); 909 WARN_ON_ONCE(max_offset < 910 (amdgpu_bo_gpu_offset(bo) - domain_start)); 911 } 912 913 return 0; 914 } 915 916 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 917 * See function amdgpu_display_supported_domains() 918 */ 919 domain = amdgpu_bo_get_preferred_domain(adev, domain); 920 921 if (bo->tbo.base.import_attach) 922 dma_buf_pin(bo->tbo.base.import_attach); 923 924 /* force to pin into visible video ram */ 925 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 926 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 927 amdgpu_bo_placement_from_domain(bo, domain); 928 for (i = 0; i < bo->placement.num_placement; i++) { 929 unsigned fpfn, lpfn; 930 931 fpfn = min_offset >> PAGE_SHIFT; 932 lpfn = max_offset >> PAGE_SHIFT; 933 934 if (fpfn > bo->placements[i].fpfn) 935 bo->placements[i].fpfn = fpfn; 936 if (!bo->placements[i].lpfn || 937 (lpfn && lpfn < bo->placements[i].lpfn)) 938 bo->placements[i].lpfn = lpfn; 939 } 940 941 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 942 if (unlikely(r)) { 943 dev_err(adev->dev, "%p pin failed\n", bo); 944 goto error; 945 } 946 947 ttm_bo_pin(&bo->tbo); 948 949 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 950 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 951 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 952 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 953 &adev->visible_pin_size); 954 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 955 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 956 } 957 958 error: 959 return r; 960 } 961 962 /** 963 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 964 * @bo: &amdgpu_bo buffer object to be pinned 965 * @domain: domain to be pinned to 966 * 967 * A simple wrapper to amdgpu_bo_pin_restricted(). 968 * Provides a simpler API for buffers that do not have any strict restrictions 969 * on where a buffer must be located. 970 * 971 * Returns: 972 * 0 for success or a negative error code on failure. 973 */ 974 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 975 { 976 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 977 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 978 } 979 980 /** 981 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 982 * @bo: &amdgpu_bo buffer object to be unpinned 983 * 984 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 985 * Changes placement and pin size accordingly. 986 * 987 * Returns: 988 * 0 for success or a negative error code on failure. 989 */ 990 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 991 { 992 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 993 994 ttm_bo_unpin(&bo->tbo); 995 if (bo->tbo.pin_count) 996 return; 997 998 if (bo->tbo.base.import_attach) 999 dma_buf_unpin(bo->tbo.base.import_attach); 1000 1001 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1002 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1003 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1004 &adev->visible_pin_size); 1005 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1006 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1007 } 1008 } 1009 1010 static const char *amdgpu_vram_names[] = { 1011 "UNKNOWN", 1012 "GDDR1", 1013 "DDR2", 1014 "GDDR3", 1015 "GDDR4", 1016 "GDDR5", 1017 "HBM", 1018 "DDR3", 1019 "DDR4", 1020 "GDDR6", 1021 "DDR5" 1022 }; 1023 1024 /** 1025 * amdgpu_bo_init - initialize memory manager 1026 * @adev: amdgpu device object 1027 * 1028 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1029 * 1030 * Returns: 1031 * 0 for success or a negative error code on failure. 1032 */ 1033 int amdgpu_bo_init(struct amdgpu_device *adev) 1034 { 1035 /* On A+A platform, VRAM can be mapped as WB */ 1036 if (!adev->gmc.xgmi.connected_to_cpu) { 1037 /* reserve PAT memory space to WC for VRAM */ 1038 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1039 adev->gmc.aper_size); 1040 1041 if (r) { 1042 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1043 return r; 1044 } 1045 1046 /* Add an MTRR for the VRAM */ 1047 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1048 adev->gmc.aper_size); 1049 } 1050 1051 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1052 adev->gmc.mc_vram_size >> 20, 1053 (unsigned long long)adev->gmc.aper_size >> 20); 1054 DRM_INFO("RAM width %dbits %s\n", 1055 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1056 return amdgpu_ttm_init(adev); 1057 } 1058 1059 /** 1060 * amdgpu_bo_fini - tear down memory manager 1061 * @adev: amdgpu device object 1062 * 1063 * Reverses amdgpu_bo_init() to tear down memory manager. 1064 */ 1065 void amdgpu_bo_fini(struct amdgpu_device *adev) 1066 { 1067 int idx; 1068 1069 amdgpu_ttm_fini(adev); 1070 1071 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1072 1073 if (!adev->gmc.xgmi.connected_to_cpu) { 1074 arch_phys_wc_del(adev->gmc.vram_mtrr); 1075 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1076 } 1077 drm_dev_exit(idx); 1078 } 1079 } 1080 1081 /** 1082 * amdgpu_bo_set_tiling_flags - set tiling flags 1083 * @bo: &amdgpu_bo buffer object 1084 * @tiling_flags: new flags 1085 * 1086 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1087 * kernel driver to set the tiling flags on a buffer. 1088 * 1089 * Returns: 1090 * 0 for success or a negative error code on failure. 1091 */ 1092 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1093 { 1094 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1095 struct amdgpu_bo_user *ubo; 1096 1097 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1098 if (adev->family <= AMDGPU_FAMILY_CZ && 1099 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1100 return -EINVAL; 1101 1102 ubo = to_amdgpu_bo_user(bo); 1103 ubo->tiling_flags = tiling_flags; 1104 return 0; 1105 } 1106 1107 /** 1108 * amdgpu_bo_get_tiling_flags - get tiling flags 1109 * @bo: &amdgpu_bo buffer object 1110 * @tiling_flags: returned flags 1111 * 1112 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1113 * set the tiling flags on a buffer. 1114 */ 1115 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1116 { 1117 struct amdgpu_bo_user *ubo; 1118 1119 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1120 dma_resv_assert_held(bo->tbo.base.resv); 1121 ubo = to_amdgpu_bo_user(bo); 1122 1123 if (tiling_flags) 1124 *tiling_flags = ubo->tiling_flags; 1125 } 1126 1127 /** 1128 * amdgpu_bo_set_metadata - set metadata 1129 * @bo: &amdgpu_bo buffer object 1130 * @metadata: new metadata 1131 * @metadata_size: size of the new metadata 1132 * @flags: flags of the new metadata 1133 * 1134 * Sets buffer object's metadata, its size and flags. 1135 * Used via GEM ioctl. 1136 * 1137 * Returns: 1138 * 0 for success or a negative error code on failure. 1139 */ 1140 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1141 uint32_t metadata_size, uint64_t flags) 1142 { 1143 struct amdgpu_bo_user *ubo; 1144 void *buffer; 1145 1146 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1147 ubo = to_amdgpu_bo_user(bo); 1148 if (!metadata_size) { 1149 if (ubo->metadata_size) { 1150 kfree(ubo->metadata); 1151 ubo->metadata = NULL; 1152 ubo->metadata_size = 0; 1153 } 1154 return 0; 1155 } 1156 1157 if (metadata == NULL) 1158 return -EINVAL; 1159 1160 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1161 if (buffer == NULL) 1162 return -ENOMEM; 1163 1164 kfree(ubo->metadata); 1165 ubo->metadata_flags = flags; 1166 ubo->metadata = buffer; 1167 ubo->metadata_size = metadata_size; 1168 1169 return 0; 1170 } 1171 1172 /** 1173 * amdgpu_bo_get_metadata - get metadata 1174 * @bo: &amdgpu_bo buffer object 1175 * @buffer: returned metadata 1176 * @buffer_size: size of the buffer 1177 * @metadata_size: size of the returned metadata 1178 * @flags: flags of the returned metadata 1179 * 1180 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1181 * less than metadata_size. 1182 * Used via GEM ioctl. 1183 * 1184 * Returns: 1185 * 0 for success or a negative error code on failure. 1186 */ 1187 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1188 size_t buffer_size, uint32_t *metadata_size, 1189 uint64_t *flags) 1190 { 1191 struct amdgpu_bo_user *ubo; 1192 1193 if (!buffer && !metadata_size) 1194 return -EINVAL; 1195 1196 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1197 ubo = to_amdgpu_bo_user(bo); 1198 if (metadata_size) 1199 *metadata_size = ubo->metadata_size; 1200 1201 if (buffer) { 1202 if (buffer_size < ubo->metadata_size) 1203 return -EINVAL; 1204 1205 if (ubo->metadata_size) 1206 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1207 } 1208 1209 if (flags) 1210 *flags = ubo->metadata_flags; 1211 1212 return 0; 1213 } 1214 1215 /** 1216 * amdgpu_bo_move_notify - notification about a memory move 1217 * @bo: pointer to a buffer object 1218 * @evict: if this move is evicting the buffer from the graphics address space 1219 * @new_mem: new information of the bufer object 1220 * 1221 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1222 * bookkeeping. 1223 * TTM driver callback which is called when ttm moves a buffer. 1224 */ 1225 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1226 bool evict, 1227 struct ttm_resource *new_mem) 1228 { 1229 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1230 struct amdgpu_bo *abo; 1231 struct ttm_resource *old_mem = bo->resource; 1232 1233 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1234 return; 1235 1236 abo = ttm_to_amdgpu_bo(bo); 1237 amdgpu_vm_bo_invalidate(adev, abo, evict); 1238 1239 amdgpu_bo_kunmap(abo); 1240 1241 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1242 bo->resource->mem_type != TTM_PL_SYSTEM) 1243 dma_buf_move_notify(abo->tbo.base.dma_buf); 1244 1245 /* remember the eviction */ 1246 if (evict) 1247 atomic64_inc(&adev->num_evictions); 1248 1249 /* update statistics */ 1250 if (!new_mem) 1251 return; 1252 1253 /* move_notify is called before move happens */ 1254 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1255 } 1256 1257 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, 1258 uint64_t *gtt_mem, uint64_t *cpu_mem) 1259 { 1260 unsigned int domain; 1261 1262 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1263 switch (domain) { 1264 case AMDGPU_GEM_DOMAIN_VRAM: 1265 *vram_mem += amdgpu_bo_size(bo); 1266 break; 1267 case AMDGPU_GEM_DOMAIN_GTT: 1268 *gtt_mem += amdgpu_bo_size(bo); 1269 break; 1270 case AMDGPU_GEM_DOMAIN_CPU: 1271 default: 1272 *cpu_mem += amdgpu_bo_size(bo); 1273 break; 1274 } 1275 } 1276 1277 /** 1278 * amdgpu_bo_release_notify - notification about a BO being released 1279 * @bo: pointer to a buffer object 1280 * 1281 * Wipes VRAM buffers whose contents should not be leaked before the 1282 * memory is released. 1283 */ 1284 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1285 { 1286 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1287 struct dma_fence *fence = NULL; 1288 struct amdgpu_bo *abo; 1289 int r; 1290 1291 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1292 return; 1293 1294 abo = ttm_to_amdgpu_bo(bo); 1295 1296 if (abo->kfd_bo) 1297 amdgpu_amdkfd_release_notify(abo); 1298 1299 /* We only remove the fence if the resv has individualized. */ 1300 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1301 && bo->base.resv != &bo->base._resv); 1302 if (bo->base.resv == &bo->base._resv) 1303 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1304 1305 if (bo->resource->mem_type != TTM_PL_VRAM || 1306 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1307 adev->in_suspend || adev->shutdown) 1308 return; 1309 1310 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1311 return; 1312 1313 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1314 if (!WARN_ON(r)) { 1315 amdgpu_bo_fence(abo, fence, false); 1316 dma_fence_put(fence); 1317 } 1318 1319 dma_resv_unlock(bo->base.resv); 1320 } 1321 1322 /** 1323 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1324 * @bo: pointer to a buffer object 1325 * 1326 * Notifies the driver we are taking a fault on this BO and have reserved it, 1327 * also performs bookkeeping. 1328 * TTM driver callback for dealing with vm faults. 1329 * 1330 * Returns: 1331 * 0 for success or a negative error code on failure. 1332 */ 1333 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1334 { 1335 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1336 struct ttm_operation_ctx ctx = { false, false }; 1337 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1338 unsigned long offset; 1339 int r; 1340 1341 /* Remember that this BO was accessed by the CPU */ 1342 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1343 1344 if (bo->resource->mem_type != TTM_PL_VRAM) 1345 return 0; 1346 1347 offset = bo->resource->start << PAGE_SHIFT; 1348 if ((offset + bo->base.size) <= adev->gmc.visible_vram_size) 1349 return 0; 1350 1351 /* Can't move a pinned BO to visible VRAM */ 1352 if (abo->tbo.pin_count > 0) 1353 return VM_FAULT_SIGBUS; 1354 1355 /* hurrah the memory is not visible ! */ 1356 atomic64_inc(&adev->num_vram_cpu_page_faults); 1357 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1358 AMDGPU_GEM_DOMAIN_GTT); 1359 1360 /* Avoid costly evictions; only set GTT as a busy placement */ 1361 abo->placement.num_busy_placement = 1; 1362 abo->placement.busy_placement = &abo->placements[1]; 1363 1364 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1365 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1366 return VM_FAULT_NOPAGE; 1367 else if (unlikely(r)) 1368 return VM_FAULT_SIGBUS; 1369 1370 offset = bo->resource->start << PAGE_SHIFT; 1371 /* this should never happen */ 1372 if (bo->resource->mem_type == TTM_PL_VRAM && 1373 (offset + bo->base.size) > adev->gmc.visible_vram_size) 1374 return VM_FAULT_SIGBUS; 1375 1376 ttm_bo_move_to_lru_tail_unlocked(bo); 1377 return 0; 1378 } 1379 1380 /** 1381 * amdgpu_bo_fence - add fence to buffer object 1382 * 1383 * @bo: buffer object in question 1384 * @fence: fence to add 1385 * @shared: true if fence should be added shared 1386 * 1387 */ 1388 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1389 bool shared) 1390 { 1391 struct dma_resv *resv = bo->tbo.base.resv; 1392 int r; 1393 1394 r = dma_resv_reserve_fences(resv, 1); 1395 if (r) { 1396 /* As last resort on OOM we block for the fence */ 1397 dma_fence_wait(fence, false); 1398 return; 1399 } 1400 1401 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1402 DMA_RESV_USAGE_WRITE); 1403 } 1404 1405 /** 1406 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1407 * 1408 * @adev: amdgpu device pointer 1409 * @resv: reservation object to sync to 1410 * @sync_mode: synchronization mode 1411 * @owner: fence owner 1412 * @intr: Whether the wait is interruptible 1413 * 1414 * Extract the fences from the reservation object and waits for them to finish. 1415 * 1416 * Returns: 1417 * 0 on success, errno otherwise. 1418 */ 1419 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1420 enum amdgpu_sync_mode sync_mode, void *owner, 1421 bool intr) 1422 { 1423 struct amdgpu_sync sync; 1424 int r; 1425 1426 amdgpu_sync_create(&sync); 1427 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1428 r = amdgpu_sync_wait(&sync, intr); 1429 amdgpu_sync_free(&sync); 1430 return r; 1431 } 1432 1433 /** 1434 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1435 * @bo: buffer object to wait for 1436 * @owner: fence owner 1437 * @intr: Whether the wait is interruptible 1438 * 1439 * Wrapper to wait for fences in a BO. 1440 * Returns: 1441 * 0 on success, errno otherwise. 1442 */ 1443 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1444 { 1445 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1446 1447 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1448 AMDGPU_SYNC_NE_OWNER, owner, intr); 1449 } 1450 1451 /** 1452 * amdgpu_bo_gpu_offset - return GPU offset of bo 1453 * @bo: amdgpu object for which we query the offset 1454 * 1455 * Note: object should either be pinned or reserved when calling this 1456 * function, it might be useful to add check for this for debugging. 1457 * 1458 * Returns: 1459 * current GPU offset of the object. 1460 */ 1461 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1462 { 1463 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1464 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1465 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1466 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1467 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1468 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1469 1470 return amdgpu_bo_gpu_offset_no_check(bo); 1471 } 1472 1473 /** 1474 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1475 * @bo: amdgpu object for which we query the offset 1476 * 1477 * Returns: 1478 * current GPU offset of the object without raising warnings. 1479 */ 1480 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1481 { 1482 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1483 uint64_t offset; 1484 1485 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1486 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1487 1488 return amdgpu_gmc_sign_extend(offset); 1489 } 1490 1491 /** 1492 * amdgpu_bo_get_preferred_domain - get preferred domain 1493 * @adev: amdgpu device object 1494 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1495 * 1496 * Returns: 1497 * Which of the allowed domains is preferred for allocating the BO. 1498 */ 1499 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1500 uint32_t domain) 1501 { 1502 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1503 domain = AMDGPU_GEM_DOMAIN_VRAM; 1504 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1505 domain = AMDGPU_GEM_DOMAIN_GTT; 1506 } 1507 return domain; 1508 } 1509 1510 #if defined(CONFIG_DEBUG_FS) 1511 #define amdgpu_bo_print_flag(m, bo, flag) \ 1512 do { \ 1513 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1514 seq_printf((m), " " #flag); \ 1515 } \ 1516 } while (0) 1517 1518 /** 1519 * amdgpu_bo_print_info - print BO info in debugfs file 1520 * 1521 * @id: Index or Id of the BO 1522 * @bo: Requested BO for printing info 1523 * @m: debugfs file 1524 * 1525 * Print BO information in debugfs file 1526 * 1527 * Returns: 1528 * Size of the BO in bytes. 1529 */ 1530 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1531 { 1532 struct dma_buf_attachment *attachment; 1533 struct dma_buf *dma_buf; 1534 unsigned int domain; 1535 const char *placement; 1536 unsigned int pin_count; 1537 u64 size; 1538 1539 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1540 switch (domain) { 1541 case AMDGPU_GEM_DOMAIN_VRAM: 1542 placement = "VRAM"; 1543 break; 1544 case AMDGPU_GEM_DOMAIN_GTT: 1545 placement = " GTT"; 1546 break; 1547 case AMDGPU_GEM_DOMAIN_CPU: 1548 default: 1549 placement = " CPU"; 1550 break; 1551 } 1552 1553 size = amdgpu_bo_size(bo); 1554 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1555 id, size, placement); 1556 1557 pin_count = READ_ONCE(bo->tbo.pin_count); 1558 if (pin_count) 1559 seq_printf(m, " pin count %d", pin_count); 1560 1561 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1562 attachment = READ_ONCE(bo->tbo.base.import_attach); 1563 1564 if (attachment) 1565 seq_printf(m, " imported from %p", dma_buf); 1566 else if (dma_buf) 1567 seq_printf(m, " exported as %p", dma_buf); 1568 1569 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1570 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1571 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1572 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1573 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1574 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1575 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1576 1577 seq_puts(m, "\n"); 1578 1579 return size; 1580 } 1581 #endif 1582