1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 40 41 42 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, 43 struct ttm_mem_reg *mem) 44 { 45 if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size) 46 return 0; 47 48 return ((mem->start << PAGE_SHIFT) + mem->size) > 49 adev->mc.visible_vram_size ? 50 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : 51 mem->size; 52 } 53 54 static void amdgpu_update_memory_usage(struct amdgpu_device *adev, 55 struct ttm_mem_reg *old_mem, 56 struct ttm_mem_reg *new_mem) 57 { 58 u64 vis_size; 59 if (!adev) 60 return; 61 62 if (new_mem) { 63 switch (new_mem->mem_type) { 64 case TTM_PL_TT: 65 atomic64_add(new_mem->size, &adev->gtt_usage); 66 break; 67 case TTM_PL_VRAM: 68 atomic64_add(new_mem->size, &adev->vram_usage); 69 vis_size = amdgpu_get_vis_part_size(adev, new_mem); 70 atomic64_add(vis_size, &adev->vram_vis_usage); 71 break; 72 } 73 } 74 75 if (old_mem) { 76 switch (old_mem->mem_type) { 77 case TTM_PL_TT: 78 atomic64_sub(old_mem->size, &adev->gtt_usage); 79 break; 80 case TTM_PL_VRAM: 81 atomic64_sub(old_mem->size, &adev->vram_usage); 82 vis_size = amdgpu_get_vis_part_size(adev, old_mem); 83 atomic64_sub(vis_size, &adev->vram_vis_usage); 84 break; 85 } 86 } 87 } 88 89 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 90 { 91 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 92 struct amdgpu_bo *bo; 93 94 bo = container_of(tbo, struct amdgpu_bo, tbo); 95 96 amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL); 97 98 drm_gem_object_release(&bo->gem_base); 99 amdgpu_bo_unref(&bo->parent); 100 if (!list_empty(&bo->shadow_list)) { 101 mutex_lock(&adev->shadow_list_lock); 102 list_del_init(&bo->shadow_list); 103 mutex_unlock(&adev->shadow_list_lock); 104 } 105 kfree(bo->metadata); 106 kfree(bo); 107 } 108 109 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 110 { 111 if (bo->destroy == &amdgpu_ttm_bo_destroy) 112 return true; 113 return false; 114 } 115 116 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 117 struct ttm_placement *placement, 118 struct ttm_place *places, 119 u32 domain, u64 flags) 120 { 121 u32 c = 0; 122 123 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 124 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 125 126 places[c].fpfn = 0; 127 places[c].lpfn = 0; 128 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 129 TTM_PL_FLAG_VRAM; 130 131 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 132 places[c].lpfn = visible_pfn; 133 else 134 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 135 136 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 137 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 138 c++; 139 } 140 141 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 142 places[c].fpfn = 0; 143 places[c].lpfn = 0; 144 places[c].flags = TTM_PL_FLAG_TT; 145 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 146 places[c].flags |= TTM_PL_FLAG_WC | 147 TTM_PL_FLAG_UNCACHED; 148 else 149 places[c].flags |= TTM_PL_FLAG_CACHED; 150 c++; 151 } 152 153 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 154 places[c].fpfn = 0; 155 places[c].lpfn = 0; 156 places[c].flags = TTM_PL_FLAG_SYSTEM; 157 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 158 places[c].flags |= TTM_PL_FLAG_WC | 159 TTM_PL_FLAG_UNCACHED; 160 else 161 places[c].flags |= TTM_PL_FLAG_CACHED; 162 c++; 163 } 164 165 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 166 places[c].fpfn = 0; 167 places[c].lpfn = 0; 168 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 169 c++; 170 } 171 172 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 173 places[c].fpfn = 0; 174 places[c].lpfn = 0; 175 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 176 c++; 177 } 178 179 if (domain & AMDGPU_GEM_DOMAIN_OA) { 180 places[c].fpfn = 0; 181 places[c].lpfn = 0; 182 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 183 c++; 184 } 185 186 if (!c) { 187 places[c].fpfn = 0; 188 places[c].lpfn = 0; 189 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 190 c++; 191 } 192 193 placement->num_placement = c; 194 placement->placement = places; 195 196 placement->num_busy_placement = c; 197 placement->busy_placement = places; 198 } 199 200 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 201 { 202 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 203 204 amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements, 205 domain, abo->flags); 206 } 207 208 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 209 struct ttm_placement *placement) 210 { 211 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 212 213 memcpy(bo->placements, placement->placement, 214 placement->num_placement * sizeof(struct ttm_place)); 215 bo->placement.num_placement = placement->num_placement; 216 bo->placement.num_busy_placement = placement->num_busy_placement; 217 bo->placement.placement = bo->placements; 218 bo->placement.busy_placement = bo->placements; 219 } 220 221 /** 222 * amdgpu_bo_create_kernel - create BO for kernel use 223 * 224 * @adev: amdgpu device object 225 * @size: size for the new BO 226 * @align: alignment for the new BO 227 * @domain: where to place it 228 * @bo_ptr: resulting BO 229 * @gpu_addr: GPU addr of the pinned BO 230 * @cpu_addr: optional CPU address mapping 231 * 232 * Allocates and pins a BO for kernel internal use. 233 * 234 * Returns 0 on success, negative error code otherwise. 235 */ 236 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 237 unsigned long size, int align, 238 u32 domain, struct amdgpu_bo **bo_ptr, 239 u64 *gpu_addr, void **cpu_addr) 240 { 241 int r; 242 243 r = amdgpu_bo_create(adev, size, align, true, domain, 244 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 245 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 246 NULL, NULL, bo_ptr); 247 if (r) { 248 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r); 249 return r; 250 } 251 252 r = amdgpu_bo_reserve(*bo_ptr, false); 253 if (r) { 254 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 255 goto error_free; 256 } 257 258 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr); 259 if (r) { 260 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 261 goto error_unreserve; 262 } 263 264 if (cpu_addr) { 265 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 266 if (r) { 267 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 268 goto error_unreserve; 269 } 270 } 271 272 amdgpu_bo_unreserve(*bo_ptr); 273 274 return 0; 275 276 error_unreserve: 277 amdgpu_bo_unreserve(*bo_ptr); 278 279 error_free: 280 amdgpu_bo_unref(bo_ptr); 281 282 return r; 283 } 284 285 /** 286 * amdgpu_bo_free_kernel - free BO for kernel use 287 * 288 * @bo: amdgpu BO to free 289 * 290 * unmaps and unpin a BO for kernel internal use. 291 */ 292 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 293 void **cpu_addr) 294 { 295 if (*bo == NULL) 296 return; 297 298 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 299 if (cpu_addr) 300 amdgpu_bo_kunmap(*bo); 301 302 amdgpu_bo_unpin(*bo); 303 amdgpu_bo_unreserve(*bo); 304 } 305 amdgpu_bo_unref(bo); 306 307 if (gpu_addr) 308 *gpu_addr = 0; 309 310 if (cpu_addr) 311 *cpu_addr = NULL; 312 } 313 314 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 315 unsigned long size, int byte_align, 316 bool kernel, u32 domain, u64 flags, 317 struct sg_table *sg, 318 struct ttm_placement *placement, 319 struct reservation_object *resv, 320 struct amdgpu_bo **bo_ptr) 321 { 322 struct amdgpu_bo *bo; 323 enum ttm_bo_type type; 324 unsigned long page_align; 325 u64 initial_bytes_moved; 326 size_t acc_size; 327 int r; 328 329 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 330 size = ALIGN(size, PAGE_SIZE); 331 332 if (kernel) { 333 type = ttm_bo_type_kernel; 334 } else if (sg) { 335 type = ttm_bo_type_sg; 336 } else { 337 type = ttm_bo_type_device; 338 } 339 *bo_ptr = NULL; 340 341 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 342 sizeof(struct amdgpu_bo)); 343 344 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 345 if (bo == NULL) 346 return -ENOMEM; 347 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 348 if (unlikely(r)) { 349 kfree(bo); 350 return r; 351 } 352 INIT_LIST_HEAD(&bo->shadow_list); 353 INIT_LIST_HEAD(&bo->va); 354 bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | 355 AMDGPU_GEM_DOMAIN_GTT | 356 AMDGPU_GEM_DOMAIN_CPU | 357 AMDGPU_GEM_DOMAIN_GDS | 358 AMDGPU_GEM_DOMAIN_GWS | 359 AMDGPU_GEM_DOMAIN_OA); 360 bo->allowed_domains = bo->prefered_domains; 361 if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 362 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 363 364 bo->flags = flags; 365 366 #ifdef CONFIG_X86_32 367 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 368 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 369 */ 370 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 371 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 372 /* Don't try to enable write-combining when it can't work, or things 373 * may be slow 374 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 375 */ 376 377 #ifndef CONFIG_COMPILE_TEST 378 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 379 thanks to write-combining 380 #endif 381 382 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 383 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 384 "better performance thanks to write-combining\n"); 385 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 386 #else 387 /* For architectures that don't support WC memory, 388 * mask out the WC flag from the BO 389 */ 390 if (!drm_arch_can_wc_memory()) 391 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 392 #endif 393 394 amdgpu_fill_placement_to_bo(bo, placement); 395 /* Kernel allocation are uninterruptible */ 396 397 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); 398 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, 399 &bo->placement, page_align, !kernel, NULL, 400 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 401 amdgpu_cs_report_moved_bytes(adev, 402 atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved); 403 404 if (unlikely(r != 0)) 405 return r; 406 407 if (kernel) 408 bo->tbo.priority = 1; 409 410 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 411 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 412 struct dma_fence *fence; 413 414 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); 415 if (unlikely(r)) 416 goto fail_unreserve; 417 418 amdgpu_bo_fence(bo, fence, false); 419 dma_fence_put(bo->tbo.moving); 420 bo->tbo.moving = dma_fence_get(fence); 421 dma_fence_put(fence); 422 } 423 if (!resv) 424 amdgpu_bo_unreserve(bo); 425 *bo_ptr = bo; 426 427 trace_amdgpu_bo_create(bo); 428 429 return 0; 430 431 fail_unreserve: 432 if (!resv) 433 ww_mutex_unlock(&bo->tbo.resv->lock); 434 amdgpu_bo_unref(&bo); 435 return r; 436 } 437 438 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 439 unsigned long size, int byte_align, 440 struct amdgpu_bo *bo) 441 { 442 struct ttm_placement placement = {0}; 443 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 444 int r; 445 446 if (bo->shadow) 447 return 0; 448 449 bo->flags |= AMDGPU_GEM_CREATE_SHADOW; 450 memset(&placements, 0, 451 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 452 453 amdgpu_ttm_placement_init(adev, &placement, 454 placements, AMDGPU_GEM_DOMAIN_GTT, 455 AMDGPU_GEM_CREATE_CPU_GTT_USWC); 456 457 r = amdgpu_bo_create_restricted(adev, size, byte_align, true, 458 AMDGPU_GEM_DOMAIN_GTT, 459 AMDGPU_GEM_CREATE_CPU_GTT_USWC, 460 NULL, &placement, 461 bo->tbo.resv, 462 &bo->shadow); 463 if (!r) { 464 bo->shadow->parent = amdgpu_bo_ref(bo); 465 mutex_lock(&adev->shadow_list_lock); 466 list_add_tail(&bo->shadow_list, &adev->shadow_list); 467 mutex_unlock(&adev->shadow_list_lock); 468 } 469 470 return r; 471 } 472 473 int amdgpu_bo_create(struct amdgpu_device *adev, 474 unsigned long size, int byte_align, 475 bool kernel, u32 domain, u64 flags, 476 struct sg_table *sg, 477 struct reservation_object *resv, 478 struct amdgpu_bo **bo_ptr) 479 { 480 struct ttm_placement placement = {0}; 481 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 482 int r; 483 484 memset(&placements, 0, 485 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 486 487 amdgpu_ttm_placement_init(adev, &placement, 488 placements, domain, flags); 489 490 r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, 491 domain, flags, sg, &placement, 492 resv, bo_ptr); 493 if (r) 494 return r; 495 496 if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) { 497 if (!resv) { 498 r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL); 499 WARN_ON(r != 0); 500 } 501 502 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr)); 503 504 if (!resv) 505 ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock); 506 507 if (r) 508 amdgpu_bo_unref(bo_ptr); 509 } 510 511 return r; 512 } 513 514 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 515 struct amdgpu_ring *ring, 516 struct amdgpu_bo *bo, 517 struct reservation_object *resv, 518 struct dma_fence **fence, 519 bool direct) 520 521 { 522 struct amdgpu_bo *shadow = bo->shadow; 523 uint64_t bo_addr, shadow_addr; 524 int r; 525 526 if (!shadow) 527 return -EINVAL; 528 529 bo_addr = amdgpu_bo_gpu_offset(bo); 530 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 531 532 r = reservation_object_reserve_shared(bo->tbo.resv); 533 if (r) 534 goto err; 535 536 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr, 537 amdgpu_bo_size(bo), resv, fence, 538 direct); 539 if (!r) 540 amdgpu_bo_fence(bo, *fence, true); 541 542 err: 543 return r; 544 } 545 546 int amdgpu_bo_validate(struct amdgpu_bo *bo) 547 { 548 uint32_t domain; 549 int r; 550 551 if (bo->pin_count) 552 return 0; 553 554 domain = bo->prefered_domains; 555 556 retry: 557 amdgpu_ttm_placement_from_domain(bo, domain); 558 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 559 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 560 domain = bo->allowed_domains; 561 goto retry; 562 } 563 564 return r; 565 } 566 567 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 568 struct amdgpu_ring *ring, 569 struct amdgpu_bo *bo, 570 struct reservation_object *resv, 571 struct dma_fence **fence, 572 bool direct) 573 574 { 575 struct amdgpu_bo *shadow = bo->shadow; 576 uint64_t bo_addr, shadow_addr; 577 int r; 578 579 if (!shadow) 580 return -EINVAL; 581 582 bo_addr = amdgpu_bo_gpu_offset(bo); 583 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 584 585 r = reservation_object_reserve_shared(bo->tbo.resv); 586 if (r) 587 goto err; 588 589 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr, 590 amdgpu_bo_size(bo), resv, fence, 591 direct); 592 if (!r) 593 amdgpu_bo_fence(bo, *fence, true); 594 595 err: 596 return r; 597 } 598 599 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 600 { 601 bool is_iomem; 602 long r; 603 604 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 605 return -EPERM; 606 607 if (bo->kptr) { 608 if (ptr) { 609 *ptr = bo->kptr; 610 } 611 return 0; 612 } 613 614 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 615 MAX_SCHEDULE_TIMEOUT); 616 if (r < 0) 617 return r; 618 619 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 620 if (r) 621 return r; 622 623 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 624 if (ptr) 625 *ptr = bo->kptr; 626 627 return 0; 628 } 629 630 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 631 { 632 if (bo->kptr == NULL) 633 return; 634 bo->kptr = NULL; 635 ttm_bo_kunmap(&bo->kmap); 636 } 637 638 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 639 { 640 if (bo == NULL) 641 return NULL; 642 643 ttm_bo_reference(&bo->tbo); 644 return bo; 645 } 646 647 void amdgpu_bo_unref(struct amdgpu_bo **bo) 648 { 649 struct ttm_buffer_object *tbo; 650 651 if ((*bo) == NULL) 652 return; 653 654 tbo = &((*bo)->tbo); 655 ttm_bo_unref(&tbo); 656 if (tbo == NULL) 657 *bo = NULL; 658 } 659 660 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 661 u64 min_offset, u64 max_offset, 662 u64 *gpu_addr) 663 { 664 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 665 int r, i; 666 unsigned fpfn, lpfn; 667 668 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 669 return -EPERM; 670 671 if (WARN_ON_ONCE(min_offset > max_offset)) 672 return -EINVAL; 673 674 /* A shared bo cannot be migrated to VRAM */ 675 if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM)) 676 return -EINVAL; 677 678 if (bo->pin_count) { 679 uint32_t mem_type = bo->tbo.mem.mem_type; 680 681 if (domain != amdgpu_mem_type_to_domain(mem_type)) 682 return -EINVAL; 683 684 bo->pin_count++; 685 if (gpu_addr) 686 *gpu_addr = amdgpu_bo_gpu_offset(bo); 687 688 if (max_offset != 0) { 689 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 690 WARN_ON_ONCE(max_offset < 691 (amdgpu_bo_gpu_offset(bo) - domain_start)); 692 } 693 694 return 0; 695 } 696 697 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 698 amdgpu_ttm_placement_from_domain(bo, domain); 699 for (i = 0; i < bo->placement.num_placement; i++) { 700 /* force to pin into visible video ram */ 701 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 702 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 703 (!max_offset || max_offset > 704 adev->mc.visible_vram_size)) { 705 if (WARN_ON_ONCE(min_offset > 706 adev->mc.visible_vram_size)) 707 return -EINVAL; 708 fpfn = min_offset >> PAGE_SHIFT; 709 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 710 } else { 711 fpfn = min_offset >> PAGE_SHIFT; 712 lpfn = max_offset >> PAGE_SHIFT; 713 } 714 if (fpfn > bo->placements[i].fpfn) 715 bo->placements[i].fpfn = fpfn; 716 if (!bo->placements[i].lpfn || 717 (lpfn && lpfn < bo->placements[i].lpfn)) 718 bo->placements[i].lpfn = lpfn; 719 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 720 } 721 722 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 723 if (unlikely(r)) { 724 dev_err(adev->dev, "%p pin failed\n", bo); 725 goto error; 726 } 727 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); 728 if (unlikely(r)) { 729 dev_err(adev->dev, "%p bind failed\n", bo); 730 goto error; 731 } 732 733 bo->pin_count = 1; 734 if (gpu_addr != NULL) 735 *gpu_addr = amdgpu_bo_gpu_offset(bo); 736 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 737 adev->vram_pin_size += amdgpu_bo_size(bo); 738 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 739 adev->invisible_pin_size += amdgpu_bo_size(bo); 740 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 741 adev->gart_pin_size += amdgpu_bo_size(bo); 742 } 743 744 error: 745 return r; 746 } 747 748 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 749 { 750 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 751 } 752 753 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 754 { 755 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 756 int r, i; 757 758 if (!bo->pin_count) { 759 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 760 return 0; 761 } 762 bo->pin_count--; 763 if (bo->pin_count) 764 return 0; 765 for (i = 0; i < bo->placement.num_placement; i++) { 766 bo->placements[i].lpfn = 0; 767 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 768 } 769 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 770 if (unlikely(r)) { 771 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 772 goto error; 773 } 774 775 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 776 adev->vram_pin_size -= amdgpu_bo_size(bo); 777 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 778 adev->invisible_pin_size -= amdgpu_bo_size(bo); 779 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 780 adev->gart_pin_size -= amdgpu_bo_size(bo); 781 } 782 783 error: 784 return r; 785 } 786 787 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 788 { 789 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 790 if (0 && (adev->flags & AMD_IS_APU)) { 791 /* Useless to evict on IGP chips */ 792 return 0; 793 } 794 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 795 } 796 797 static const char *amdgpu_vram_names[] = { 798 "UNKNOWN", 799 "GDDR1", 800 "DDR2", 801 "GDDR3", 802 "GDDR4", 803 "GDDR5", 804 "HBM", 805 "DDR3" 806 }; 807 808 int amdgpu_bo_init(struct amdgpu_device *adev) 809 { 810 /* reserve PAT memory space to WC for VRAM */ 811 arch_io_reserve_memtype_wc(adev->mc.aper_base, 812 adev->mc.aper_size); 813 814 /* Add an MTRR for the VRAM */ 815 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 816 adev->mc.aper_size); 817 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 818 adev->mc.mc_vram_size >> 20, 819 (unsigned long long)adev->mc.aper_size >> 20); 820 DRM_INFO("RAM width %dbits %s\n", 821 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); 822 return amdgpu_ttm_init(adev); 823 } 824 825 void amdgpu_bo_fini(struct amdgpu_device *adev) 826 { 827 amdgpu_ttm_fini(adev); 828 arch_phys_wc_del(adev->mc.vram_mtrr); 829 arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size); 830 } 831 832 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 833 struct vm_area_struct *vma) 834 { 835 return ttm_fbdev_mmap(vma, &bo->tbo); 836 } 837 838 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 839 { 840 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 841 842 if (adev->family <= AMDGPU_FAMILY_CZ && 843 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 844 return -EINVAL; 845 846 bo->tiling_flags = tiling_flags; 847 return 0; 848 } 849 850 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 851 { 852 lockdep_assert_held(&bo->tbo.resv->lock.base); 853 854 if (tiling_flags) 855 *tiling_flags = bo->tiling_flags; 856 } 857 858 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 859 uint32_t metadata_size, uint64_t flags) 860 { 861 void *buffer; 862 863 if (!metadata_size) { 864 if (bo->metadata_size) { 865 kfree(bo->metadata); 866 bo->metadata = NULL; 867 bo->metadata_size = 0; 868 } 869 return 0; 870 } 871 872 if (metadata == NULL) 873 return -EINVAL; 874 875 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 876 if (buffer == NULL) 877 return -ENOMEM; 878 879 kfree(bo->metadata); 880 bo->metadata_flags = flags; 881 bo->metadata = buffer; 882 bo->metadata_size = metadata_size; 883 884 return 0; 885 } 886 887 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 888 size_t buffer_size, uint32_t *metadata_size, 889 uint64_t *flags) 890 { 891 if (!buffer && !metadata_size) 892 return -EINVAL; 893 894 if (buffer) { 895 if (buffer_size < bo->metadata_size) 896 return -EINVAL; 897 898 if (bo->metadata_size) 899 memcpy(buffer, bo->metadata, bo->metadata_size); 900 } 901 902 if (metadata_size) 903 *metadata_size = bo->metadata_size; 904 if (flags) 905 *flags = bo->metadata_flags; 906 907 return 0; 908 } 909 910 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 911 bool evict, 912 struct ttm_mem_reg *new_mem) 913 { 914 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 915 struct amdgpu_bo *abo; 916 struct ttm_mem_reg *old_mem = &bo->mem; 917 918 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 919 return; 920 921 abo = container_of(bo, struct amdgpu_bo, tbo); 922 amdgpu_vm_bo_invalidate(adev, abo); 923 924 /* remember the eviction */ 925 if (evict) 926 atomic64_inc(&adev->num_evictions); 927 928 /* update statistics */ 929 if (!new_mem) 930 return; 931 932 /* move_notify is called before move happens */ 933 amdgpu_update_memory_usage(adev, &bo->mem, new_mem); 934 935 trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 936 } 937 938 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 939 { 940 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 941 struct amdgpu_bo *abo; 942 unsigned long offset, size, lpfn; 943 int i, r; 944 945 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 946 return 0; 947 948 abo = container_of(bo, struct amdgpu_bo, tbo); 949 if (bo->mem.mem_type != TTM_PL_VRAM) 950 return 0; 951 952 size = bo->mem.num_pages << PAGE_SHIFT; 953 offset = bo->mem.start << PAGE_SHIFT; 954 /* TODO: figure out how to map scattered VRAM to the CPU */ 955 if ((offset + size) <= adev->mc.visible_vram_size) 956 return 0; 957 958 /* Can't move a pinned BO to visible VRAM */ 959 if (abo->pin_count > 0) 960 return -EINVAL; 961 962 /* hurrah the memory is not visible ! */ 963 atomic64_inc(&adev->num_vram_cpu_page_faults); 964 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); 965 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 966 for (i = 0; i < abo->placement.num_placement; i++) { 967 /* Force into visible VRAM */ 968 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && 969 (!abo->placements[i].lpfn || 970 abo->placements[i].lpfn > lpfn)) 971 abo->placements[i].lpfn = lpfn; 972 } 973 r = ttm_bo_validate(bo, &abo->placement, false, false); 974 if (unlikely(r == -ENOMEM)) { 975 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 976 return ttm_bo_validate(bo, &abo->placement, false, false); 977 } else if (unlikely(r != 0)) { 978 return r; 979 } 980 981 offset = bo->mem.start << PAGE_SHIFT; 982 /* this should never happen */ 983 if ((offset + size) > adev->mc.visible_vram_size) 984 return -EINVAL; 985 986 return 0; 987 } 988 989 /** 990 * amdgpu_bo_fence - add fence to buffer object 991 * 992 * @bo: buffer object in question 993 * @fence: fence to add 994 * @shared: true if fence should be added shared 995 * 996 */ 997 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 998 bool shared) 999 { 1000 struct reservation_object *resv = bo->tbo.resv; 1001 1002 if (shared) 1003 reservation_object_add_shared_fence(resv, fence); 1004 else 1005 reservation_object_add_excl_fence(resv, fence); 1006 } 1007 1008 /** 1009 * amdgpu_bo_gpu_offset - return GPU offset of bo 1010 * @bo: amdgpu object for which we query the offset 1011 * 1012 * Returns current GPU offset of the object. 1013 * 1014 * Note: object should either be pinned or reserved when calling this 1015 * function, it might be useful to add check for this for debugging. 1016 */ 1017 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1018 { 1019 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1020 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && 1021 !amdgpu_ttm_is_bound(bo->tbo.ttm)); 1022 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 1023 !bo->pin_count); 1024 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1025 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1026 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1027 1028 return bo->tbo.offset; 1029 } 1030