1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 59 60 amdgpu_bo_kunmap(bo); 61 62 if (bo->tbo.base.import_attach) 63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 64 drm_gem_object_release(&bo->tbo.base); 65 amdgpu_bo_unref(&bo->parent); 66 kvfree(bo); 67 } 68 69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 70 { 71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 72 struct amdgpu_bo_user *ubo; 73 74 ubo = to_amdgpu_bo_user(bo); 75 kfree(ubo->metadata); 76 amdgpu_bo_destroy(tbo); 77 } 78 79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 82 struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; 83 struct amdgpu_bo_vm *vmbo; 84 85 bo = shadow_bo->parent; 86 vmbo = to_amdgpu_bo_vm(bo); 87 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 88 if (!list_empty(&vmbo->shadow_list)) { 89 mutex_lock(&adev->shadow_list_lock); 90 list_del_init(&vmbo->shadow_list); 91 mutex_unlock(&adev->shadow_list_lock); 92 } 93 94 amdgpu_bo_destroy(tbo); 95 } 96 97 /** 98 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 99 * @bo: buffer object to be checked 100 * 101 * Uses destroy function associated with the object to determine if this is 102 * an &amdgpu_bo. 103 * 104 * Returns: 105 * true if the object belongs to &amdgpu_bo, false if not. 106 */ 107 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 108 { 109 if (bo->destroy == &amdgpu_bo_destroy || 110 bo->destroy == &amdgpu_bo_user_destroy || 111 bo->destroy == &amdgpu_bo_vm_destroy) 112 return true; 113 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 136 137 if (adev->gmc.mem_partitions && mem_id >= 0) { 138 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn; 139 /* 140 * memory partition range lpfn is inclusive start + size - 1 141 * TTM place lpfn is exclusive start + size 142 */ 143 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1; 144 } else { 145 places[c].fpfn = 0; 146 places[c].lpfn = 0; 147 } 148 places[c].mem_type = TTM_PL_VRAM; 149 places[c].flags = 0; 150 151 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 152 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); 153 else 154 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 155 156 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 157 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 158 c++; 159 } 160 161 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 162 places[c].fpfn = 0; 163 places[c].lpfn = 0; 164 places[c].mem_type = 165 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 166 AMDGPU_PL_PREEMPT : TTM_PL_TT; 167 places[c].flags = 0; 168 c++; 169 } 170 171 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 172 places[c].fpfn = 0; 173 places[c].lpfn = 0; 174 places[c].mem_type = TTM_PL_SYSTEM; 175 places[c].flags = 0; 176 c++; 177 } 178 179 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 180 places[c].fpfn = 0; 181 places[c].lpfn = 0; 182 places[c].mem_type = AMDGPU_PL_GDS; 183 places[c].flags = 0; 184 c++; 185 } 186 187 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 188 places[c].fpfn = 0; 189 places[c].lpfn = 0; 190 places[c].mem_type = AMDGPU_PL_GWS; 191 places[c].flags = 0; 192 c++; 193 } 194 195 if (domain & AMDGPU_GEM_DOMAIN_OA) { 196 places[c].fpfn = 0; 197 places[c].lpfn = 0; 198 places[c].mem_type = AMDGPU_PL_OA; 199 places[c].flags = 0; 200 c++; 201 } 202 203 if (!c) { 204 places[c].fpfn = 0; 205 places[c].lpfn = 0; 206 places[c].mem_type = TTM_PL_SYSTEM; 207 places[c].flags = 0; 208 c++; 209 } 210 211 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 212 213 placement->num_placement = c; 214 placement->placement = places; 215 216 placement->num_busy_placement = c; 217 placement->busy_placement = places; 218 } 219 220 /** 221 * amdgpu_bo_create_reserved - create reserved BO for kernel use 222 * 223 * @adev: amdgpu device object 224 * @size: size for the new BO 225 * @align: alignment for the new BO 226 * @domain: where to place it 227 * @bo_ptr: used to initialize BOs in structures 228 * @gpu_addr: GPU addr of the pinned BO 229 * @cpu_addr: optional CPU address mapping 230 * 231 * Allocates and pins a BO for kernel internal use, and returns it still 232 * reserved. 233 * 234 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 235 * 236 * Returns: 237 * 0 on success, negative error code otherwise. 238 */ 239 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 240 unsigned long size, int align, 241 u32 domain, struct amdgpu_bo **bo_ptr, 242 u64 *gpu_addr, void **cpu_addr) 243 { 244 struct amdgpu_bo_param bp; 245 bool free = false; 246 int r; 247 248 if (!size) { 249 amdgpu_bo_unref(bo_ptr); 250 return 0; 251 } 252 253 memset(&bp, 0, sizeof(bp)); 254 bp.size = size; 255 bp.byte_align = align; 256 bp.domain = domain; 257 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 258 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 259 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 260 bp.type = ttm_bo_type_kernel; 261 bp.resv = NULL; 262 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 263 264 if (!*bo_ptr) { 265 r = amdgpu_bo_create(adev, &bp, bo_ptr); 266 if (r) { 267 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 268 r); 269 return r; 270 } 271 free = true; 272 } 273 274 r = amdgpu_bo_reserve(*bo_ptr, false); 275 if (r) { 276 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 277 goto error_free; 278 } 279 280 r = amdgpu_bo_pin(*bo_ptr, domain); 281 if (r) { 282 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 283 goto error_unreserve; 284 } 285 286 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 287 if (r) { 288 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 289 goto error_unpin; 290 } 291 292 if (gpu_addr) 293 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 294 295 if (cpu_addr) { 296 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 297 if (r) { 298 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 299 goto error_unpin; 300 } 301 } 302 303 return 0; 304 305 error_unpin: 306 amdgpu_bo_unpin(*bo_ptr); 307 error_unreserve: 308 amdgpu_bo_unreserve(*bo_ptr); 309 310 error_free: 311 if (free) 312 amdgpu_bo_unref(bo_ptr); 313 314 return r; 315 } 316 317 /** 318 * amdgpu_bo_create_kernel - create BO for kernel use 319 * 320 * @adev: amdgpu device object 321 * @size: size for the new BO 322 * @align: alignment for the new BO 323 * @domain: where to place it 324 * @bo_ptr: used to initialize BOs in structures 325 * @gpu_addr: GPU addr of the pinned BO 326 * @cpu_addr: optional CPU address mapping 327 * 328 * Allocates and pins a BO for kernel internal use. 329 * 330 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 331 * 332 * Returns: 333 * 0 on success, negative error code otherwise. 334 */ 335 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 336 unsigned long size, int align, 337 u32 domain, struct amdgpu_bo **bo_ptr, 338 u64 *gpu_addr, void **cpu_addr) 339 { 340 int r; 341 342 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 343 gpu_addr, cpu_addr); 344 345 if (r) 346 return r; 347 348 if (*bo_ptr) 349 amdgpu_bo_unreserve(*bo_ptr); 350 351 return 0; 352 } 353 354 /** 355 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 356 * 357 * @adev: amdgpu device object 358 * @offset: offset of the BO 359 * @size: size of the BO 360 * @bo_ptr: used to initialize BOs in structures 361 * @cpu_addr: optional CPU address mapping 362 * 363 * Creates a kernel BO at a specific offset in VRAM. 364 * 365 * Returns: 366 * 0 on success, negative error code otherwise. 367 */ 368 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 369 uint64_t offset, uint64_t size, 370 struct amdgpu_bo **bo_ptr, void **cpu_addr) 371 { 372 struct ttm_operation_ctx ctx = { false, false }; 373 unsigned int i; 374 int r; 375 376 offset &= PAGE_MASK; 377 size = ALIGN(size, PAGE_SIZE); 378 379 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 380 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL, 381 cpu_addr); 382 if (r) 383 return r; 384 385 if ((*bo_ptr) == NULL) 386 return 0; 387 388 /* 389 * Remove the original mem node and create a new one at the request 390 * position. 391 */ 392 if (cpu_addr) 393 amdgpu_bo_kunmap(*bo_ptr); 394 395 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 396 397 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 398 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 399 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 400 } 401 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 402 &(*bo_ptr)->tbo.resource, &ctx); 403 if (r) 404 goto error; 405 406 if (cpu_addr) { 407 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 408 if (r) 409 goto error; 410 } 411 412 amdgpu_bo_unreserve(*bo_ptr); 413 return 0; 414 415 error: 416 amdgpu_bo_unreserve(*bo_ptr); 417 amdgpu_bo_unref(bo_ptr); 418 return r; 419 } 420 421 /** 422 * amdgpu_bo_free_kernel - free BO for kernel use 423 * 424 * @bo: amdgpu BO to free 425 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 426 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 427 * 428 * unmaps and unpin a BO for kernel internal use. 429 */ 430 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 431 void **cpu_addr) 432 { 433 if (*bo == NULL) 434 return; 435 436 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend); 437 438 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 439 if (cpu_addr) 440 amdgpu_bo_kunmap(*bo); 441 442 amdgpu_bo_unpin(*bo); 443 amdgpu_bo_unreserve(*bo); 444 } 445 amdgpu_bo_unref(bo); 446 447 if (gpu_addr) 448 *gpu_addr = 0; 449 450 if (cpu_addr) 451 *cpu_addr = NULL; 452 } 453 454 /* Validate bo size is bit bigger then the request domain */ 455 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 456 unsigned long size, u32 domain) 457 { 458 struct ttm_resource_manager *man = NULL; 459 460 /* 461 * If GTT is part of requested domains the check must succeed to 462 * allow fall back to GTT. 463 */ 464 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 465 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 466 467 if (man && size < man->size) 468 return true; 469 else if (!man) 470 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 471 goto fail; 472 } else if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 473 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 474 475 if (man && size < man->size) 476 return true; 477 goto fail; 478 } 479 480 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 481 return true; 482 483 fail: 484 if (man) 485 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 486 man->size); 487 return false; 488 } 489 490 bool amdgpu_bo_support_uswc(u64 bo_flags) 491 { 492 493 #ifdef CONFIG_X86_32 494 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 495 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 496 */ 497 return false; 498 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 499 /* Don't try to enable write-combining when it can't work, or things 500 * may be slow 501 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 502 */ 503 504 #ifndef CONFIG_COMPILE_TEST 505 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 506 thanks to write-combining 507 #endif 508 509 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 510 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 511 "better performance thanks to write-combining\n"); 512 return false; 513 #else 514 /* For architectures that don't support WC memory, 515 * mask out the WC flag from the BO 516 */ 517 if (!drm_arch_can_wc_memory()) 518 return false; 519 520 return true; 521 #endif 522 } 523 524 /** 525 * amdgpu_bo_create - create an &amdgpu_bo buffer object 526 * @adev: amdgpu device object 527 * @bp: parameters to be used for the buffer object 528 * @bo_ptr: pointer to the buffer object pointer 529 * 530 * Creates an &amdgpu_bo buffer object. 531 * 532 * Returns: 533 * 0 for success or a negative error code on failure. 534 */ 535 int amdgpu_bo_create(struct amdgpu_device *adev, 536 struct amdgpu_bo_param *bp, 537 struct amdgpu_bo **bo_ptr) 538 { 539 struct ttm_operation_ctx ctx = { 540 .interruptible = (bp->type != ttm_bo_type_kernel), 541 .no_wait_gpu = bp->no_wait_gpu, 542 /* We opt to avoid OOM on system pages allocations */ 543 .gfp_retry_mayfail = true, 544 .allow_res_evict = bp->type != ttm_bo_type_kernel, 545 .resv = bp->resv 546 }; 547 struct amdgpu_bo *bo; 548 unsigned long page_align, size = bp->size; 549 int r; 550 551 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 552 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 553 /* GWS and OA don't need any alignment. */ 554 page_align = bp->byte_align; 555 size <<= PAGE_SHIFT; 556 557 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 558 /* Both size and alignment must be a multiple of 4. */ 559 page_align = ALIGN(bp->byte_align, 4); 560 size = ALIGN(size, 4) << PAGE_SHIFT; 561 } else { 562 /* Memory should be aligned at least to a page size. */ 563 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 564 size = ALIGN(size, PAGE_SIZE); 565 } 566 567 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 568 return -ENOMEM; 569 570 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 571 572 *bo_ptr = NULL; 573 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 574 if (bo == NULL) 575 return -ENOMEM; 576 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 577 bo->vm_bo = NULL; 578 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 579 bp->domain; 580 bo->allowed_domains = bo->preferred_domains; 581 if (bp->type != ttm_bo_type_kernel && 582 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 583 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 584 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 585 586 bo->flags = bp->flags; 587 588 if (adev->gmc.mem_partitions) 589 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */ 590 bo->xcp_id = bp->xcp_id_plus1 - 1; 591 else 592 /* For GPUs without spatial partitioning */ 593 bo->xcp_id = 0; 594 595 if (!amdgpu_bo_support_uswc(bo->flags)) 596 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 597 598 if (adev->ras_enabled) 599 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 600 601 bo->tbo.bdev = &adev->mman.bdev; 602 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 603 AMDGPU_GEM_DOMAIN_GDS)) 604 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 605 else 606 amdgpu_bo_placement_from_domain(bo, bp->domain); 607 if (bp->type == ttm_bo_type_kernel) 608 bo->tbo.priority = 1; 609 610 if (!bp->destroy) 611 bp->destroy = &amdgpu_bo_destroy; 612 613 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 614 &bo->placement, page_align, &ctx, NULL, 615 bp->resv, bp->destroy); 616 if (unlikely(r != 0)) 617 return r; 618 619 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 620 bo->tbo.resource->mem_type == TTM_PL_VRAM && 621 amdgpu_bo_in_cpu_visible_vram(bo)) 622 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 623 ctx.bytes_moved); 624 else 625 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 626 627 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 628 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 629 struct dma_fence *fence; 630 631 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence, true); 632 if (unlikely(r)) 633 goto fail_unreserve; 634 635 dma_resv_add_fence(bo->tbo.base.resv, fence, 636 DMA_RESV_USAGE_KERNEL); 637 dma_fence_put(fence); 638 } 639 if (!bp->resv) 640 amdgpu_bo_unreserve(bo); 641 *bo_ptr = bo; 642 643 trace_amdgpu_bo_create(bo); 644 645 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 646 if (bp->type == ttm_bo_type_device) 647 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 648 649 return 0; 650 651 fail_unreserve: 652 if (!bp->resv) 653 dma_resv_unlock(bo->tbo.base.resv); 654 amdgpu_bo_unref(&bo); 655 return r; 656 } 657 658 /** 659 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 660 * @adev: amdgpu device object 661 * @bp: parameters to be used for the buffer object 662 * @ubo_ptr: pointer to the buffer object pointer 663 * 664 * Create a BO to be used by user application; 665 * 666 * Returns: 667 * 0 for success or a negative error code on failure. 668 */ 669 670 int amdgpu_bo_create_user(struct amdgpu_device *adev, 671 struct amdgpu_bo_param *bp, 672 struct amdgpu_bo_user **ubo_ptr) 673 { 674 struct amdgpu_bo *bo_ptr; 675 int r; 676 677 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 678 bp->destroy = &amdgpu_bo_user_destroy; 679 r = amdgpu_bo_create(adev, bp, &bo_ptr); 680 if (r) 681 return r; 682 683 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 684 return r; 685 } 686 687 /** 688 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 689 * @adev: amdgpu device object 690 * @bp: parameters to be used for the buffer object 691 * @vmbo_ptr: pointer to the buffer object pointer 692 * 693 * Create a BO to be for GPUVM. 694 * 695 * Returns: 696 * 0 for success or a negative error code on failure. 697 */ 698 699 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 700 struct amdgpu_bo_param *bp, 701 struct amdgpu_bo_vm **vmbo_ptr) 702 { 703 struct amdgpu_bo *bo_ptr; 704 int r; 705 706 /* bo_ptr_size will be determined by the caller and it depends on 707 * num of amdgpu_vm_pt entries. 708 */ 709 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 710 r = amdgpu_bo_create(adev, bp, &bo_ptr); 711 if (r) 712 return r; 713 714 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 715 return r; 716 } 717 718 /** 719 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 720 * 721 * @vmbo: BO that will be inserted into the shadow list 722 * 723 * Insert a BO to the shadow list. 724 */ 725 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 726 { 727 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 728 729 mutex_lock(&adev->shadow_list_lock); 730 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 731 vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); 732 vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; 733 mutex_unlock(&adev->shadow_list_lock); 734 } 735 736 /** 737 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 738 * 739 * @shadow: &amdgpu_bo shadow to be restored 740 * @fence: dma_fence associated with the operation 741 * 742 * Copies a buffer object's shadow content back to the object. 743 * This is used for recovering a buffer from its shadow in case of a gpu 744 * reset where vram context may be lost. 745 * 746 * Returns: 747 * 0 for success or a negative error code on failure. 748 */ 749 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 750 751 { 752 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 753 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 754 uint64_t shadow_addr, parent_addr; 755 756 shadow_addr = amdgpu_bo_gpu_offset(shadow); 757 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 758 759 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 760 amdgpu_bo_size(shadow), NULL, fence, 761 true, false, false); 762 } 763 764 /** 765 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 766 * @bo: &amdgpu_bo buffer object to be mapped 767 * @ptr: kernel virtual address to be returned 768 * 769 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 770 * amdgpu_bo_kptr() to get the kernel virtual address. 771 * 772 * Returns: 773 * 0 for success or a negative error code on failure. 774 */ 775 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 776 { 777 void *kptr; 778 long r; 779 780 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 781 return -EPERM; 782 783 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 784 false, MAX_SCHEDULE_TIMEOUT); 785 if (r < 0) 786 return r; 787 788 kptr = amdgpu_bo_kptr(bo); 789 if (kptr) { 790 if (ptr) 791 *ptr = kptr; 792 return 0; 793 } 794 795 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 796 if (r) 797 return r; 798 799 if (ptr) 800 *ptr = amdgpu_bo_kptr(bo); 801 802 return 0; 803 } 804 805 /** 806 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 807 * @bo: &amdgpu_bo buffer object 808 * 809 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 810 * 811 * Returns: 812 * the virtual address of a buffer object area. 813 */ 814 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 815 { 816 bool is_iomem; 817 818 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 819 } 820 821 /** 822 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 823 * @bo: &amdgpu_bo buffer object to be unmapped 824 * 825 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 826 */ 827 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 828 { 829 if (bo->kmap.bo) 830 ttm_bo_kunmap(&bo->kmap); 831 } 832 833 /** 834 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 835 * @bo: &amdgpu_bo buffer object 836 * 837 * References the contained &ttm_buffer_object. 838 * 839 * Returns: 840 * a refcounted pointer to the &amdgpu_bo buffer object. 841 */ 842 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 843 { 844 if (bo == NULL) 845 return NULL; 846 847 ttm_bo_get(&bo->tbo); 848 return bo; 849 } 850 851 /** 852 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 853 * @bo: &amdgpu_bo buffer object 854 * 855 * Unreferences the contained &ttm_buffer_object and clear the pointer 856 */ 857 void amdgpu_bo_unref(struct amdgpu_bo **bo) 858 { 859 struct ttm_buffer_object *tbo; 860 861 if ((*bo) == NULL) 862 return; 863 864 tbo = &((*bo)->tbo); 865 ttm_bo_put(tbo); 866 *bo = NULL; 867 } 868 869 /** 870 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 871 * @bo: &amdgpu_bo buffer object to be pinned 872 * @domain: domain to be pinned to 873 * @min_offset: the start of requested address range 874 * @max_offset: the end of requested address range 875 * 876 * Pins the buffer object according to requested domain and address range. If 877 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 878 * pin_count and pin_size accordingly. 879 * 880 * Pinning means to lock pages in memory along with keeping them at a fixed 881 * offset. It is required when a buffer can not be moved, for example, when 882 * a display buffer is being scanned out. 883 * 884 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 885 * where to pin a buffer if there are specific restrictions on where a buffer 886 * must be located. 887 * 888 * Returns: 889 * 0 for success or a negative error code on failure. 890 */ 891 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 892 u64 min_offset, u64 max_offset) 893 { 894 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 895 struct ttm_operation_ctx ctx = { false, false }; 896 int r, i; 897 898 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 899 return -EPERM; 900 901 if (WARN_ON_ONCE(min_offset > max_offset)) 902 return -EINVAL; 903 904 /* Check domain to be pinned to against preferred domains */ 905 if (bo->preferred_domains & domain) 906 domain = bo->preferred_domains & domain; 907 908 /* A shared bo cannot be migrated to VRAM */ 909 if (bo->tbo.base.import_attach) { 910 if (domain & AMDGPU_GEM_DOMAIN_GTT) 911 domain = AMDGPU_GEM_DOMAIN_GTT; 912 else 913 return -EINVAL; 914 } 915 916 if (bo->tbo.pin_count) { 917 uint32_t mem_type = bo->tbo.resource->mem_type; 918 uint32_t mem_flags = bo->tbo.resource->placement; 919 920 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 921 return -EINVAL; 922 923 if ((mem_type == TTM_PL_VRAM) && 924 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 925 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 926 return -EINVAL; 927 928 ttm_bo_pin(&bo->tbo); 929 930 if (max_offset != 0) { 931 u64 domain_start = amdgpu_ttm_domain_start(adev, 932 mem_type); 933 WARN_ON_ONCE(max_offset < 934 (amdgpu_bo_gpu_offset(bo) - domain_start)); 935 } 936 937 return 0; 938 } 939 940 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 941 * See function amdgpu_display_supported_domains() 942 */ 943 domain = amdgpu_bo_get_preferred_domain(adev, domain); 944 945 if (bo->tbo.base.import_attach) 946 dma_buf_pin(bo->tbo.base.import_attach); 947 948 /* force to pin into visible video ram */ 949 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 950 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 951 amdgpu_bo_placement_from_domain(bo, domain); 952 for (i = 0; i < bo->placement.num_placement; i++) { 953 unsigned int fpfn, lpfn; 954 955 fpfn = min_offset >> PAGE_SHIFT; 956 lpfn = max_offset >> PAGE_SHIFT; 957 958 if (fpfn > bo->placements[i].fpfn) 959 bo->placements[i].fpfn = fpfn; 960 if (!bo->placements[i].lpfn || 961 (lpfn && lpfn < bo->placements[i].lpfn)) 962 bo->placements[i].lpfn = lpfn; 963 } 964 965 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 966 if (unlikely(r)) { 967 dev_err(adev->dev, "%p pin failed\n", bo); 968 goto error; 969 } 970 971 ttm_bo_pin(&bo->tbo); 972 973 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 974 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 975 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 976 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 977 &adev->visible_pin_size); 978 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 979 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 980 } 981 982 error: 983 return r; 984 } 985 986 /** 987 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 988 * @bo: &amdgpu_bo buffer object to be pinned 989 * @domain: domain to be pinned to 990 * 991 * A simple wrapper to amdgpu_bo_pin_restricted(). 992 * Provides a simpler API for buffers that do not have any strict restrictions 993 * on where a buffer must be located. 994 * 995 * Returns: 996 * 0 for success or a negative error code on failure. 997 */ 998 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 999 { 1000 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1001 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 1002 } 1003 1004 /** 1005 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 1006 * @bo: &amdgpu_bo buffer object to be unpinned 1007 * 1008 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 1009 * Changes placement and pin size accordingly. 1010 * 1011 * Returns: 1012 * 0 for success or a negative error code on failure. 1013 */ 1014 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1015 { 1016 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1017 1018 ttm_bo_unpin(&bo->tbo); 1019 if (bo->tbo.pin_count) 1020 return; 1021 1022 if (bo->tbo.base.import_attach) 1023 dma_buf_unpin(bo->tbo.base.import_attach); 1024 1025 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1026 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1027 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1028 &adev->visible_pin_size); 1029 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1030 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1031 } 1032 } 1033 1034 static const char * const amdgpu_vram_names[] = { 1035 "UNKNOWN", 1036 "GDDR1", 1037 "DDR2", 1038 "GDDR3", 1039 "GDDR4", 1040 "GDDR5", 1041 "HBM", 1042 "DDR3", 1043 "DDR4", 1044 "GDDR6", 1045 "DDR5", 1046 "LPDDR4", 1047 "LPDDR5" 1048 }; 1049 1050 /** 1051 * amdgpu_bo_init - initialize memory manager 1052 * @adev: amdgpu device object 1053 * 1054 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1055 * 1056 * Returns: 1057 * 0 for success or a negative error code on failure. 1058 */ 1059 int amdgpu_bo_init(struct amdgpu_device *adev) 1060 { 1061 /* On A+A platform, VRAM can be mapped as WB */ 1062 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1063 /* reserve PAT memory space to WC for VRAM */ 1064 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1065 adev->gmc.aper_size); 1066 1067 if (r) { 1068 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1069 return r; 1070 } 1071 1072 /* Add an MTRR for the VRAM */ 1073 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1074 adev->gmc.aper_size); 1075 } 1076 1077 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1078 adev->gmc.mc_vram_size >> 20, 1079 (unsigned long long)adev->gmc.aper_size >> 20); 1080 DRM_INFO("RAM width %dbits %s\n", 1081 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1082 return amdgpu_ttm_init(adev); 1083 } 1084 1085 /** 1086 * amdgpu_bo_fini - tear down memory manager 1087 * @adev: amdgpu device object 1088 * 1089 * Reverses amdgpu_bo_init() to tear down memory manager. 1090 */ 1091 void amdgpu_bo_fini(struct amdgpu_device *adev) 1092 { 1093 int idx; 1094 1095 amdgpu_ttm_fini(adev); 1096 1097 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1098 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1099 arch_phys_wc_del(adev->gmc.vram_mtrr); 1100 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1101 } 1102 drm_dev_exit(idx); 1103 } 1104 } 1105 1106 /** 1107 * amdgpu_bo_set_tiling_flags - set tiling flags 1108 * @bo: &amdgpu_bo buffer object 1109 * @tiling_flags: new flags 1110 * 1111 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1112 * kernel driver to set the tiling flags on a buffer. 1113 * 1114 * Returns: 1115 * 0 for success or a negative error code on failure. 1116 */ 1117 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1118 { 1119 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1120 struct amdgpu_bo_user *ubo; 1121 1122 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1123 if (adev->family <= AMDGPU_FAMILY_CZ && 1124 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1125 return -EINVAL; 1126 1127 ubo = to_amdgpu_bo_user(bo); 1128 ubo->tiling_flags = tiling_flags; 1129 return 0; 1130 } 1131 1132 /** 1133 * amdgpu_bo_get_tiling_flags - get tiling flags 1134 * @bo: &amdgpu_bo buffer object 1135 * @tiling_flags: returned flags 1136 * 1137 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1138 * set the tiling flags on a buffer. 1139 */ 1140 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1141 { 1142 struct amdgpu_bo_user *ubo; 1143 1144 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1145 dma_resv_assert_held(bo->tbo.base.resv); 1146 ubo = to_amdgpu_bo_user(bo); 1147 1148 if (tiling_flags) 1149 *tiling_flags = ubo->tiling_flags; 1150 } 1151 1152 /** 1153 * amdgpu_bo_set_metadata - set metadata 1154 * @bo: &amdgpu_bo buffer object 1155 * @metadata: new metadata 1156 * @metadata_size: size of the new metadata 1157 * @flags: flags of the new metadata 1158 * 1159 * Sets buffer object's metadata, its size and flags. 1160 * Used via GEM ioctl. 1161 * 1162 * Returns: 1163 * 0 for success or a negative error code on failure. 1164 */ 1165 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata, 1166 u32 metadata_size, uint64_t flags) 1167 { 1168 struct amdgpu_bo_user *ubo; 1169 void *buffer; 1170 1171 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1172 ubo = to_amdgpu_bo_user(bo); 1173 if (!metadata_size) { 1174 if (ubo->metadata_size) { 1175 kfree(ubo->metadata); 1176 ubo->metadata = NULL; 1177 ubo->metadata_size = 0; 1178 } 1179 return 0; 1180 } 1181 1182 if (metadata == NULL) 1183 return -EINVAL; 1184 1185 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1186 if (buffer == NULL) 1187 return -ENOMEM; 1188 1189 kfree(ubo->metadata); 1190 ubo->metadata_flags = flags; 1191 ubo->metadata = buffer; 1192 ubo->metadata_size = metadata_size; 1193 1194 return 0; 1195 } 1196 1197 /** 1198 * amdgpu_bo_get_metadata - get metadata 1199 * @bo: &amdgpu_bo buffer object 1200 * @buffer: returned metadata 1201 * @buffer_size: size of the buffer 1202 * @metadata_size: size of the returned metadata 1203 * @flags: flags of the returned metadata 1204 * 1205 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1206 * less than metadata_size. 1207 * Used via GEM ioctl. 1208 * 1209 * Returns: 1210 * 0 for success or a negative error code on failure. 1211 */ 1212 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1213 size_t buffer_size, uint32_t *metadata_size, 1214 uint64_t *flags) 1215 { 1216 struct amdgpu_bo_user *ubo; 1217 1218 if (!buffer && !metadata_size) 1219 return -EINVAL; 1220 1221 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1222 ubo = to_amdgpu_bo_user(bo); 1223 if (metadata_size) 1224 *metadata_size = ubo->metadata_size; 1225 1226 if (buffer) { 1227 if (buffer_size < ubo->metadata_size) 1228 return -EINVAL; 1229 1230 if (ubo->metadata_size) 1231 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1232 } 1233 1234 if (flags) 1235 *flags = ubo->metadata_flags; 1236 1237 return 0; 1238 } 1239 1240 /** 1241 * amdgpu_bo_move_notify - notification about a memory move 1242 * @bo: pointer to a buffer object 1243 * @evict: if this move is evicting the buffer from the graphics address space 1244 * @new_mem: new information of the bufer object 1245 * 1246 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1247 * bookkeeping. 1248 * TTM driver callback which is called when ttm moves a buffer. 1249 */ 1250 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1251 bool evict, 1252 struct ttm_resource *new_mem) 1253 { 1254 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1255 struct amdgpu_bo *abo; 1256 struct ttm_resource *old_mem = bo->resource; 1257 1258 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1259 return; 1260 1261 abo = ttm_to_amdgpu_bo(bo); 1262 amdgpu_vm_bo_invalidate(adev, abo, evict); 1263 1264 amdgpu_bo_kunmap(abo); 1265 1266 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1267 bo->resource->mem_type != TTM_PL_SYSTEM) 1268 dma_buf_move_notify(abo->tbo.base.dma_buf); 1269 1270 /* remember the eviction */ 1271 if (evict) 1272 atomic64_inc(&adev->num_evictions); 1273 1274 /* update statistics */ 1275 if (!new_mem) 1276 return; 1277 1278 /* move_notify is called before move happens */ 1279 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1280 } 1281 1282 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, 1283 struct amdgpu_mem_stats *stats) 1284 { 1285 uint64_t size = amdgpu_bo_size(bo); 1286 unsigned int domain; 1287 1288 /* Abort if the BO doesn't currently have a backing store */ 1289 if (!bo->tbo.resource) 1290 return; 1291 1292 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1293 switch (domain) { 1294 case AMDGPU_GEM_DOMAIN_VRAM: 1295 stats->vram += size; 1296 if (amdgpu_bo_in_cpu_visible_vram(bo)) 1297 stats->visible_vram += size; 1298 break; 1299 case AMDGPU_GEM_DOMAIN_GTT: 1300 stats->gtt += size; 1301 break; 1302 case AMDGPU_GEM_DOMAIN_CPU: 1303 default: 1304 stats->cpu += size; 1305 break; 1306 } 1307 1308 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) { 1309 stats->requested_vram += size; 1310 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1311 stats->requested_visible_vram += size; 1312 1313 if (domain != AMDGPU_GEM_DOMAIN_VRAM) { 1314 stats->evicted_vram += size; 1315 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1316 stats->evicted_visible_vram += size; 1317 } 1318 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) { 1319 stats->requested_gtt += size; 1320 } 1321 } 1322 1323 /** 1324 * amdgpu_bo_release_notify - notification about a BO being released 1325 * @bo: pointer to a buffer object 1326 * 1327 * Wipes VRAM buffers whose contents should not be leaked before the 1328 * memory is released. 1329 */ 1330 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1331 { 1332 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1333 struct dma_fence *fence = NULL; 1334 struct amdgpu_bo *abo; 1335 int r; 1336 1337 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1338 return; 1339 1340 abo = ttm_to_amdgpu_bo(bo); 1341 1342 if (abo->kfd_bo) 1343 amdgpu_amdkfd_release_notify(abo); 1344 1345 /* We only remove the fence if the resv has individualized. */ 1346 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1347 && bo->base.resv != &bo->base._resv); 1348 if (bo->base.resv == &bo->base._resv) 1349 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1350 1351 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1352 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1353 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1354 return; 1355 1356 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1357 return; 1358 1359 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence, true); 1360 if (!WARN_ON(r)) { 1361 amdgpu_bo_fence(abo, fence, false); 1362 dma_fence_put(fence); 1363 } 1364 1365 dma_resv_unlock(bo->base.resv); 1366 } 1367 1368 /** 1369 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1370 * @bo: pointer to a buffer object 1371 * 1372 * Notifies the driver we are taking a fault on this BO and have reserved it, 1373 * also performs bookkeeping. 1374 * TTM driver callback for dealing with vm faults. 1375 * 1376 * Returns: 1377 * 0 for success or a negative error code on failure. 1378 */ 1379 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1380 { 1381 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1382 struct ttm_operation_ctx ctx = { false, false }; 1383 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1384 int r; 1385 1386 /* Remember that this BO was accessed by the CPU */ 1387 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1388 1389 if (bo->resource->mem_type != TTM_PL_VRAM) 1390 return 0; 1391 1392 if (amdgpu_bo_in_cpu_visible_vram(abo)) 1393 return 0; 1394 1395 /* Can't move a pinned BO to visible VRAM */ 1396 if (abo->tbo.pin_count > 0) 1397 return VM_FAULT_SIGBUS; 1398 1399 /* hurrah the memory is not visible ! */ 1400 atomic64_inc(&adev->num_vram_cpu_page_faults); 1401 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1402 AMDGPU_GEM_DOMAIN_GTT); 1403 1404 /* Avoid costly evictions; only set GTT as a busy placement */ 1405 abo->placement.num_busy_placement = 1; 1406 abo->placement.busy_placement = &abo->placements[1]; 1407 1408 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1409 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1410 return VM_FAULT_NOPAGE; 1411 else if (unlikely(r)) 1412 return VM_FAULT_SIGBUS; 1413 1414 /* this should never happen */ 1415 if (bo->resource->mem_type == TTM_PL_VRAM && 1416 !amdgpu_bo_in_cpu_visible_vram(abo)) 1417 return VM_FAULT_SIGBUS; 1418 1419 ttm_bo_move_to_lru_tail_unlocked(bo); 1420 return 0; 1421 } 1422 1423 /** 1424 * amdgpu_bo_fence - add fence to buffer object 1425 * 1426 * @bo: buffer object in question 1427 * @fence: fence to add 1428 * @shared: true if fence should be added shared 1429 * 1430 */ 1431 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1432 bool shared) 1433 { 1434 struct dma_resv *resv = bo->tbo.base.resv; 1435 int r; 1436 1437 r = dma_resv_reserve_fences(resv, 1); 1438 if (r) { 1439 /* As last resort on OOM we block for the fence */ 1440 dma_fence_wait(fence, false); 1441 return; 1442 } 1443 1444 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1445 DMA_RESV_USAGE_WRITE); 1446 } 1447 1448 /** 1449 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1450 * 1451 * @adev: amdgpu device pointer 1452 * @resv: reservation object to sync to 1453 * @sync_mode: synchronization mode 1454 * @owner: fence owner 1455 * @intr: Whether the wait is interruptible 1456 * 1457 * Extract the fences from the reservation object and waits for them to finish. 1458 * 1459 * Returns: 1460 * 0 on success, errno otherwise. 1461 */ 1462 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1463 enum amdgpu_sync_mode sync_mode, void *owner, 1464 bool intr) 1465 { 1466 struct amdgpu_sync sync; 1467 int r; 1468 1469 amdgpu_sync_create(&sync); 1470 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1471 r = amdgpu_sync_wait(&sync, intr); 1472 amdgpu_sync_free(&sync); 1473 return r; 1474 } 1475 1476 /** 1477 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1478 * @bo: buffer object to wait for 1479 * @owner: fence owner 1480 * @intr: Whether the wait is interruptible 1481 * 1482 * Wrapper to wait for fences in a BO. 1483 * Returns: 1484 * 0 on success, errno otherwise. 1485 */ 1486 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1487 { 1488 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1489 1490 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1491 AMDGPU_SYNC_NE_OWNER, owner, intr); 1492 } 1493 1494 /** 1495 * amdgpu_bo_gpu_offset - return GPU offset of bo 1496 * @bo: amdgpu object for which we query the offset 1497 * 1498 * Note: object should either be pinned or reserved when calling this 1499 * function, it might be useful to add check for this for debugging. 1500 * 1501 * Returns: 1502 * current GPU offset of the object. 1503 */ 1504 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1505 { 1506 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1507 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1508 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1509 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1510 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1511 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1512 1513 return amdgpu_bo_gpu_offset_no_check(bo); 1514 } 1515 1516 /** 1517 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1518 * @bo: amdgpu object for which we query the offset 1519 * 1520 * Returns: 1521 * current GPU offset of the object without raising warnings. 1522 */ 1523 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1524 { 1525 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1526 uint64_t offset; 1527 1528 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1529 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1530 1531 return amdgpu_gmc_sign_extend(offset); 1532 } 1533 1534 /** 1535 * amdgpu_bo_get_preferred_domain - get preferred domain 1536 * @adev: amdgpu device object 1537 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1538 * 1539 * Returns: 1540 * Which of the allowed domains is preferred for allocating the BO. 1541 */ 1542 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1543 uint32_t domain) 1544 { 1545 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1546 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1547 domain = AMDGPU_GEM_DOMAIN_VRAM; 1548 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1549 domain = AMDGPU_GEM_DOMAIN_GTT; 1550 } 1551 return domain; 1552 } 1553 1554 #if defined(CONFIG_DEBUG_FS) 1555 #define amdgpu_bo_print_flag(m, bo, flag) \ 1556 do { \ 1557 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1558 seq_printf((m), " " #flag); \ 1559 } \ 1560 } while (0) 1561 1562 /** 1563 * amdgpu_bo_print_info - print BO info in debugfs file 1564 * 1565 * @id: Index or Id of the BO 1566 * @bo: Requested BO for printing info 1567 * @m: debugfs file 1568 * 1569 * Print BO information in debugfs file 1570 * 1571 * Returns: 1572 * Size of the BO in bytes. 1573 */ 1574 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1575 { 1576 struct dma_buf_attachment *attachment; 1577 struct dma_buf *dma_buf; 1578 unsigned int domain; 1579 const char *placement; 1580 unsigned int pin_count; 1581 u64 size; 1582 1583 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1584 switch (domain) { 1585 case AMDGPU_GEM_DOMAIN_VRAM: 1586 placement = "VRAM"; 1587 break; 1588 case AMDGPU_GEM_DOMAIN_GTT: 1589 placement = " GTT"; 1590 break; 1591 case AMDGPU_GEM_DOMAIN_CPU: 1592 default: 1593 placement = " CPU"; 1594 break; 1595 } 1596 1597 size = amdgpu_bo_size(bo); 1598 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1599 id, size, placement); 1600 1601 pin_count = READ_ONCE(bo->tbo.pin_count); 1602 if (pin_count) 1603 seq_printf(m, " pin count %d", pin_count); 1604 1605 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1606 attachment = READ_ONCE(bo->tbo.base.import_attach); 1607 1608 if (attachment) 1609 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino); 1610 else if (dma_buf) 1611 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino); 1612 1613 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1614 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1615 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1616 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1617 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1618 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1619 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1620 1621 seq_puts(m, "\n"); 1622 1623 return size; 1624 } 1625 #endif 1626