1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * DOC: amdgpu_object 43 * 44 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 45 * represents memory used by driver (VRAM, system memory, etc.). The driver 46 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 47 * to create/destroy/set buffer object which are then managed by the kernel TTM 48 * memory manager. 49 * The interfaces are also used internally by kernel clients, including gfx, 50 * uvd, etc. for kernel managed allocations used by the GPU. 51 * 52 */ 53 54 /** 55 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 56 * 57 * @bo: &amdgpu_bo buffer object 58 * 59 * This function is called when a BO stops being pinned, and updates the 60 * &amdgpu_device pin_size values accordingly. 61 */ 62 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 63 { 64 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 65 66 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 67 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 68 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 69 &adev->visible_pin_size); 70 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 71 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 72 } 73 } 74 75 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 76 { 77 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 78 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 79 80 if (bo->pin_count > 0) 81 amdgpu_bo_subtract_pin_size(bo); 82 83 if (bo->kfd_bo) 84 amdgpu_amdkfd_unreserve_memory_limit(bo); 85 86 amdgpu_bo_kunmap(bo); 87 88 if (bo->gem_base.import_attach) 89 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); 90 drm_gem_object_release(&bo->gem_base); 91 amdgpu_bo_unref(&bo->parent); 92 if (!list_empty(&bo->shadow_list)) { 93 mutex_lock(&adev->shadow_list_lock); 94 list_del_init(&bo->shadow_list); 95 mutex_unlock(&adev->shadow_list_lock); 96 } 97 kfree(bo->metadata); 98 kfree(bo); 99 } 100 101 /** 102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 103 * @bo: buffer object to be checked 104 * 105 * Uses destroy function associated with the object to determine if this is 106 * an &amdgpu_bo. 107 * 108 * Returns: 109 * true if the object belongs to &amdgpu_bo, false if not. 110 */ 111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 112 { 113 if (bo->destroy == &amdgpu_bo_destroy) 114 return true; 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 137 places[c].fpfn = 0; 138 places[c].lpfn = 0; 139 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 140 TTM_PL_FLAG_VRAM; 141 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 places[c].lpfn = visible_pfn; 144 else 145 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 146 147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 149 c++; 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 places[c].fpfn = 0; 154 places[c].lpfn = 0; 155 places[c].flags = TTM_PL_FLAG_TT; 156 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 157 places[c].flags |= TTM_PL_FLAG_WC | 158 TTM_PL_FLAG_UNCACHED; 159 else 160 places[c].flags |= TTM_PL_FLAG_CACHED; 161 c++; 162 } 163 164 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 165 places[c].fpfn = 0; 166 places[c].lpfn = 0; 167 places[c].flags = TTM_PL_FLAG_SYSTEM; 168 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 169 places[c].flags |= TTM_PL_FLAG_WC | 170 TTM_PL_FLAG_UNCACHED; 171 else 172 places[c].flags |= TTM_PL_FLAG_CACHED; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 180 c++; 181 } 182 183 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 184 places[c].fpfn = 0; 185 places[c].lpfn = 0; 186 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 187 c++; 188 } 189 190 if (domain & AMDGPU_GEM_DOMAIN_OA) { 191 places[c].fpfn = 0; 192 places[c].lpfn = 0; 193 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 194 c++; 195 } 196 197 if (!c) { 198 places[c].fpfn = 0; 199 places[c].lpfn = 0; 200 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 201 c++; 202 } 203 204 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 205 206 placement->num_placement = c; 207 placement->placement = places; 208 209 placement->num_busy_placement = c; 210 placement->busy_placement = places; 211 } 212 213 /** 214 * amdgpu_bo_create_reserved - create reserved BO for kernel use 215 * 216 * @adev: amdgpu device object 217 * @size: size for the new BO 218 * @align: alignment for the new BO 219 * @domain: where to place it 220 * @bo_ptr: used to initialize BOs in structures 221 * @gpu_addr: GPU addr of the pinned BO 222 * @cpu_addr: optional CPU address mapping 223 * 224 * Allocates and pins a BO for kernel internal use, and returns it still 225 * reserved. 226 * 227 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 228 * 229 * Returns: 230 * 0 on success, negative error code otherwise. 231 */ 232 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 233 unsigned long size, int align, 234 u32 domain, struct amdgpu_bo **bo_ptr, 235 u64 *gpu_addr, void **cpu_addr) 236 { 237 struct amdgpu_bo_param bp; 238 bool free = false; 239 int r; 240 241 if (!size) { 242 amdgpu_bo_unref(bo_ptr); 243 return 0; 244 } 245 246 memset(&bp, 0, sizeof(bp)); 247 bp.size = size; 248 bp.byte_align = align; 249 bp.domain = domain; 250 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 251 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 252 bp.type = ttm_bo_type_kernel; 253 bp.resv = NULL; 254 255 if (!*bo_ptr) { 256 r = amdgpu_bo_create(adev, &bp, bo_ptr); 257 if (r) { 258 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 259 r); 260 return r; 261 } 262 free = true; 263 } 264 265 r = amdgpu_bo_reserve(*bo_ptr, false); 266 if (r) { 267 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 268 goto error_free; 269 } 270 271 r = amdgpu_bo_pin(*bo_ptr, domain); 272 if (r) { 273 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 274 goto error_unreserve; 275 } 276 277 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 278 if (r) { 279 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 280 goto error_unpin; 281 } 282 283 if (gpu_addr) 284 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 285 286 if (cpu_addr) { 287 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 288 if (r) { 289 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 290 goto error_unpin; 291 } 292 } 293 294 return 0; 295 296 error_unpin: 297 amdgpu_bo_unpin(*bo_ptr); 298 error_unreserve: 299 amdgpu_bo_unreserve(*bo_ptr); 300 301 error_free: 302 if (free) 303 amdgpu_bo_unref(bo_ptr); 304 305 return r; 306 } 307 308 /** 309 * amdgpu_bo_create_kernel - create BO for kernel use 310 * 311 * @adev: amdgpu device object 312 * @size: size for the new BO 313 * @align: alignment for the new BO 314 * @domain: where to place it 315 * @bo_ptr: used to initialize BOs in structures 316 * @gpu_addr: GPU addr of the pinned BO 317 * @cpu_addr: optional CPU address mapping 318 * 319 * Allocates and pins a BO for kernel internal use. 320 * 321 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 322 * 323 * Returns: 324 * 0 on success, negative error code otherwise. 325 */ 326 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 327 unsigned long size, int align, 328 u32 domain, struct amdgpu_bo **bo_ptr, 329 u64 *gpu_addr, void **cpu_addr) 330 { 331 int r; 332 333 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 334 gpu_addr, cpu_addr); 335 336 if (r) 337 return r; 338 339 if (*bo_ptr) 340 amdgpu_bo_unreserve(*bo_ptr); 341 342 return 0; 343 } 344 345 /** 346 * amdgpu_bo_free_kernel - free BO for kernel use 347 * 348 * @bo: amdgpu BO to free 349 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 350 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 351 * 352 * unmaps and unpin a BO for kernel internal use. 353 */ 354 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 355 void **cpu_addr) 356 { 357 if (*bo == NULL) 358 return; 359 360 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 361 if (cpu_addr) 362 amdgpu_bo_kunmap(*bo); 363 364 amdgpu_bo_unpin(*bo); 365 amdgpu_bo_unreserve(*bo); 366 } 367 amdgpu_bo_unref(bo); 368 369 if (gpu_addr) 370 *gpu_addr = 0; 371 372 if (cpu_addr) 373 *cpu_addr = NULL; 374 } 375 376 /* Validate bo size is bit bigger then the request domain */ 377 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 378 unsigned long size, u32 domain) 379 { 380 struct ttm_mem_type_manager *man = NULL; 381 382 /* 383 * If GTT is part of requested domains the check must succeed to 384 * allow fall back to GTT 385 */ 386 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 387 man = &adev->mman.bdev.man[TTM_PL_TT]; 388 389 if (size < (man->size << PAGE_SHIFT)) 390 return true; 391 else 392 goto fail; 393 } 394 395 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 396 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 397 398 if (size < (man->size << PAGE_SHIFT)) 399 return true; 400 else 401 goto fail; 402 } 403 404 405 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 406 return true; 407 408 fail: 409 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 410 man->size << PAGE_SHIFT); 411 return false; 412 } 413 414 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 415 struct amdgpu_bo_param *bp, 416 struct amdgpu_bo **bo_ptr) 417 { 418 struct ttm_operation_ctx ctx = { 419 .interruptible = (bp->type != ttm_bo_type_kernel), 420 .no_wait_gpu = false, 421 .resv = bp->resv, 422 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT 423 }; 424 struct amdgpu_bo *bo; 425 unsigned long page_align, size = bp->size; 426 size_t acc_size; 427 int r; 428 429 page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 430 if (bp->domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | 431 AMDGPU_GEM_DOMAIN_OA)) 432 size <<= PAGE_SHIFT; 433 else 434 size = ALIGN(size, PAGE_SIZE); 435 436 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 437 return -ENOMEM; 438 439 *bo_ptr = NULL; 440 441 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 442 sizeof(struct amdgpu_bo)); 443 444 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 445 if (bo == NULL) 446 return -ENOMEM; 447 drm_gem_private_object_init(adev->ddev, &bo->gem_base, size); 448 INIT_LIST_HEAD(&bo->shadow_list); 449 bo->vm_bo = NULL; 450 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 451 bp->domain; 452 bo->allowed_domains = bo->preferred_domains; 453 if (bp->type != ttm_bo_type_kernel && 454 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 455 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 456 457 bo->flags = bp->flags; 458 459 #ifdef CONFIG_X86_32 460 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 461 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 462 */ 463 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 464 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 465 /* Don't try to enable write-combining when it can't work, or things 466 * may be slow 467 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 468 */ 469 470 #ifndef CONFIG_COMPILE_TEST 471 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 472 thanks to write-combining 473 #endif 474 475 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 476 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 477 "better performance thanks to write-combining\n"); 478 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 479 #else 480 /* For architectures that don't support WC memory, 481 * mask out the WC flag from the BO 482 */ 483 if (!drm_arch_can_wc_memory()) 484 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 485 #endif 486 487 bo->tbo.bdev = &adev->mman.bdev; 488 amdgpu_bo_placement_from_domain(bo, bp->domain); 489 if (bp->type == ttm_bo_type_kernel) 490 bo->tbo.priority = 1; 491 492 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 493 &bo->placement, page_align, &ctx, acc_size, 494 NULL, bp->resv, &amdgpu_bo_destroy); 495 if (unlikely(r != 0)) 496 return r; 497 498 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 499 bo->tbo.mem.mem_type == TTM_PL_VRAM && 500 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 501 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 502 ctx.bytes_moved); 503 else 504 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 505 506 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 507 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 508 struct dma_fence *fence; 509 510 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); 511 if (unlikely(r)) 512 goto fail_unreserve; 513 514 amdgpu_bo_fence(bo, fence, false); 515 dma_fence_put(bo->tbo.moving); 516 bo->tbo.moving = dma_fence_get(fence); 517 dma_fence_put(fence); 518 } 519 if (!bp->resv) 520 amdgpu_bo_unreserve(bo); 521 *bo_ptr = bo; 522 523 trace_amdgpu_bo_create(bo); 524 525 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 526 if (bp->type == ttm_bo_type_device) 527 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 528 529 return 0; 530 531 fail_unreserve: 532 if (!bp->resv) 533 ww_mutex_unlock(&bo->tbo.resv->lock); 534 amdgpu_bo_unref(&bo); 535 return r; 536 } 537 538 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 539 unsigned long size, 540 struct amdgpu_bo *bo) 541 { 542 struct amdgpu_bo_param bp; 543 int r; 544 545 if (bo->shadow) 546 return 0; 547 548 memset(&bp, 0, sizeof(bp)); 549 bp.size = size; 550 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 551 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 552 AMDGPU_GEM_CREATE_SHADOW; 553 bp.type = ttm_bo_type_kernel; 554 bp.resv = bo->tbo.resv; 555 556 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 557 if (!r) { 558 bo->shadow->parent = amdgpu_bo_ref(bo); 559 mutex_lock(&adev->shadow_list_lock); 560 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 561 mutex_unlock(&adev->shadow_list_lock); 562 } 563 564 return r; 565 } 566 567 /** 568 * amdgpu_bo_create - create an &amdgpu_bo buffer object 569 * @adev: amdgpu device object 570 * @bp: parameters to be used for the buffer object 571 * @bo_ptr: pointer to the buffer object pointer 572 * 573 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 574 * shadow object. 575 * Shadow object is used to backup the original buffer object, and is always 576 * in GTT. 577 * 578 * Returns: 579 * 0 for success or a negative error code on failure. 580 */ 581 int amdgpu_bo_create(struct amdgpu_device *adev, 582 struct amdgpu_bo_param *bp, 583 struct amdgpu_bo **bo_ptr) 584 { 585 u64 flags = bp->flags; 586 int r; 587 588 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 589 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 590 if (r) 591 return r; 592 593 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 594 if (!bp->resv) 595 WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv, 596 NULL)); 597 598 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 599 600 if (!bp->resv) 601 reservation_object_unlock((*bo_ptr)->tbo.resv); 602 603 if (r) 604 amdgpu_bo_unref(bo_ptr); 605 } 606 607 return r; 608 } 609 610 /** 611 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 612 * @bo: pointer to the buffer object 613 * 614 * Sets placement according to domain; and changes placement and caching 615 * policy of the buffer object according to the placement. 616 * This is used for validating shadow bos. It calls ttm_bo_validate() to 617 * make sure the buffer is resident where it needs to be. 618 * 619 * Returns: 620 * 0 for success or a negative error code on failure. 621 */ 622 int amdgpu_bo_validate(struct amdgpu_bo *bo) 623 { 624 struct ttm_operation_ctx ctx = { false, false }; 625 uint32_t domain; 626 int r; 627 628 if (bo->pin_count) 629 return 0; 630 631 domain = bo->preferred_domains; 632 633 retry: 634 amdgpu_bo_placement_from_domain(bo, domain); 635 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 636 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 637 domain = bo->allowed_domains; 638 goto retry; 639 } 640 641 return r; 642 } 643 644 /** 645 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 646 * 647 * @shadow: &amdgpu_bo shadow to be restored 648 * @fence: dma_fence associated with the operation 649 * 650 * Copies a buffer object's shadow content back to the object. 651 * This is used for recovering a buffer from its shadow in case of a gpu 652 * reset where vram context may be lost. 653 * 654 * Returns: 655 * 0 for success or a negative error code on failure. 656 */ 657 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 658 659 { 660 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 661 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 662 uint64_t shadow_addr, parent_addr; 663 664 shadow_addr = amdgpu_bo_gpu_offset(shadow); 665 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 666 667 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 668 amdgpu_bo_size(shadow), NULL, fence, 669 true, false); 670 } 671 672 /** 673 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 674 * @bo: &amdgpu_bo buffer object to be mapped 675 * @ptr: kernel virtual address to be returned 676 * 677 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 678 * amdgpu_bo_kptr() to get the kernel virtual address. 679 * 680 * Returns: 681 * 0 for success or a negative error code on failure. 682 */ 683 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 684 { 685 void *kptr; 686 long r; 687 688 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 689 return -EPERM; 690 691 kptr = amdgpu_bo_kptr(bo); 692 if (kptr) { 693 if (ptr) 694 *ptr = kptr; 695 return 0; 696 } 697 698 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 699 MAX_SCHEDULE_TIMEOUT); 700 if (r < 0) 701 return r; 702 703 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 704 if (r) 705 return r; 706 707 if (ptr) 708 *ptr = amdgpu_bo_kptr(bo); 709 710 return 0; 711 } 712 713 /** 714 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 715 * @bo: &amdgpu_bo buffer object 716 * 717 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 718 * 719 * Returns: 720 * the virtual address of a buffer object area. 721 */ 722 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 723 { 724 bool is_iomem; 725 726 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 727 } 728 729 /** 730 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 731 * @bo: &amdgpu_bo buffer object to be unmapped 732 * 733 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 734 */ 735 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 736 { 737 if (bo->kmap.bo) 738 ttm_bo_kunmap(&bo->kmap); 739 } 740 741 /** 742 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 743 * @bo: &amdgpu_bo buffer object 744 * 745 * References the contained &ttm_buffer_object. 746 * 747 * Returns: 748 * a refcounted pointer to the &amdgpu_bo buffer object. 749 */ 750 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 751 { 752 if (bo == NULL) 753 return NULL; 754 755 ttm_bo_get(&bo->tbo); 756 return bo; 757 } 758 759 /** 760 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 761 * @bo: &amdgpu_bo buffer object 762 * 763 * Unreferences the contained &ttm_buffer_object and clear the pointer 764 */ 765 void amdgpu_bo_unref(struct amdgpu_bo **bo) 766 { 767 struct ttm_buffer_object *tbo; 768 769 if ((*bo) == NULL) 770 return; 771 772 tbo = &((*bo)->tbo); 773 ttm_bo_put(tbo); 774 *bo = NULL; 775 } 776 777 /** 778 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 779 * @bo: &amdgpu_bo buffer object to be pinned 780 * @domain: domain to be pinned to 781 * @min_offset: the start of requested address range 782 * @max_offset: the end of requested address range 783 * 784 * Pins the buffer object according to requested domain and address range. If 785 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 786 * pin_count and pin_size accordingly. 787 * 788 * Pinning means to lock pages in memory along with keeping them at a fixed 789 * offset. It is required when a buffer can not be moved, for example, when 790 * a display buffer is being scanned out. 791 * 792 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 793 * where to pin a buffer if there are specific restrictions on where a buffer 794 * must be located. 795 * 796 * Returns: 797 * 0 for success or a negative error code on failure. 798 */ 799 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 800 u64 min_offset, u64 max_offset) 801 { 802 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 803 struct ttm_operation_ctx ctx = { false, false }; 804 int r, i; 805 806 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 807 return -EPERM; 808 809 if (WARN_ON_ONCE(min_offset > max_offset)) 810 return -EINVAL; 811 812 /* A shared bo cannot be migrated to VRAM */ 813 if (bo->prime_shared_count) { 814 if (domain & AMDGPU_GEM_DOMAIN_GTT) 815 domain = AMDGPU_GEM_DOMAIN_GTT; 816 else 817 return -EINVAL; 818 } 819 820 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 821 * See function amdgpu_display_supported_domains() 822 */ 823 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 824 825 if (bo->pin_count) { 826 uint32_t mem_type = bo->tbo.mem.mem_type; 827 828 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 829 return -EINVAL; 830 831 bo->pin_count++; 832 833 if (max_offset != 0) { 834 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 835 WARN_ON_ONCE(max_offset < 836 (amdgpu_bo_gpu_offset(bo) - domain_start)); 837 } 838 839 return 0; 840 } 841 842 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 843 /* force to pin into visible video ram */ 844 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 845 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 846 amdgpu_bo_placement_from_domain(bo, domain); 847 for (i = 0; i < bo->placement.num_placement; i++) { 848 unsigned fpfn, lpfn; 849 850 fpfn = min_offset >> PAGE_SHIFT; 851 lpfn = max_offset >> PAGE_SHIFT; 852 853 if (fpfn > bo->placements[i].fpfn) 854 bo->placements[i].fpfn = fpfn; 855 if (!bo->placements[i].lpfn || 856 (lpfn && lpfn < bo->placements[i].lpfn)) 857 bo->placements[i].lpfn = lpfn; 858 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 859 } 860 861 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 862 if (unlikely(r)) { 863 dev_err(adev->dev, "%p pin failed\n", bo); 864 goto error; 865 } 866 867 bo->pin_count = 1; 868 869 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 870 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 871 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 872 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 873 &adev->visible_pin_size); 874 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 875 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 876 } 877 878 error: 879 return r; 880 } 881 882 /** 883 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 884 * @bo: &amdgpu_bo buffer object to be pinned 885 * @domain: domain to be pinned to 886 * 887 * A simple wrapper to amdgpu_bo_pin_restricted(). 888 * Provides a simpler API for buffers that do not have any strict restrictions 889 * on where a buffer must be located. 890 * 891 * Returns: 892 * 0 for success or a negative error code on failure. 893 */ 894 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 895 { 896 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 897 } 898 899 /** 900 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 901 * @bo: &amdgpu_bo buffer object to be unpinned 902 * 903 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 904 * Changes placement and pin size accordingly. 905 * 906 * Returns: 907 * 0 for success or a negative error code on failure. 908 */ 909 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 910 { 911 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 912 struct ttm_operation_ctx ctx = { false, false }; 913 int r, i; 914 915 if (WARN_ON_ONCE(!bo->pin_count)) { 916 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 917 return 0; 918 } 919 bo->pin_count--; 920 if (bo->pin_count) 921 return 0; 922 923 amdgpu_bo_subtract_pin_size(bo); 924 925 for (i = 0; i < bo->placement.num_placement; i++) { 926 bo->placements[i].lpfn = 0; 927 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 928 } 929 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 930 if (unlikely(r)) 931 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 932 933 return r; 934 } 935 936 /** 937 * amdgpu_bo_evict_vram - evict VRAM buffers 938 * @adev: amdgpu device object 939 * 940 * Evicts all VRAM buffers on the lru list of the memory type. 941 * Mainly used for evicting vram at suspend time. 942 * 943 * Returns: 944 * 0 for success or a negative error code on failure. 945 */ 946 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 947 { 948 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 949 #ifndef CONFIG_HIBERNATION 950 if (adev->flags & AMD_IS_APU) { 951 /* Useless to evict on IGP chips */ 952 return 0; 953 } 954 #endif 955 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 956 } 957 958 static const char *amdgpu_vram_names[] = { 959 "UNKNOWN", 960 "GDDR1", 961 "DDR2", 962 "GDDR3", 963 "GDDR4", 964 "GDDR5", 965 "HBM", 966 "DDR3", 967 "DDR4", 968 }; 969 970 /** 971 * amdgpu_bo_init - initialize memory manager 972 * @adev: amdgpu device object 973 * 974 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 975 * 976 * Returns: 977 * 0 for success or a negative error code on failure. 978 */ 979 int amdgpu_bo_init(struct amdgpu_device *adev) 980 { 981 /* reserve PAT memory space to WC for VRAM */ 982 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 983 adev->gmc.aper_size); 984 985 /* Add an MTRR for the VRAM */ 986 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 987 adev->gmc.aper_size); 988 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 989 adev->gmc.mc_vram_size >> 20, 990 (unsigned long long)adev->gmc.aper_size >> 20); 991 DRM_INFO("RAM width %dbits %s\n", 992 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 993 return amdgpu_ttm_init(adev); 994 } 995 996 /** 997 * amdgpu_bo_late_init - late init 998 * @adev: amdgpu device object 999 * 1000 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1001 * initialization. 1002 * 1003 * Returns: 1004 * 0 for success or a negative error code on failure. 1005 */ 1006 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1007 { 1008 amdgpu_ttm_late_init(adev); 1009 1010 return 0; 1011 } 1012 1013 /** 1014 * amdgpu_bo_fini - tear down memory manager 1015 * @adev: amdgpu device object 1016 * 1017 * Reverses amdgpu_bo_init() to tear down memory manager. 1018 */ 1019 void amdgpu_bo_fini(struct amdgpu_device *adev) 1020 { 1021 amdgpu_ttm_fini(adev); 1022 arch_phys_wc_del(adev->gmc.vram_mtrr); 1023 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1024 } 1025 1026 /** 1027 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1028 * @bo: &amdgpu_bo buffer object 1029 * @vma: vma as input from the fbdev mmap method 1030 * 1031 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1032 * 1033 * Returns: 1034 * 0 for success or a negative error code on failure. 1035 */ 1036 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1037 struct vm_area_struct *vma) 1038 { 1039 return ttm_fbdev_mmap(vma, &bo->tbo); 1040 } 1041 1042 /** 1043 * amdgpu_bo_set_tiling_flags - set tiling flags 1044 * @bo: &amdgpu_bo buffer object 1045 * @tiling_flags: new flags 1046 * 1047 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1048 * kernel driver to set the tiling flags on a buffer. 1049 * 1050 * Returns: 1051 * 0 for success or a negative error code on failure. 1052 */ 1053 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1054 { 1055 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1056 1057 if (adev->family <= AMDGPU_FAMILY_CZ && 1058 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1059 return -EINVAL; 1060 1061 bo->tiling_flags = tiling_flags; 1062 return 0; 1063 } 1064 1065 /** 1066 * amdgpu_bo_get_tiling_flags - get tiling flags 1067 * @bo: &amdgpu_bo buffer object 1068 * @tiling_flags: returned flags 1069 * 1070 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1071 * set the tiling flags on a buffer. 1072 */ 1073 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1074 { 1075 lockdep_assert_held(&bo->tbo.resv->lock.base); 1076 1077 if (tiling_flags) 1078 *tiling_flags = bo->tiling_flags; 1079 } 1080 1081 /** 1082 * amdgpu_bo_set_metadata - set metadata 1083 * @bo: &amdgpu_bo buffer object 1084 * @metadata: new metadata 1085 * @metadata_size: size of the new metadata 1086 * @flags: flags of the new metadata 1087 * 1088 * Sets buffer object's metadata, its size and flags. 1089 * Used via GEM ioctl. 1090 * 1091 * Returns: 1092 * 0 for success or a negative error code on failure. 1093 */ 1094 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1095 uint32_t metadata_size, uint64_t flags) 1096 { 1097 void *buffer; 1098 1099 if (!metadata_size) { 1100 if (bo->metadata_size) { 1101 kfree(bo->metadata); 1102 bo->metadata = NULL; 1103 bo->metadata_size = 0; 1104 } 1105 return 0; 1106 } 1107 1108 if (metadata == NULL) 1109 return -EINVAL; 1110 1111 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1112 if (buffer == NULL) 1113 return -ENOMEM; 1114 1115 kfree(bo->metadata); 1116 bo->metadata_flags = flags; 1117 bo->metadata = buffer; 1118 bo->metadata_size = metadata_size; 1119 1120 return 0; 1121 } 1122 1123 /** 1124 * amdgpu_bo_get_metadata - get metadata 1125 * @bo: &amdgpu_bo buffer object 1126 * @buffer: returned metadata 1127 * @buffer_size: size of the buffer 1128 * @metadata_size: size of the returned metadata 1129 * @flags: flags of the returned metadata 1130 * 1131 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1132 * less than metadata_size. 1133 * Used via GEM ioctl. 1134 * 1135 * Returns: 1136 * 0 for success or a negative error code on failure. 1137 */ 1138 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1139 size_t buffer_size, uint32_t *metadata_size, 1140 uint64_t *flags) 1141 { 1142 if (!buffer && !metadata_size) 1143 return -EINVAL; 1144 1145 if (buffer) { 1146 if (buffer_size < bo->metadata_size) 1147 return -EINVAL; 1148 1149 if (bo->metadata_size) 1150 memcpy(buffer, bo->metadata, bo->metadata_size); 1151 } 1152 1153 if (metadata_size) 1154 *metadata_size = bo->metadata_size; 1155 if (flags) 1156 *flags = bo->metadata_flags; 1157 1158 return 0; 1159 } 1160 1161 /** 1162 * amdgpu_bo_move_notify - notification about a memory move 1163 * @bo: pointer to a buffer object 1164 * @evict: if this move is evicting the buffer from the graphics address space 1165 * @new_mem: new information of the bufer object 1166 * 1167 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1168 * bookkeeping. 1169 * TTM driver callback which is called when ttm moves a buffer. 1170 */ 1171 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1172 bool evict, 1173 struct ttm_mem_reg *new_mem) 1174 { 1175 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1176 struct amdgpu_bo *abo; 1177 struct ttm_mem_reg *old_mem = &bo->mem; 1178 1179 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1180 return; 1181 1182 abo = ttm_to_amdgpu_bo(bo); 1183 amdgpu_vm_bo_invalidate(adev, abo, evict); 1184 1185 amdgpu_bo_kunmap(abo); 1186 1187 /* remember the eviction */ 1188 if (evict) 1189 atomic64_inc(&adev->num_evictions); 1190 1191 /* update statistics */ 1192 if (!new_mem) 1193 return; 1194 1195 /* move_notify is called before move happens */ 1196 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1197 } 1198 1199 /** 1200 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1201 * @bo: pointer to a buffer object 1202 * 1203 * Notifies the driver we are taking a fault on this BO and have reserved it, 1204 * also performs bookkeeping. 1205 * TTM driver callback for dealing with vm faults. 1206 * 1207 * Returns: 1208 * 0 for success or a negative error code on failure. 1209 */ 1210 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1211 { 1212 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1213 struct ttm_operation_ctx ctx = { false, false }; 1214 struct amdgpu_bo *abo; 1215 unsigned long offset, size; 1216 int r; 1217 1218 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1219 return 0; 1220 1221 abo = ttm_to_amdgpu_bo(bo); 1222 1223 /* Remember that this BO was accessed by the CPU */ 1224 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1225 1226 if (bo->mem.mem_type != TTM_PL_VRAM) 1227 return 0; 1228 1229 size = bo->mem.num_pages << PAGE_SHIFT; 1230 offset = bo->mem.start << PAGE_SHIFT; 1231 if ((offset + size) <= adev->gmc.visible_vram_size) 1232 return 0; 1233 1234 /* Can't move a pinned BO to visible VRAM */ 1235 if (abo->pin_count > 0) 1236 return -EINVAL; 1237 1238 /* hurrah the memory is not visible ! */ 1239 atomic64_inc(&adev->num_vram_cpu_page_faults); 1240 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1241 AMDGPU_GEM_DOMAIN_GTT); 1242 1243 /* Avoid costly evictions; only set GTT as a busy placement */ 1244 abo->placement.num_busy_placement = 1; 1245 abo->placement.busy_placement = &abo->placements[1]; 1246 1247 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1248 if (unlikely(r != 0)) 1249 return r; 1250 1251 offset = bo->mem.start << PAGE_SHIFT; 1252 /* this should never happen */ 1253 if (bo->mem.mem_type == TTM_PL_VRAM && 1254 (offset + size) > adev->gmc.visible_vram_size) 1255 return -EINVAL; 1256 1257 return 0; 1258 } 1259 1260 /** 1261 * amdgpu_bo_fence - add fence to buffer object 1262 * 1263 * @bo: buffer object in question 1264 * @fence: fence to add 1265 * @shared: true if fence should be added shared 1266 * 1267 */ 1268 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1269 bool shared) 1270 { 1271 struct reservation_object *resv = bo->tbo.resv; 1272 1273 if (shared) 1274 reservation_object_add_shared_fence(resv, fence); 1275 else 1276 reservation_object_add_excl_fence(resv, fence); 1277 } 1278 1279 /** 1280 * amdgpu_bo_gpu_offset - return GPU offset of bo 1281 * @bo: amdgpu object for which we query the offset 1282 * 1283 * Note: object should either be pinned or reserved when calling this 1284 * function, it might be useful to add check for this for debugging. 1285 * 1286 * Returns: 1287 * current GPU offset of the object. 1288 */ 1289 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1290 { 1291 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1292 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 1293 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); 1294 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1295 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1296 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1297 1298 return amdgpu_gmc_sign_extend(bo->tbo.offset); 1299 } 1300 1301 /** 1302 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1303 * @adev: amdgpu device object 1304 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1305 * 1306 * Returns: 1307 * Which of the allowed domains is preferred for pinning the BO for scanout. 1308 */ 1309 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1310 uint32_t domain) 1311 { 1312 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1313 domain = AMDGPU_GEM_DOMAIN_VRAM; 1314 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1315 domain = AMDGPU_GEM_DOMAIN_GTT; 1316 } 1317 return domain; 1318 } 1319