1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 59 60 amdgpu_bo_kunmap(bo); 61 62 if (bo->tbo.base.import_attach) 63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 64 drm_gem_object_release(&bo->tbo.base); 65 amdgpu_bo_unref(&bo->parent); 66 kvfree(bo); 67 } 68 69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 70 { 71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 72 struct amdgpu_bo_user *ubo; 73 74 ubo = to_amdgpu_bo_user(bo); 75 kfree(ubo->metadata); 76 amdgpu_bo_destroy(tbo); 77 } 78 79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 82 struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; 83 struct amdgpu_bo_vm *vmbo; 84 85 bo = shadow_bo->parent; 86 vmbo = to_amdgpu_bo_vm(bo); 87 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 88 if (!list_empty(&vmbo->shadow_list)) { 89 mutex_lock(&adev->shadow_list_lock); 90 list_del_init(&vmbo->shadow_list); 91 mutex_unlock(&adev->shadow_list_lock); 92 } 93 94 amdgpu_bo_destroy(tbo); 95 } 96 97 /** 98 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 99 * @bo: buffer object to be checked 100 * 101 * Uses destroy function associated with the object to determine if this is 102 * an &amdgpu_bo. 103 * 104 * Returns: 105 * true if the object belongs to &amdgpu_bo, false if not. 106 */ 107 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 108 { 109 if (bo->destroy == &amdgpu_bo_destroy || 110 bo->destroy == &amdgpu_bo_user_destroy || 111 bo->destroy == &amdgpu_bo_vm_destroy) 112 return true; 113 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 136 places[c].fpfn = 0; 137 places[c].lpfn = 0; 138 places[c].mem_type = TTM_PL_VRAM; 139 places[c].flags = 0; 140 141 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 142 places[c].lpfn = visible_pfn; 143 else 144 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 145 146 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 147 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 148 c++; 149 } 150 151 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 152 places[c].fpfn = 0; 153 places[c].lpfn = 0; 154 places[c].mem_type = 155 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 156 AMDGPU_PL_PREEMPT : TTM_PL_TT; 157 places[c].flags = 0; 158 c++; 159 } 160 161 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 162 places[c].fpfn = 0; 163 places[c].lpfn = 0; 164 places[c].mem_type = TTM_PL_SYSTEM; 165 places[c].flags = 0; 166 c++; 167 } 168 169 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 170 places[c].fpfn = 0; 171 places[c].lpfn = 0; 172 places[c].mem_type = AMDGPU_PL_GDS; 173 places[c].flags = 0; 174 c++; 175 } 176 177 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 178 places[c].fpfn = 0; 179 places[c].lpfn = 0; 180 places[c].mem_type = AMDGPU_PL_GWS; 181 places[c].flags = 0; 182 c++; 183 } 184 185 if (domain & AMDGPU_GEM_DOMAIN_OA) { 186 places[c].fpfn = 0; 187 places[c].lpfn = 0; 188 places[c].mem_type = AMDGPU_PL_OA; 189 places[c].flags = 0; 190 c++; 191 } 192 193 if (!c) { 194 places[c].fpfn = 0; 195 places[c].lpfn = 0; 196 places[c].mem_type = TTM_PL_SYSTEM; 197 places[c].flags = 0; 198 c++; 199 } 200 201 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 202 203 placement->num_placement = c; 204 placement->placement = places; 205 206 placement->num_busy_placement = c; 207 placement->busy_placement = places; 208 } 209 210 /** 211 * amdgpu_bo_create_reserved - create reserved BO for kernel use 212 * 213 * @adev: amdgpu device object 214 * @size: size for the new BO 215 * @align: alignment for the new BO 216 * @domain: where to place it 217 * @bo_ptr: used to initialize BOs in structures 218 * @gpu_addr: GPU addr of the pinned BO 219 * @cpu_addr: optional CPU address mapping 220 * 221 * Allocates and pins a BO for kernel internal use, and returns it still 222 * reserved. 223 * 224 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 225 * 226 * Returns: 227 * 0 on success, negative error code otherwise. 228 */ 229 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 230 unsigned long size, int align, 231 u32 domain, struct amdgpu_bo **bo_ptr, 232 u64 *gpu_addr, void **cpu_addr) 233 { 234 struct amdgpu_bo_param bp; 235 bool free = false; 236 int r; 237 238 if (!size) { 239 amdgpu_bo_unref(bo_ptr); 240 return 0; 241 } 242 243 memset(&bp, 0, sizeof(bp)); 244 bp.size = size; 245 bp.byte_align = align; 246 bp.domain = domain; 247 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 248 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 249 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 250 bp.type = ttm_bo_type_kernel; 251 bp.resv = NULL; 252 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 253 254 if (!*bo_ptr) { 255 r = amdgpu_bo_create(adev, &bp, bo_ptr); 256 if (r) { 257 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 258 r); 259 return r; 260 } 261 free = true; 262 } 263 264 r = amdgpu_bo_reserve(*bo_ptr, false); 265 if (r) { 266 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 267 goto error_free; 268 } 269 270 r = amdgpu_bo_pin(*bo_ptr, domain); 271 if (r) { 272 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 273 goto error_unreserve; 274 } 275 276 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 277 if (r) { 278 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 279 goto error_unpin; 280 } 281 282 if (gpu_addr) 283 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 284 285 if (cpu_addr) { 286 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 287 if (r) { 288 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 289 goto error_unpin; 290 } 291 } 292 293 return 0; 294 295 error_unpin: 296 amdgpu_bo_unpin(*bo_ptr); 297 error_unreserve: 298 amdgpu_bo_unreserve(*bo_ptr); 299 300 error_free: 301 if (free) 302 amdgpu_bo_unref(bo_ptr); 303 304 return r; 305 } 306 307 /** 308 * amdgpu_bo_create_kernel - create BO for kernel use 309 * 310 * @adev: amdgpu device object 311 * @size: size for the new BO 312 * @align: alignment for the new BO 313 * @domain: where to place it 314 * @bo_ptr: used to initialize BOs in structures 315 * @gpu_addr: GPU addr of the pinned BO 316 * @cpu_addr: optional CPU address mapping 317 * 318 * Allocates and pins a BO for kernel internal use. 319 * 320 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 321 * 322 * Returns: 323 * 0 on success, negative error code otherwise. 324 */ 325 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 326 unsigned long size, int align, 327 u32 domain, struct amdgpu_bo **bo_ptr, 328 u64 *gpu_addr, void **cpu_addr) 329 { 330 int r; 331 332 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 333 gpu_addr, cpu_addr); 334 335 if (r) 336 return r; 337 338 if (*bo_ptr) 339 amdgpu_bo_unreserve(*bo_ptr); 340 341 return 0; 342 } 343 344 /** 345 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 346 * 347 * @adev: amdgpu device object 348 * @offset: offset of the BO 349 * @size: size of the BO 350 * @bo_ptr: used to initialize BOs in structures 351 * @cpu_addr: optional CPU address mapping 352 * 353 * Creates a kernel BO at a specific offset in VRAM. 354 * 355 * Returns: 356 * 0 on success, negative error code otherwise. 357 */ 358 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 359 uint64_t offset, uint64_t size, 360 struct amdgpu_bo **bo_ptr, void **cpu_addr) 361 { 362 struct ttm_operation_ctx ctx = { false, false }; 363 unsigned int i; 364 int r; 365 366 offset &= PAGE_MASK; 367 size = ALIGN(size, PAGE_SIZE); 368 369 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 370 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL, 371 cpu_addr); 372 if (r) 373 return r; 374 375 if ((*bo_ptr) == NULL) 376 return 0; 377 378 /* 379 * Remove the original mem node and create a new one at the request 380 * position. 381 */ 382 if (cpu_addr) 383 amdgpu_bo_kunmap(*bo_ptr); 384 385 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 386 387 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 388 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 389 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 390 } 391 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 392 &(*bo_ptr)->tbo.resource, &ctx); 393 if (r) 394 goto error; 395 396 if (cpu_addr) { 397 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 398 if (r) 399 goto error; 400 } 401 402 amdgpu_bo_unreserve(*bo_ptr); 403 return 0; 404 405 error: 406 amdgpu_bo_unreserve(*bo_ptr); 407 amdgpu_bo_unref(bo_ptr); 408 return r; 409 } 410 411 /** 412 * amdgpu_bo_free_kernel - free BO for kernel use 413 * 414 * @bo: amdgpu BO to free 415 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 416 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 417 * 418 * unmaps and unpin a BO for kernel internal use. 419 */ 420 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 421 void **cpu_addr) 422 { 423 if (*bo == NULL) 424 return; 425 426 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend); 427 428 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 429 if (cpu_addr) 430 amdgpu_bo_kunmap(*bo); 431 432 amdgpu_bo_unpin(*bo); 433 amdgpu_bo_unreserve(*bo); 434 } 435 amdgpu_bo_unref(bo); 436 437 if (gpu_addr) 438 *gpu_addr = 0; 439 440 if (cpu_addr) 441 *cpu_addr = NULL; 442 } 443 444 /* Validate bo size is bit bigger then the request domain */ 445 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 446 unsigned long size, u32 domain) 447 { 448 struct ttm_resource_manager *man = NULL; 449 450 /* 451 * If GTT is part of requested domains the check must succeed to 452 * allow fall back to GTT. 453 */ 454 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 455 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 456 457 if (man && size < man->size) 458 return true; 459 else if (!man) 460 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 461 goto fail; 462 } else if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 463 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 464 465 if (man && size < man->size) 466 return true; 467 goto fail; 468 } 469 470 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 471 return true; 472 473 fail: 474 if (man) 475 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 476 man->size); 477 return false; 478 } 479 480 bool amdgpu_bo_support_uswc(u64 bo_flags) 481 { 482 483 #ifdef CONFIG_X86_32 484 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 485 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 486 */ 487 return false; 488 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 489 /* Don't try to enable write-combining when it can't work, or things 490 * may be slow 491 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 492 */ 493 494 #ifndef CONFIG_COMPILE_TEST 495 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 496 thanks to write-combining 497 #endif 498 499 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 500 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 501 "better performance thanks to write-combining\n"); 502 return false; 503 #else 504 /* For architectures that don't support WC memory, 505 * mask out the WC flag from the BO 506 */ 507 if (!drm_arch_can_wc_memory()) 508 return false; 509 510 return true; 511 #endif 512 } 513 514 /** 515 * amdgpu_bo_create - create an &amdgpu_bo buffer object 516 * @adev: amdgpu device object 517 * @bp: parameters to be used for the buffer object 518 * @bo_ptr: pointer to the buffer object pointer 519 * 520 * Creates an &amdgpu_bo buffer object. 521 * 522 * Returns: 523 * 0 for success or a negative error code on failure. 524 */ 525 int amdgpu_bo_create(struct amdgpu_device *adev, 526 struct amdgpu_bo_param *bp, 527 struct amdgpu_bo **bo_ptr) 528 { 529 struct ttm_operation_ctx ctx = { 530 .interruptible = (bp->type != ttm_bo_type_kernel), 531 .no_wait_gpu = bp->no_wait_gpu, 532 /* We opt to avoid OOM on system pages allocations */ 533 .gfp_retry_mayfail = true, 534 .allow_res_evict = bp->type != ttm_bo_type_kernel, 535 .resv = bp->resv 536 }; 537 struct amdgpu_bo *bo; 538 unsigned long page_align, size = bp->size; 539 int r; 540 541 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 542 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 543 /* GWS and OA don't need any alignment. */ 544 page_align = bp->byte_align; 545 size <<= PAGE_SHIFT; 546 547 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 548 /* Both size and alignment must be a multiple of 4. */ 549 page_align = ALIGN(bp->byte_align, 4); 550 size = ALIGN(size, 4) << PAGE_SHIFT; 551 } else { 552 /* Memory should be aligned at least to a page size. */ 553 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 554 size = ALIGN(size, PAGE_SIZE); 555 } 556 557 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 558 return -ENOMEM; 559 560 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 561 562 *bo_ptr = NULL; 563 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 564 if (bo == NULL) 565 return -ENOMEM; 566 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 567 bo->vm_bo = NULL; 568 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 569 bp->domain; 570 bo->allowed_domains = bo->preferred_domains; 571 if (bp->type != ttm_bo_type_kernel && 572 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 573 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 574 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 575 576 bo->flags = bp->flags; 577 578 if (!amdgpu_bo_support_uswc(bo->flags)) 579 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 580 581 if (adev->ras_enabled) 582 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 583 584 bo->tbo.bdev = &adev->mman.bdev; 585 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 586 AMDGPU_GEM_DOMAIN_GDS)) 587 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 588 else 589 amdgpu_bo_placement_from_domain(bo, bp->domain); 590 if (bp->type == ttm_bo_type_kernel) 591 bo->tbo.priority = 1; 592 593 if (!bp->destroy) 594 bp->destroy = &amdgpu_bo_destroy; 595 596 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 597 &bo->placement, page_align, &ctx, NULL, 598 bp->resv, bp->destroy); 599 if (unlikely(r != 0)) 600 return r; 601 602 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 603 bo->tbo.resource->mem_type == TTM_PL_VRAM && 604 amdgpu_bo_in_cpu_visible_vram(bo)) 605 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 606 ctx.bytes_moved); 607 else 608 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 609 610 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 611 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 612 struct dma_fence *fence; 613 614 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 615 if (unlikely(r)) 616 goto fail_unreserve; 617 618 dma_resv_add_fence(bo->tbo.base.resv, fence, 619 DMA_RESV_USAGE_KERNEL); 620 dma_fence_put(fence); 621 } 622 if (!bp->resv) 623 amdgpu_bo_unreserve(bo); 624 *bo_ptr = bo; 625 626 trace_amdgpu_bo_create(bo); 627 628 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 629 if (bp->type == ttm_bo_type_device) 630 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 631 632 return 0; 633 634 fail_unreserve: 635 if (!bp->resv) 636 dma_resv_unlock(bo->tbo.base.resv); 637 amdgpu_bo_unref(&bo); 638 return r; 639 } 640 641 /** 642 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 643 * @adev: amdgpu device object 644 * @bp: parameters to be used for the buffer object 645 * @ubo_ptr: pointer to the buffer object pointer 646 * 647 * Create a BO to be used by user application; 648 * 649 * Returns: 650 * 0 for success or a negative error code on failure. 651 */ 652 653 int amdgpu_bo_create_user(struct amdgpu_device *adev, 654 struct amdgpu_bo_param *bp, 655 struct amdgpu_bo_user **ubo_ptr) 656 { 657 struct amdgpu_bo *bo_ptr; 658 int r; 659 660 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 661 bp->destroy = &amdgpu_bo_user_destroy; 662 r = amdgpu_bo_create(adev, bp, &bo_ptr); 663 if (r) 664 return r; 665 666 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 667 return r; 668 } 669 670 /** 671 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 672 * @adev: amdgpu device object 673 * @bp: parameters to be used for the buffer object 674 * @vmbo_ptr: pointer to the buffer object pointer 675 * 676 * Create a BO to be for GPUVM. 677 * 678 * Returns: 679 * 0 for success or a negative error code on failure. 680 */ 681 682 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 683 struct amdgpu_bo_param *bp, 684 struct amdgpu_bo_vm **vmbo_ptr) 685 { 686 struct amdgpu_bo *bo_ptr; 687 int r; 688 689 /* bo_ptr_size will be determined by the caller and it depends on 690 * num of amdgpu_vm_pt entries. 691 */ 692 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 693 r = amdgpu_bo_create(adev, bp, &bo_ptr); 694 if (r) 695 return r; 696 697 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 698 return r; 699 } 700 701 /** 702 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 703 * 704 * @vmbo: BO that will be inserted into the shadow list 705 * 706 * Insert a BO to the shadow list. 707 */ 708 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 709 { 710 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 711 712 mutex_lock(&adev->shadow_list_lock); 713 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 714 vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); 715 vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; 716 mutex_unlock(&adev->shadow_list_lock); 717 } 718 719 /** 720 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 721 * 722 * @shadow: &amdgpu_bo shadow to be restored 723 * @fence: dma_fence associated with the operation 724 * 725 * Copies a buffer object's shadow content back to the object. 726 * This is used for recovering a buffer from its shadow in case of a gpu 727 * reset where vram context may be lost. 728 * 729 * Returns: 730 * 0 for success or a negative error code on failure. 731 */ 732 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 733 734 { 735 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 736 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 737 uint64_t shadow_addr, parent_addr; 738 739 shadow_addr = amdgpu_bo_gpu_offset(shadow); 740 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 741 742 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 743 amdgpu_bo_size(shadow), NULL, fence, 744 true, false, false); 745 } 746 747 /** 748 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 749 * @bo: &amdgpu_bo buffer object to be mapped 750 * @ptr: kernel virtual address to be returned 751 * 752 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 753 * amdgpu_bo_kptr() to get the kernel virtual address. 754 * 755 * Returns: 756 * 0 for success or a negative error code on failure. 757 */ 758 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 759 { 760 void *kptr; 761 long r; 762 763 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 764 return -EPERM; 765 766 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 767 false, MAX_SCHEDULE_TIMEOUT); 768 if (r < 0) 769 return r; 770 771 kptr = amdgpu_bo_kptr(bo); 772 if (kptr) { 773 if (ptr) 774 *ptr = kptr; 775 return 0; 776 } 777 778 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 779 if (r) 780 return r; 781 782 if (ptr) 783 *ptr = amdgpu_bo_kptr(bo); 784 785 return 0; 786 } 787 788 /** 789 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 790 * @bo: &amdgpu_bo buffer object 791 * 792 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 793 * 794 * Returns: 795 * the virtual address of a buffer object area. 796 */ 797 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 798 { 799 bool is_iomem; 800 801 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 802 } 803 804 /** 805 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 806 * @bo: &amdgpu_bo buffer object to be unmapped 807 * 808 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 809 */ 810 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 811 { 812 if (bo->kmap.bo) 813 ttm_bo_kunmap(&bo->kmap); 814 } 815 816 /** 817 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 818 * @bo: &amdgpu_bo buffer object 819 * 820 * References the contained &ttm_buffer_object. 821 * 822 * Returns: 823 * a refcounted pointer to the &amdgpu_bo buffer object. 824 */ 825 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 826 { 827 if (bo == NULL) 828 return NULL; 829 830 ttm_bo_get(&bo->tbo); 831 return bo; 832 } 833 834 /** 835 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 836 * @bo: &amdgpu_bo buffer object 837 * 838 * Unreferences the contained &ttm_buffer_object and clear the pointer 839 */ 840 void amdgpu_bo_unref(struct amdgpu_bo **bo) 841 { 842 struct ttm_buffer_object *tbo; 843 844 if ((*bo) == NULL) 845 return; 846 847 tbo = &((*bo)->tbo); 848 ttm_bo_put(tbo); 849 *bo = NULL; 850 } 851 852 /** 853 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 854 * @bo: &amdgpu_bo buffer object to be pinned 855 * @domain: domain to be pinned to 856 * @min_offset: the start of requested address range 857 * @max_offset: the end of requested address range 858 * 859 * Pins the buffer object according to requested domain and address range. If 860 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 861 * pin_count and pin_size accordingly. 862 * 863 * Pinning means to lock pages in memory along with keeping them at a fixed 864 * offset. It is required when a buffer can not be moved, for example, when 865 * a display buffer is being scanned out. 866 * 867 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 868 * where to pin a buffer if there are specific restrictions on where a buffer 869 * must be located. 870 * 871 * Returns: 872 * 0 for success or a negative error code on failure. 873 */ 874 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 875 u64 min_offset, u64 max_offset) 876 { 877 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 878 struct ttm_operation_ctx ctx = { false, false }; 879 int r, i; 880 881 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 882 return -EPERM; 883 884 if (WARN_ON_ONCE(min_offset > max_offset)) 885 return -EINVAL; 886 887 /* Check domain to be pinned to against preferred domains */ 888 if (bo->preferred_domains & domain) 889 domain = bo->preferred_domains & domain; 890 891 /* A shared bo cannot be migrated to VRAM */ 892 if (bo->tbo.base.import_attach) { 893 if (domain & AMDGPU_GEM_DOMAIN_GTT) 894 domain = AMDGPU_GEM_DOMAIN_GTT; 895 else 896 return -EINVAL; 897 } 898 899 if (bo->tbo.pin_count) { 900 uint32_t mem_type = bo->tbo.resource->mem_type; 901 uint32_t mem_flags = bo->tbo.resource->placement; 902 903 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 904 return -EINVAL; 905 906 if ((mem_type == TTM_PL_VRAM) && 907 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 908 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 909 return -EINVAL; 910 911 ttm_bo_pin(&bo->tbo); 912 913 if (max_offset != 0) { 914 u64 domain_start = amdgpu_ttm_domain_start(adev, 915 mem_type); 916 WARN_ON_ONCE(max_offset < 917 (amdgpu_bo_gpu_offset(bo) - domain_start)); 918 } 919 920 return 0; 921 } 922 923 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 924 * See function amdgpu_display_supported_domains() 925 */ 926 domain = amdgpu_bo_get_preferred_domain(adev, domain); 927 928 if (bo->tbo.base.import_attach) 929 dma_buf_pin(bo->tbo.base.import_attach); 930 931 /* force to pin into visible video ram */ 932 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 933 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 934 amdgpu_bo_placement_from_domain(bo, domain); 935 for (i = 0; i < bo->placement.num_placement; i++) { 936 unsigned fpfn, lpfn; 937 938 fpfn = min_offset >> PAGE_SHIFT; 939 lpfn = max_offset >> PAGE_SHIFT; 940 941 if (fpfn > bo->placements[i].fpfn) 942 bo->placements[i].fpfn = fpfn; 943 if (!bo->placements[i].lpfn || 944 (lpfn && lpfn < bo->placements[i].lpfn)) 945 bo->placements[i].lpfn = lpfn; 946 } 947 948 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 949 if (unlikely(r)) { 950 dev_err(adev->dev, "%p pin failed\n", bo); 951 goto error; 952 } 953 954 ttm_bo_pin(&bo->tbo); 955 956 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 957 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 958 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 959 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 960 &adev->visible_pin_size); 961 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 962 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 963 } 964 965 error: 966 return r; 967 } 968 969 /** 970 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 971 * @bo: &amdgpu_bo buffer object to be pinned 972 * @domain: domain to be pinned to 973 * 974 * A simple wrapper to amdgpu_bo_pin_restricted(). 975 * Provides a simpler API for buffers that do not have any strict restrictions 976 * on where a buffer must be located. 977 * 978 * Returns: 979 * 0 for success or a negative error code on failure. 980 */ 981 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 982 { 983 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 984 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 985 } 986 987 /** 988 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 989 * @bo: &amdgpu_bo buffer object to be unpinned 990 * 991 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 992 * Changes placement and pin size accordingly. 993 * 994 * Returns: 995 * 0 for success or a negative error code on failure. 996 */ 997 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 998 { 999 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1000 1001 ttm_bo_unpin(&bo->tbo); 1002 if (bo->tbo.pin_count) 1003 return; 1004 1005 if (bo->tbo.base.import_attach) 1006 dma_buf_unpin(bo->tbo.base.import_attach); 1007 1008 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1009 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1010 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1011 &adev->visible_pin_size); 1012 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1013 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1014 } 1015 } 1016 1017 static const char *amdgpu_vram_names[] = { 1018 "UNKNOWN", 1019 "GDDR1", 1020 "DDR2", 1021 "GDDR3", 1022 "GDDR4", 1023 "GDDR5", 1024 "HBM", 1025 "DDR3", 1026 "DDR4", 1027 "GDDR6", 1028 "DDR5", 1029 "LPDDR4", 1030 "LPDDR5" 1031 }; 1032 1033 /** 1034 * amdgpu_bo_init - initialize memory manager 1035 * @adev: amdgpu device object 1036 * 1037 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1038 * 1039 * Returns: 1040 * 0 for success or a negative error code on failure. 1041 */ 1042 int amdgpu_bo_init(struct amdgpu_device *adev) 1043 { 1044 /* On A+A platform, VRAM can be mapped as WB */ 1045 if (!adev->gmc.xgmi.connected_to_cpu) { 1046 /* reserve PAT memory space to WC for VRAM */ 1047 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1048 adev->gmc.aper_size); 1049 1050 if (r) { 1051 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1052 return r; 1053 } 1054 1055 /* Add an MTRR for the VRAM */ 1056 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1057 adev->gmc.aper_size); 1058 } 1059 1060 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1061 adev->gmc.mc_vram_size >> 20, 1062 (unsigned long long)adev->gmc.aper_size >> 20); 1063 DRM_INFO("RAM width %dbits %s\n", 1064 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1065 return amdgpu_ttm_init(adev); 1066 } 1067 1068 /** 1069 * amdgpu_bo_fini - tear down memory manager 1070 * @adev: amdgpu device object 1071 * 1072 * Reverses amdgpu_bo_init() to tear down memory manager. 1073 */ 1074 void amdgpu_bo_fini(struct amdgpu_device *adev) 1075 { 1076 int idx; 1077 1078 amdgpu_ttm_fini(adev); 1079 1080 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1081 1082 if (!adev->gmc.xgmi.connected_to_cpu) { 1083 arch_phys_wc_del(adev->gmc.vram_mtrr); 1084 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1085 } 1086 drm_dev_exit(idx); 1087 } 1088 } 1089 1090 /** 1091 * amdgpu_bo_set_tiling_flags - set tiling flags 1092 * @bo: &amdgpu_bo buffer object 1093 * @tiling_flags: new flags 1094 * 1095 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1096 * kernel driver to set the tiling flags on a buffer. 1097 * 1098 * Returns: 1099 * 0 for success or a negative error code on failure. 1100 */ 1101 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1102 { 1103 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1104 struct amdgpu_bo_user *ubo; 1105 1106 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1107 if (adev->family <= AMDGPU_FAMILY_CZ && 1108 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1109 return -EINVAL; 1110 1111 ubo = to_amdgpu_bo_user(bo); 1112 ubo->tiling_flags = tiling_flags; 1113 return 0; 1114 } 1115 1116 /** 1117 * amdgpu_bo_get_tiling_flags - get tiling flags 1118 * @bo: &amdgpu_bo buffer object 1119 * @tiling_flags: returned flags 1120 * 1121 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1122 * set the tiling flags on a buffer. 1123 */ 1124 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1125 { 1126 struct amdgpu_bo_user *ubo; 1127 1128 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1129 dma_resv_assert_held(bo->tbo.base.resv); 1130 ubo = to_amdgpu_bo_user(bo); 1131 1132 if (tiling_flags) 1133 *tiling_flags = ubo->tiling_flags; 1134 } 1135 1136 /** 1137 * amdgpu_bo_set_metadata - set metadata 1138 * @bo: &amdgpu_bo buffer object 1139 * @metadata: new metadata 1140 * @metadata_size: size of the new metadata 1141 * @flags: flags of the new metadata 1142 * 1143 * Sets buffer object's metadata, its size and flags. 1144 * Used via GEM ioctl. 1145 * 1146 * Returns: 1147 * 0 for success or a negative error code on failure. 1148 */ 1149 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1150 uint32_t metadata_size, uint64_t flags) 1151 { 1152 struct amdgpu_bo_user *ubo; 1153 void *buffer; 1154 1155 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1156 ubo = to_amdgpu_bo_user(bo); 1157 if (!metadata_size) { 1158 if (ubo->metadata_size) { 1159 kfree(ubo->metadata); 1160 ubo->metadata = NULL; 1161 ubo->metadata_size = 0; 1162 } 1163 return 0; 1164 } 1165 1166 if (metadata == NULL) 1167 return -EINVAL; 1168 1169 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1170 if (buffer == NULL) 1171 return -ENOMEM; 1172 1173 kfree(ubo->metadata); 1174 ubo->metadata_flags = flags; 1175 ubo->metadata = buffer; 1176 ubo->metadata_size = metadata_size; 1177 1178 return 0; 1179 } 1180 1181 /** 1182 * amdgpu_bo_get_metadata - get metadata 1183 * @bo: &amdgpu_bo buffer object 1184 * @buffer: returned metadata 1185 * @buffer_size: size of the buffer 1186 * @metadata_size: size of the returned metadata 1187 * @flags: flags of the returned metadata 1188 * 1189 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1190 * less than metadata_size. 1191 * Used via GEM ioctl. 1192 * 1193 * Returns: 1194 * 0 for success or a negative error code on failure. 1195 */ 1196 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1197 size_t buffer_size, uint32_t *metadata_size, 1198 uint64_t *flags) 1199 { 1200 struct amdgpu_bo_user *ubo; 1201 1202 if (!buffer && !metadata_size) 1203 return -EINVAL; 1204 1205 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1206 ubo = to_amdgpu_bo_user(bo); 1207 if (metadata_size) 1208 *metadata_size = ubo->metadata_size; 1209 1210 if (buffer) { 1211 if (buffer_size < ubo->metadata_size) 1212 return -EINVAL; 1213 1214 if (ubo->metadata_size) 1215 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1216 } 1217 1218 if (flags) 1219 *flags = ubo->metadata_flags; 1220 1221 return 0; 1222 } 1223 1224 /** 1225 * amdgpu_bo_move_notify - notification about a memory move 1226 * @bo: pointer to a buffer object 1227 * @evict: if this move is evicting the buffer from the graphics address space 1228 * @new_mem: new information of the bufer object 1229 * 1230 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1231 * bookkeeping. 1232 * TTM driver callback which is called when ttm moves a buffer. 1233 */ 1234 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1235 bool evict, 1236 struct ttm_resource *new_mem) 1237 { 1238 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1239 struct amdgpu_bo *abo; 1240 struct ttm_resource *old_mem = bo->resource; 1241 1242 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1243 return; 1244 1245 abo = ttm_to_amdgpu_bo(bo); 1246 amdgpu_vm_bo_invalidate(adev, abo, evict); 1247 1248 amdgpu_bo_kunmap(abo); 1249 1250 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1251 bo->resource->mem_type != TTM_PL_SYSTEM) 1252 dma_buf_move_notify(abo->tbo.base.dma_buf); 1253 1254 /* remember the eviction */ 1255 if (evict) 1256 atomic64_inc(&adev->num_evictions); 1257 1258 /* update statistics */ 1259 if (!new_mem) 1260 return; 1261 1262 /* move_notify is called before move happens */ 1263 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1264 } 1265 1266 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, 1267 struct amdgpu_mem_stats *stats) 1268 { 1269 unsigned int domain; 1270 uint64_t size = amdgpu_bo_size(bo); 1271 1272 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1273 switch (domain) { 1274 case AMDGPU_GEM_DOMAIN_VRAM: 1275 stats->vram += size; 1276 if (amdgpu_bo_in_cpu_visible_vram(bo)) 1277 stats->visible_vram += size; 1278 break; 1279 case AMDGPU_GEM_DOMAIN_GTT: 1280 stats->gtt += size; 1281 break; 1282 case AMDGPU_GEM_DOMAIN_CPU: 1283 default: 1284 stats->cpu += size; 1285 break; 1286 } 1287 1288 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) { 1289 stats->requested_vram += size; 1290 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1291 stats->requested_visible_vram += size; 1292 1293 if (domain != AMDGPU_GEM_DOMAIN_VRAM) { 1294 stats->evicted_vram += size; 1295 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1296 stats->evicted_visible_vram += size; 1297 } 1298 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) { 1299 stats->requested_gtt += size; 1300 } 1301 } 1302 1303 /** 1304 * amdgpu_bo_release_notify - notification about a BO being released 1305 * @bo: pointer to a buffer object 1306 * 1307 * Wipes VRAM buffers whose contents should not be leaked before the 1308 * memory is released. 1309 */ 1310 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1311 { 1312 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1313 struct dma_fence *fence = NULL; 1314 struct amdgpu_bo *abo; 1315 int r; 1316 1317 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1318 return; 1319 1320 abo = ttm_to_amdgpu_bo(bo); 1321 1322 if (abo->kfd_bo) 1323 amdgpu_amdkfd_release_notify(abo); 1324 1325 /* We only remove the fence if the resv has individualized. */ 1326 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1327 && bo->base.resv != &bo->base._resv); 1328 if (bo->base.resv == &bo->base._resv) 1329 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1330 1331 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1332 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1333 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1334 return; 1335 1336 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1337 return; 1338 1339 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1340 if (!WARN_ON(r)) { 1341 amdgpu_bo_fence(abo, fence, false); 1342 dma_fence_put(fence); 1343 } 1344 1345 dma_resv_unlock(bo->base.resv); 1346 } 1347 1348 /** 1349 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1350 * @bo: pointer to a buffer object 1351 * 1352 * Notifies the driver we are taking a fault on this BO and have reserved it, 1353 * also performs bookkeeping. 1354 * TTM driver callback for dealing with vm faults. 1355 * 1356 * Returns: 1357 * 0 for success or a negative error code on failure. 1358 */ 1359 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1360 { 1361 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1362 struct ttm_operation_ctx ctx = { false, false }; 1363 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1364 int r; 1365 1366 /* Remember that this BO was accessed by the CPU */ 1367 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1368 1369 if (bo->resource->mem_type != TTM_PL_VRAM) 1370 return 0; 1371 1372 if (amdgpu_bo_in_cpu_visible_vram(abo)) 1373 return 0; 1374 1375 /* Can't move a pinned BO to visible VRAM */ 1376 if (abo->tbo.pin_count > 0) 1377 return VM_FAULT_SIGBUS; 1378 1379 /* hurrah the memory is not visible ! */ 1380 atomic64_inc(&adev->num_vram_cpu_page_faults); 1381 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1382 AMDGPU_GEM_DOMAIN_GTT); 1383 1384 /* Avoid costly evictions; only set GTT as a busy placement */ 1385 abo->placement.num_busy_placement = 1; 1386 abo->placement.busy_placement = &abo->placements[1]; 1387 1388 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1389 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1390 return VM_FAULT_NOPAGE; 1391 else if (unlikely(r)) 1392 return VM_FAULT_SIGBUS; 1393 1394 /* this should never happen */ 1395 if (bo->resource->mem_type == TTM_PL_VRAM && 1396 !amdgpu_bo_in_cpu_visible_vram(abo)) 1397 return VM_FAULT_SIGBUS; 1398 1399 ttm_bo_move_to_lru_tail_unlocked(bo); 1400 return 0; 1401 } 1402 1403 /** 1404 * amdgpu_bo_fence - add fence to buffer object 1405 * 1406 * @bo: buffer object in question 1407 * @fence: fence to add 1408 * @shared: true if fence should be added shared 1409 * 1410 */ 1411 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1412 bool shared) 1413 { 1414 struct dma_resv *resv = bo->tbo.base.resv; 1415 int r; 1416 1417 r = dma_resv_reserve_fences(resv, 1); 1418 if (r) { 1419 /* As last resort on OOM we block for the fence */ 1420 dma_fence_wait(fence, false); 1421 return; 1422 } 1423 1424 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1425 DMA_RESV_USAGE_WRITE); 1426 } 1427 1428 /** 1429 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1430 * 1431 * @adev: amdgpu device pointer 1432 * @resv: reservation object to sync to 1433 * @sync_mode: synchronization mode 1434 * @owner: fence owner 1435 * @intr: Whether the wait is interruptible 1436 * 1437 * Extract the fences from the reservation object and waits for them to finish. 1438 * 1439 * Returns: 1440 * 0 on success, errno otherwise. 1441 */ 1442 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1443 enum amdgpu_sync_mode sync_mode, void *owner, 1444 bool intr) 1445 { 1446 struct amdgpu_sync sync; 1447 int r; 1448 1449 amdgpu_sync_create(&sync); 1450 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1451 r = amdgpu_sync_wait(&sync, intr); 1452 amdgpu_sync_free(&sync); 1453 return r; 1454 } 1455 1456 /** 1457 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1458 * @bo: buffer object to wait for 1459 * @owner: fence owner 1460 * @intr: Whether the wait is interruptible 1461 * 1462 * Wrapper to wait for fences in a BO. 1463 * Returns: 1464 * 0 on success, errno otherwise. 1465 */ 1466 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1467 { 1468 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1469 1470 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1471 AMDGPU_SYNC_NE_OWNER, owner, intr); 1472 } 1473 1474 /** 1475 * amdgpu_bo_gpu_offset - return GPU offset of bo 1476 * @bo: amdgpu object for which we query the offset 1477 * 1478 * Note: object should either be pinned or reserved when calling this 1479 * function, it might be useful to add check for this for debugging. 1480 * 1481 * Returns: 1482 * current GPU offset of the object. 1483 */ 1484 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1485 { 1486 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1487 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1488 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1489 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1490 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1491 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1492 1493 return amdgpu_bo_gpu_offset_no_check(bo); 1494 } 1495 1496 /** 1497 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1498 * @bo: amdgpu object for which we query the offset 1499 * 1500 * Returns: 1501 * current GPU offset of the object without raising warnings. 1502 */ 1503 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1504 { 1505 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1506 uint64_t offset; 1507 1508 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1509 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1510 1511 return amdgpu_gmc_sign_extend(offset); 1512 } 1513 1514 /** 1515 * amdgpu_bo_get_preferred_domain - get preferred domain 1516 * @adev: amdgpu device object 1517 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1518 * 1519 * Returns: 1520 * Which of the allowed domains is preferred for allocating the BO. 1521 */ 1522 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1523 uint32_t domain) 1524 { 1525 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1526 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1527 domain = AMDGPU_GEM_DOMAIN_VRAM; 1528 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1529 domain = AMDGPU_GEM_DOMAIN_GTT; 1530 } 1531 return domain; 1532 } 1533 1534 #if defined(CONFIG_DEBUG_FS) 1535 #define amdgpu_bo_print_flag(m, bo, flag) \ 1536 do { \ 1537 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1538 seq_printf((m), " " #flag); \ 1539 } \ 1540 } while (0) 1541 1542 /** 1543 * amdgpu_bo_print_info - print BO info in debugfs file 1544 * 1545 * @id: Index or Id of the BO 1546 * @bo: Requested BO for printing info 1547 * @m: debugfs file 1548 * 1549 * Print BO information in debugfs file 1550 * 1551 * Returns: 1552 * Size of the BO in bytes. 1553 */ 1554 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1555 { 1556 struct dma_buf_attachment *attachment; 1557 struct dma_buf *dma_buf; 1558 unsigned int domain; 1559 const char *placement; 1560 unsigned int pin_count; 1561 u64 size; 1562 1563 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1564 switch (domain) { 1565 case AMDGPU_GEM_DOMAIN_VRAM: 1566 placement = "VRAM"; 1567 break; 1568 case AMDGPU_GEM_DOMAIN_GTT: 1569 placement = " GTT"; 1570 break; 1571 case AMDGPU_GEM_DOMAIN_CPU: 1572 default: 1573 placement = " CPU"; 1574 break; 1575 } 1576 1577 size = amdgpu_bo_size(bo); 1578 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1579 id, size, placement); 1580 1581 pin_count = READ_ONCE(bo->tbo.pin_count); 1582 if (pin_count) 1583 seq_printf(m, " pin count %d", pin_count); 1584 1585 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1586 attachment = READ_ONCE(bo->tbo.base.import_attach); 1587 1588 if (attachment) 1589 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino); 1590 else if (dma_buf) 1591 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino); 1592 1593 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1594 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1595 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1596 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1597 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1598 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1599 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1600 1601 seq_puts(m, "\n"); 1602 1603 return size; 1604 } 1605 #endif 1606