1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/amdgpu_drm.h> 37 #include <drm/drm_cache.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 #include "amdgpu_amdkfd.h" 41 42 /** 43 * DOC: amdgpu_object 44 * 45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 46 * represents memory used by driver (VRAM, system memory, etc.). The driver 47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 48 * to create/destroy/set buffer object which are then managed by the kernel TTM 49 * memory manager. 50 * The interfaces are also used internally by kernel clients, including gfx, 51 * uvd, etc. for kernel managed allocations used by the GPU. 52 * 53 */ 54 55 /** 56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 57 * 58 * @bo: &amdgpu_bo buffer object 59 * 60 * This function is called when a BO stops being pinned, and updates the 61 * &amdgpu_device pin_size values accordingly. 62 */ 63 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 64 { 65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 66 67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 70 &adev->visible_pin_size); 71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 73 } 74 } 75 76 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 77 { 78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 80 81 if (bo->pin_count > 0) 82 amdgpu_bo_subtract_pin_size(bo); 83 84 amdgpu_bo_kunmap(bo); 85 86 if (bo->tbo.base.import_attach) 87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 88 drm_gem_object_release(&bo->tbo.base); 89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 90 if (!list_empty(&bo->shadow_list)) { 91 mutex_lock(&adev->shadow_list_lock); 92 list_del_init(&bo->shadow_list); 93 mutex_unlock(&adev->shadow_list_lock); 94 } 95 amdgpu_bo_unref(&bo->parent); 96 97 kfree(bo->metadata); 98 kfree(bo); 99 } 100 101 /** 102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 103 * @bo: buffer object to be checked 104 * 105 * Uses destroy function associated with the object to determine if this is 106 * an &amdgpu_bo. 107 * 108 * Returns: 109 * true if the object belongs to &amdgpu_bo, false if not. 110 */ 111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 112 { 113 if (bo->destroy == &amdgpu_bo_destroy) 114 return true; 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 137 places[c].fpfn = 0; 138 places[c].lpfn = 0; 139 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 140 TTM_PL_FLAG_VRAM; 141 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 places[c].lpfn = visible_pfn; 144 else 145 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 146 147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 149 c++; 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 places[c].fpfn = 0; 154 places[c].lpfn = 0; 155 places[c].flags = TTM_PL_FLAG_TT; 156 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 157 places[c].flags |= TTM_PL_FLAG_WC | 158 TTM_PL_FLAG_UNCACHED; 159 else 160 places[c].flags |= TTM_PL_FLAG_CACHED; 161 c++; 162 } 163 164 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 165 places[c].fpfn = 0; 166 places[c].lpfn = 0; 167 places[c].flags = TTM_PL_FLAG_SYSTEM; 168 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 169 places[c].flags |= TTM_PL_FLAG_WC | 170 TTM_PL_FLAG_UNCACHED; 171 else 172 places[c].flags |= TTM_PL_FLAG_CACHED; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 180 c++; 181 } 182 183 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 184 places[c].fpfn = 0; 185 places[c].lpfn = 0; 186 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 187 c++; 188 } 189 190 if (domain & AMDGPU_GEM_DOMAIN_OA) { 191 places[c].fpfn = 0; 192 places[c].lpfn = 0; 193 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 194 c++; 195 } 196 197 if (!c) { 198 places[c].fpfn = 0; 199 places[c].lpfn = 0; 200 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 201 c++; 202 } 203 204 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 205 206 placement->num_placement = c; 207 placement->placement = places; 208 209 placement->num_busy_placement = c; 210 placement->busy_placement = places; 211 } 212 213 /** 214 * amdgpu_bo_create_reserved - create reserved BO for kernel use 215 * 216 * @adev: amdgpu device object 217 * @size: size for the new BO 218 * @align: alignment for the new BO 219 * @domain: where to place it 220 * @bo_ptr: used to initialize BOs in structures 221 * @gpu_addr: GPU addr of the pinned BO 222 * @cpu_addr: optional CPU address mapping 223 * 224 * Allocates and pins a BO for kernel internal use, and returns it still 225 * reserved. 226 * 227 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 228 * 229 * Returns: 230 * 0 on success, negative error code otherwise. 231 */ 232 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 233 unsigned long size, int align, 234 u32 domain, struct amdgpu_bo **bo_ptr, 235 u64 *gpu_addr, void **cpu_addr) 236 { 237 struct amdgpu_bo_param bp; 238 bool free = false; 239 int r; 240 241 if (!size) { 242 amdgpu_bo_unref(bo_ptr); 243 return 0; 244 } 245 246 memset(&bp, 0, sizeof(bp)); 247 bp.size = size; 248 bp.byte_align = align; 249 bp.domain = domain; 250 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 251 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 252 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 253 bp.type = ttm_bo_type_kernel; 254 bp.resv = NULL; 255 256 if (!*bo_ptr) { 257 r = amdgpu_bo_create(adev, &bp, bo_ptr); 258 if (r) { 259 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 260 r); 261 return r; 262 } 263 free = true; 264 } 265 266 r = amdgpu_bo_reserve(*bo_ptr, false); 267 if (r) { 268 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 269 goto error_free; 270 } 271 272 r = amdgpu_bo_pin(*bo_ptr, domain); 273 if (r) { 274 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 275 goto error_unreserve; 276 } 277 278 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 279 if (r) { 280 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 281 goto error_unpin; 282 } 283 284 if (gpu_addr) 285 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 286 287 if (cpu_addr) { 288 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 289 if (r) { 290 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 291 goto error_unpin; 292 } 293 } 294 295 return 0; 296 297 error_unpin: 298 amdgpu_bo_unpin(*bo_ptr); 299 error_unreserve: 300 amdgpu_bo_unreserve(*bo_ptr); 301 302 error_free: 303 if (free) 304 amdgpu_bo_unref(bo_ptr); 305 306 return r; 307 } 308 309 /** 310 * amdgpu_bo_create_kernel - create BO for kernel use 311 * 312 * @adev: amdgpu device object 313 * @size: size for the new BO 314 * @align: alignment for the new BO 315 * @domain: where to place it 316 * @bo_ptr: used to initialize BOs in structures 317 * @gpu_addr: GPU addr of the pinned BO 318 * @cpu_addr: optional CPU address mapping 319 * 320 * Allocates and pins a BO for kernel internal use. 321 * 322 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 323 * 324 * Returns: 325 * 0 on success, negative error code otherwise. 326 */ 327 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 328 unsigned long size, int align, 329 u32 domain, struct amdgpu_bo **bo_ptr, 330 u64 *gpu_addr, void **cpu_addr) 331 { 332 int r; 333 334 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 335 gpu_addr, cpu_addr); 336 337 if (r) 338 return r; 339 340 if (*bo_ptr) 341 amdgpu_bo_unreserve(*bo_ptr); 342 343 return 0; 344 } 345 346 /** 347 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 348 * 349 * @adev: amdgpu device object 350 * @offset: offset of the BO 351 * @size: size of the BO 352 * @domain: where to place it 353 * @bo_ptr: used to initialize BOs in structures 354 * @cpu_addr: optional CPU address mapping 355 * 356 * Creates a kernel BO at a specific offset in the address space of the domain. 357 * 358 * Returns: 359 * 0 on success, negative error code otherwise. 360 */ 361 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 362 uint64_t offset, uint64_t size, uint32_t domain, 363 struct amdgpu_bo **bo_ptr, void **cpu_addr) 364 { 365 struct ttm_operation_ctx ctx = { false, false }; 366 unsigned int i; 367 int r; 368 369 offset &= PAGE_MASK; 370 size = ALIGN(size, PAGE_SIZE); 371 372 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 373 NULL, cpu_addr); 374 if (r) 375 return r; 376 377 if ((*bo_ptr) == NULL) 378 return 0; 379 380 /* 381 * Remove the original mem node and create a new one at the request 382 * position. 383 */ 384 if (cpu_addr) 385 amdgpu_bo_kunmap(*bo_ptr); 386 387 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); 388 389 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 390 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 391 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 392 } 393 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 394 &(*bo_ptr)->tbo.mem, &ctx); 395 if (r) 396 goto error; 397 398 if (cpu_addr) { 399 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 400 if (r) 401 goto error; 402 } 403 404 amdgpu_bo_unreserve(*bo_ptr); 405 return 0; 406 407 error: 408 amdgpu_bo_unreserve(*bo_ptr); 409 amdgpu_bo_unref(bo_ptr); 410 return r; 411 } 412 413 /** 414 * amdgpu_bo_free_kernel - free BO for kernel use 415 * 416 * @bo: amdgpu BO to free 417 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 418 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 419 * 420 * unmaps and unpin a BO for kernel internal use. 421 */ 422 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 423 void **cpu_addr) 424 { 425 if (*bo == NULL) 426 return; 427 428 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 429 if (cpu_addr) 430 amdgpu_bo_kunmap(*bo); 431 432 amdgpu_bo_unpin(*bo); 433 amdgpu_bo_unreserve(*bo); 434 } 435 amdgpu_bo_unref(bo); 436 437 if (gpu_addr) 438 *gpu_addr = 0; 439 440 if (cpu_addr) 441 *cpu_addr = NULL; 442 } 443 444 /* Validate bo size is bit bigger then the request domain */ 445 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 446 unsigned long size, u32 domain) 447 { 448 struct ttm_resource_manager *man = NULL; 449 450 /* 451 * If GTT is part of requested domains the check must succeed to 452 * allow fall back to GTT 453 */ 454 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 455 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 456 457 if (size < (man->size << PAGE_SHIFT)) 458 return true; 459 else 460 goto fail; 461 } 462 463 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 464 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 465 466 if (size < (man->size << PAGE_SHIFT)) 467 return true; 468 else 469 goto fail; 470 } 471 472 473 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 474 return true; 475 476 fail: 477 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 478 man->size << PAGE_SHIFT); 479 return false; 480 } 481 482 bool amdgpu_bo_support_uswc(u64 bo_flags) 483 { 484 485 #ifdef CONFIG_X86_32 486 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 487 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 488 */ 489 return false; 490 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 491 /* Don't try to enable write-combining when it can't work, or things 492 * may be slow 493 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 494 */ 495 496 #ifndef CONFIG_COMPILE_TEST 497 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 498 thanks to write-combining 499 #endif 500 501 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 502 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 503 "better performance thanks to write-combining\n"); 504 return false; 505 #else 506 /* For architectures that don't support WC memory, 507 * mask out the WC flag from the BO 508 */ 509 if (!drm_arch_can_wc_memory()) 510 return false; 511 512 return true; 513 #endif 514 } 515 516 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 517 struct amdgpu_bo_param *bp, 518 struct amdgpu_bo **bo_ptr) 519 { 520 struct ttm_operation_ctx ctx = { 521 .interruptible = (bp->type != ttm_bo_type_kernel), 522 .no_wait_gpu = bp->no_wait_gpu, 523 .resv = bp->resv, 524 .flags = bp->type != ttm_bo_type_kernel ? 525 TTM_OPT_FLAG_ALLOW_RES_EVICT : 0 526 }; 527 struct amdgpu_bo *bo; 528 unsigned long page_align, size = bp->size; 529 size_t acc_size; 530 int r; 531 532 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 533 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 534 /* GWS and OA don't need any alignment. */ 535 page_align = bp->byte_align; 536 size <<= PAGE_SHIFT; 537 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 538 /* Both size and alignment must be a multiple of 4. */ 539 page_align = ALIGN(bp->byte_align, 4); 540 size = ALIGN(size, 4) << PAGE_SHIFT; 541 } else { 542 /* Memory should be aligned at least to a page size. */ 543 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 544 size = ALIGN(size, PAGE_SIZE); 545 } 546 547 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 548 return -ENOMEM; 549 550 *bo_ptr = NULL; 551 552 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 553 sizeof(struct amdgpu_bo)); 554 555 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 556 if (bo == NULL) 557 return -ENOMEM; 558 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 559 INIT_LIST_HEAD(&bo->shadow_list); 560 bo->vm_bo = NULL; 561 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 562 bp->domain; 563 bo->allowed_domains = bo->preferred_domains; 564 if (bp->type != ttm_bo_type_kernel && 565 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 566 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 567 568 bo->flags = bp->flags; 569 570 if (!amdgpu_bo_support_uswc(bo->flags)) 571 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 572 573 bo->tbo.bdev = &adev->mman.bdev; 574 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 575 AMDGPU_GEM_DOMAIN_GDS)) 576 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 577 else 578 amdgpu_bo_placement_from_domain(bo, bp->domain); 579 if (bp->type == ttm_bo_type_kernel) 580 bo->tbo.priority = 1; 581 582 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 583 &bo->placement, page_align, &ctx, acc_size, 584 NULL, bp->resv, &amdgpu_bo_destroy); 585 if (unlikely(r != 0)) 586 return r; 587 588 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 589 bo->tbo.mem.mem_type == TTM_PL_VRAM && 590 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 591 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 592 ctx.bytes_moved); 593 else 594 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 595 596 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 597 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 598 struct dma_fence *fence; 599 600 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 601 if (unlikely(r)) 602 goto fail_unreserve; 603 604 amdgpu_bo_fence(bo, fence, false); 605 dma_fence_put(bo->tbo.moving); 606 bo->tbo.moving = dma_fence_get(fence); 607 dma_fence_put(fence); 608 } 609 if (!bp->resv) 610 amdgpu_bo_unreserve(bo); 611 *bo_ptr = bo; 612 613 trace_amdgpu_bo_create(bo); 614 615 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 616 if (bp->type == ttm_bo_type_device) 617 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 618 619 return 0; 620 621 fail_unreserve: 622 if (!bp->resv) 623 dma_resv_unlock(bo->tbo.base.resv); 624 amdgpu_bo_unref(&bo); 625 return r; 626 } 627 628 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 629 unsigned long size, 630 struct amdgpu_bo *bo) 631 { 632 struct amdgpu_bo_param bp; 633 int r; 634 635 if (bo->shadow) 636 return 0; 637 638 memset(&bp, 0, sizeof(bp)); 639 bp.size = size; 640 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 641 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 642 AMDGPU_GEM_CREATE_SHADOW; 643 bp.type = ttm_bo_type_kernel; 644 bp.resv = bo->tbo.base.resv; 645 646 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 647 if (!r) { 648 bo->shadow->parent = amdgpu_bo_ref(bo); 649 mutex_lock(&adev->shadow_list_lock); 650 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 651 mutex_unlock(&adev->shadow_list_lock); 652 } 653 654 return r; 655 } 656 657 /** 658 * amdgpu_bo_create - create an &amdgpu_bo buffer object 659 * @adev: amdgpu device object 660 * @bp: parameters to be used for the buffer object 661 * @bo_ptr: pointer to the buffer object pointer 662 * 663 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 664 * shadow object. 665 * Shadow object is used to backup the original buffer object, and is always 666 * in GTT. 667 * 668 * Returns: 669 * 0 for success or a negative error code on failure. 670 */ 671 int amdgpu_bo_create(struct amdgpu_device *adev, 672 struct amdgpu_bo_param *bp, 673 struct amdgpu_bo **bo_ptr) 674 { 675 u64 flags = bp->flags; 676 int r; 677 678 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 679 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 680 if (r) 681 return r; 682 683 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 684 if (!bp->resv) 685 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 686 NULL)); 687 688 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 689 690 if (!bp->resv) 691 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 692 693 if (r) 694 amdgpu_bo_unref(bo_ptr); 695 } 696 697 return r; 698 } 699 700 /** 701 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 702 * @bo: pointer to the buffer object 703 * 704 * Sets placement according to domain; and changes placement and caching 705 * policy of the buffer object according to the placement. 706 * This is used for validating shadow bos. It calls ttm_bo_validate() to 707 * make sure the buffer is resident where it needs to be. 708 * 709 * Returns: 710 * 0 for success or a negative error code on failure. 711 */ 712 int amdgpu_bo_validate(struct amdgpu_bo *bo) 713 { 714 struct ttm_operation_ctx ctx = { false, false }; 715 uint32_t domain; 716 int r; 717 718 if (bo->pin_count) 719 return 0; 720 721 domain = bo->preferred_domains; 722 723 retry: 724 amdgpu_bo_placement_from_domain(bo, domain); 725 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 726 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 727 domain = bo->allowed_domains; 728 goto retry; 729 } 730 731 return r; 732 } 733 734 /** 735 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 736 * 737 * @shadow: &amdgpu_bo shadow to be restored 738 * @fence: dma_fence associated with the operation 739 * 740 * Copies a buffer object's shadow content back to the object. 741 * This is used for recovering a buffer from its shadow in case of a gpu 742 * reset where vram context may be lost. 743 * 744 * Returns: 745 * 0 for success or a negative error code on failure. 746 */ 747 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 748 749 { 750 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 751 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 752 uint64_t shadow_addr, parent_addr; 753 754 shadow_addr = amdgpu_bo_gpu_offset(shadow); 755 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 756 757 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 758 amdgpu_bo_size(shadow), NULL, fence, 759 true, false, false); 760 } 761 762 /** 763 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 764 * @bo: &amdgpu_bo buffer object to be mapped 765 * @ptr: kernel virtual address to be returned 766 * 767 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 768 * amdgpu_bo_kptr() to get the kernel virtual address. 769 * 770 * Returns: 771 * 0 for success or a negative error code on failure. 772 */ 773 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 774 { 775 void *kptr; 776 long r; 777 778 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 779 return -EPERM; 780 781 kptr = amdgpu_bo_kptr(bo); 782 if (kptr) { 783 if (ptr) 784 *ptr = kptr; 785 return 0; 786 } 787 788 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 789 MAX_SCHEDULE_TIMEOUT); 790 if (r < 0) 791 return r; 792 793 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 794 if (r) 795 return r; 796 797 if (ptr) 798 *ptr = amdgpu_bo_kptr(bo); 799 800 return 0; 801 } 802 803 /** 804 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 805 * @bo: &amdgpu_bo buffer object 806 * 807 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 808 * 809 * Returns: 810 * the virtual address of a buffer object area. 811 */ 812 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 813 { 814 bool is_iomem; 815 816 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 817 } 818 819 /** 820 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 821 * @bo: &amdgpu_bo buffer object to be unmapped 822 * 823 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 824 */ 825 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 826 { 827 if (bo->kmap.bo) 828 ttm_bo_kunmap(&bo->kmap); 829 } 830 831 /** 832 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 833 * @bo: &amdgpu_bo buffer object 834 * 835 * References the contained &ttm_buffer_object. 836 * 837 * Returns: 838 * a refcounted pointer to the &amdgpu_bo buffer object. 839 */ 840 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 841 { 842 if (bo == NULL) 843 return NULL; 844 845 ttm_bo_get(&bo->tbo); 846 return bo; 847 } 848 849 /** 850 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 851 * @bo: &amdgpu_bo buffer object 852 * 853 * Unreferences the contained &ttm_buffer_object and clear the pointer 854 */ 855 void amdgpu_bo_unref(struct amdgpu_bo **bo) 856 { 857 struct ttm_buffer_object *tbo; 858 859 if ((*bo) == NULL) 860 return; 861 862 tbo = &((*bo)->tbo); 863 ttm_bo_put(tbo); 864 *bo = NULL; 865 } 866 867 /** 868 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 869 * @bo: &amdgpu_bo buffer object to be pinned 870 * @domain: domain to be pinned to 871 * @min_offset: the start of requested address range 872 * @max_offset: the end of requested address range 873 * 874 * Pins the buffer object according to requested domain and address range. If 875 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 876 * pin_count and pin_size accordingly. 877 * 878 * Pinning means to lock pages in memory along with keeping them at a fixed 879 * offset. It is required when a buffer can not be moved, for example, when 880 * a display buffer is being scanned out. 881 * 882 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 883 * where to pin a buffer if there are specific restrictions on where a buffer 884 * must be located. 885 * 886 * Returns: 887 * 0 for success or a negative error code on failure. 888 */ 889 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 890 u64 min_offset, u64 max_offset) 891 { 892 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 893 struct ttm_operation_ctx ctx = { false, false }; 894 int r, i; 895 896 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 897 return -EPERM; 898 899 if (WARN_ON_ONCE(min_offset > max_offset)) 900 return -EINVAL; 901 902 /* A shared bo cannot be migrated to VRAM */ 903 if (bo->prime_shared_count) { 904 if (domain & AMDGPU_GEM_DOMAIN_GTT) 905 domain = AMDGPU_GEM_DOMAIN_GTT; 906 else 907 return -EINVAL; 908 } 909 910 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 911 * See function amdgpu_display_supported_domains() 912 */ 913 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 914 915 if (bo->pin_count) { 916 uint32_t mem_type = bo->tbo.mem.mem_type; 917 918 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 919 return -EINVAL; 920 921 bo->pin_count++; 922 923 if (max_offset != 0) { 924 u64 domain_start = amdgpu_ttm_domain_start(adev, 925 mem_type); 926 WARN_ON_ONCE(max_offset < 927 (amdgpu_bo_gpu_offset(bo) - domain_start)); 928 } 929 930 return 0; 931 } 932 933 if (bo->tbo.base.import_attach) 934 dma_buf_pin(bo->tbo.base.import_attach); 935 936 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 937 /* force to pin into visible video ram */ 938 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 939 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 940 amdgpu_bo_placement_from_domain(bo, domain); 941 for (i = 0; i < bo->placement.num_placement; i++) { 942 unsigned fpfn, lpfn; 943 944 fpfn = min_offset >> PAGE_SHIFT; 945 lpfn = max_offset >> PAGE_SHIFT; 946 947 if (fpfn > bo->placements[i].fpfn) 948 bo->placements[i].fpfn = fpfn; 949 if (!bo->placements[i].lpfn || 950 (lpfn && lpfn < bo->placements[i].lpfn)) 951 bo->placements[i].lpfn = lpfn; 952 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 953 } 954 955 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 956 if (unlikely(r)) { 957 dev_err(adev->dev, "%p pin failed\n", bo); 958 goto error; 959 } 960 961 bo->pin_count = 1; 962 963 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 964 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 965 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 966 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 967 &adev->visible_pin_size); 968 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 969 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 970 } 971 972 error: 973 return r; 974 } 975 976 /** 977 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 978 * @bo: &amdgpu_bo buffer object to be pinned 979 * @domain: domain to be pinned to 980 * 981 * A simple wrapper to amdgpu_bo_pin_restricted(). 982 * Provides a simpler API for buffers that do not have any strict restrictions 983 * on where a buffer must be located. 984 * 985 * Returns: 986 * 0 for success or a negative error code on failure. 987 */ 988 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 989 { 990 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 991 } 992 993 /** 994 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 995 * @bo: &amdgpu_bo buffer object to be unpinned 996 * 997 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 998 * Changes placement and pin size accordingly. 999 * 1000 * Returns: 1001 * 0 for success or a negative error code on failure. 1002 */ 1003 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 1004 { 1005 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1006 struct ttm_operation_ctx ctx = { false, false }; 1007 int r, i; 1008 1009 if (WARN_ON_ONCE(!bo->pin_count)) { 1010 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 1011 return 0; 1012 } 1013 bo->pin_count--; 1014 if (bo->pin_count) 1015 return 0; 1016 1017 amdgpu_bo_subtract_pin_size(bo); 1018 1019 if (bo->tbo.base.import_attach) 1020 dma_buf_unpin(bo->tbo.base.import_attach); 1021 1022 for (i = 0; i < bo->placement.num_placement; i++) { 1023 bo->placements[i].lpfn = 0; 1024 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 1025 } 1026 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1027 if (unlikely(r)) 1028 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 1029 1030 return r; 1031 } 1032 1033 /** 1034 * amdgpu_bo_evict_vram - evict VRAM buffers 1035 * @adev: amdgpu device object 1036 * 1037 * Evicts all VRAM buffers on the lru list of the memory type. 1038 * Mainly used for evicting vram at suspend time. 1039 * 1040 * Returns: 1041 * 0 for success or a negative error code on failure. 1042 */ 1043 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1044 { 1045 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1046 #ifndef CONFIG_HIBERNATION 1047 if (adev->flags & AMD_IS_APU) { 1048 /* Useless to evict on IGP chips */ 1049 return 0; 1050 } 1051 #endif 1052 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 1053 } 1054 1055 static const char *amdgpu_vram_names[] = { 1056 "UNKNOWN", 1057 "GDDR1", 1058 "DDR2", 1059 "GDDR3", 1060 "GDDR4", 1061 "GDDR5", 1062 "HBM", 1063 "DDR3", 1064 "DDR4", 1065 "GDDR6", 1066 }; 1067 1068 /** 1069 * amdgpu_bo_init - initialize memory manager 1070 * @adev: amdgpu device object 1071 * 1072 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1073 * 1074 * Returns: 1075 * 0 for success or a negative error code on failure. 1076 */ 1077 int amdgpu_bo_init(struct amdgpu_device *adev) 1078 { 1079 /* reserve PAT memory space to WC for VRAM */ 1080 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1081 adev->gmc.aper_size); 1082 1083 /* Add an MTRR for the VRAM */ 1084 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1085 adev->gmc.aper_size); 1086 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1087 adev->gmc.mc_vram_size >> 20, 1088 (unsigned long long)adev->gmc.aper_size >> 20); 1089 DRM_INFO("RAM width %dbits %s\n", 1090 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1091 return amdgpu_ttm_init(adev); 1092 } 1093 1094 /** 1095 * amdgpu_bo_late_init - late init 1096 * @adev: amdgpu device object 1097 * 1098 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1099 * initialization. 1100 * 1101 * Returns: 1102 * 0 for success or a negative error code on failure. 1103 */ 1104 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1105 { 1106 amdgpu_ttm_late_init(adev); 1107 1108 return 0; 1109 } 1110 1111 /** 1112 * amdgpu_bo_fini - tear down memory manager 1113 * @adev: amdgpu device object 1114 * 1115 * Reverses amdgpu_bo_init() to tear down memory manager. 1116 */ 1117 void amdgpu_bo_fini(struct amdgpu_device *adev) 1118 { 1119 amdgpu_ttm_fini(adev); 1120 arch_phys_wc_del(adev->gmc.vram_mtrr); 1121 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1122 } 1123 1124 /** 1125 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1126 * @bo: &amdgpu_bo buffer object 1127 * @vma: vma as input from the fbdev mmap method 1128 * 1129 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1130 * 1131 * Returns: 1132 * 0 for success or a negative error code on failure. 1133 */ 1134 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1135 struct vm_area_struct *vma) 1136 { 1137 if (vma->vm_pgoff != 0) 1138 return -EACCES; 1139 1140 return ttm_bo_mmap_obj(vma, &bo->tbo); 1141 } 1142 1143 /** 1144 * amdgpu_bo_set_tiling_flags - set tiling flags 1145 * @bo: &amdgpu_bo buffer object 1146 * @tiling_flags: new flags 1147 * 1148 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1149 * kernel driver to set the tiling flags on a buffer. 1150 * 1151 * Returns: 1152 * 0 for success or a negative error code on failure. 1153 */ 1154 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1155 { 1156 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1157 1158 if (adev->family <= AMDGPU_FAMILY_CZ && 1159 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1160 return -EINVAL; 1161 1162 bo->tiling_flags = tiling_flags; 1163 return 0; 1164 } 1165 1166 /** 1167 * amdgpu_bo_get_tiling_flags - get tiling flags 1168 * @bo: &amdgpu_bo buffer object 1169 * @tiling_flags: returned flags 1170 * 1171 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1172 * set the tiling flags on a buffer. 1173 */ 1174 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1175 { 1176 dma_resv_assert_held(bo->tbo.base.resv); 1177 1178 if (tiling_flags) 1179 *tiling_flags = bo->tiling_flags; 1180 } 1181 1182 /** 1183 * amdgpu_bo_set_metadata - set metadata 1184 * @bo: &amdgpu_bo buffer object 1185 * @metadata: new metadata 1186 * @metadata_size: size of the new metadata 1187 * @flags: flags of the new metadata 1188 * 1189 * Sets buffer object's metadata, its size and flags. 1190 * Used via GEM ioctl. 1191 * 1192 * Returns: 1193 * 0 for success or a negative error code on failure. 1194 */ 1195 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1196 uint32_t metadata_size, uint64_t flags) 1197 { 1198 void *buffer; 1199 1200 if (!metadata_size) { 1201 if (bo->metadata_size) { 1202 kfree(bo->metadata); 1203 bo->metadata = NULL; 1204 bo->metadata_size = 0; 1205 } 1206 return 0; 1207 } 1208 1209 if (metadata == NULL) 1210 return -EINVAL; 1211 1212 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1213 if (buffer == NULL) 1214 return -ENOMEM; 1215 1216 kfree(bo->metadata); 1217 bo->metadata_flags = flags; 1218 bo->metadata = buffer; 1219 bo->metadata_size = metadata_size; 1220 1221 return 0; 1222 } 1223 1224 /** 1225 * amdgpu_bo_get_metadata - get metadata 1226 * @bo: &amdgpu_bo buffer object 1227 * @buffer: returned metadata 1228 * @buffer_size: size of the buffer 1229 * @metadata_size: size of the returned metadata 1230 * @flags: flags of the returned metadata 1231 * 1232 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1233 * less than metadata_size. 1234 * Used via GEM ioctl. 1235 * 1236 * Returns: 1237 * 0 for success or a negative error code on failure. 1238 */ 1239 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1240 size_t buffer_size, uint32_t *metadata_size, 1241 uint64_t *flags) 1242 { 1243 if (!buffer && !metadata_size) 1244 return -EINVAL; 1245 1246 if (buffer) { 1247 if (buffer_size < bo->metadata_size) 1248 return -EINVAL; 1249 1250 if (bo->metadata_size) 1251 memcpy(buffer, bo->metadata, bo->metadata_size); 1252 } 1253 1254 if (metadata_size) 1255 *metadata_size = bo->metadata_size; 1256 if (flags) 1257 *flags = bo->metadata_flags; 1258 1259 return 0; 1260 } 1261 1262 /** 1263 * amdgpu_bo_move_notify - notification about a memory move 1264 * @bo: pointer to a buffer object 1265 * @evict: if this move is evicting the buffer from the graphics address space 1266 * @new_mem: new information of the bufer object 1267 * 1268 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1269 * bookkeeping. 1270 * TTM driver callback which is called when ttm moves a buffer. 1271 */ 1272 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1273 bool evict, 1274 struct ttm_resource *new_mem) 1275 { 1276 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1277 struct amdgpu_bo *abo; 1278 struct ttm_resource *old_mem = &bo->mem; 1279 1280 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1281 return; 1282 1283 abo = ttm_to_amdgpu_bo(bo); 1284 amdgpu_vm_bo_invalidate(adev, abo, evict); 1285 1286 amdgpu_bo_kunmap(abo); 1287 1288 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1289 bo->mem.mem_type != TTM_PL_SYSTEM) 1290 dma_buf_move_notify(abo->tbo.base.dma_buf); 1291 1292 /* remember the eviction */ 1293 if (evict) 1294 atomic64_inc(&adev->num_evictions); 1295 1296 /* update statistics */ 1297 if (!new_mem) 1298 return; 1299 1300 /* move_notify is called before move happens */ 1301 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1302 } 1303 1304 /** 1305 * amdgpu_bo_release_notify - notification about a BO being released 1306 * @bo: pointer to a buffer object 1307 * 1308 * Wipes VRAM buffers whose contents should not be leaked before the 1309 * memory is released. 1310 */ 1311 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1312 { 1313 struct dma_fence *fence = NULL; 1314 struct amdgpu_bo *abo; 1315 int r; 1316 1317 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1318 return; 1319 1320 abo = ttm_to_amdgpu_bo(bo); 1321 1322 if (abo->kfd_bo) 1323 amdgpu_amdkfd_unreserve_memory_limit(abo); 1324 1325 /* We only remove the fence if the resv has individualized. */ 1326 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1327 && bo->base.resv != &bo->base._resv); 1328 if (bo->base.resv == &bo->base._resv) 1329 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1330 1331 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1332 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1333 return; 1334 1335 dma_resv_lock(bo->base.resv, NULL); 1336 1337 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1338 if (!WARN_ON(r)) { 1339 amdgpu_bo_fence(abo, fence, false); 1340 dma_fence_put(fence); 1341 } 1342 1343 dma_resv_unlock(bo->base.resv); 1344 } 1345 1346 /** 1347 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1348 * @bo: pointer to a buffer object 1349 * 1350 * Notifies the driver we are taking a fault on this BO and have reserved it, 1351 * also performs bookkeeping. 1352 * TTM driver callback for dealing with vm faults. 1353 * 1354 * Returns: 1355 * 0 for success or a negative error code on failure. 1356 */ 1357 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1358 { 1359 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1360 struct ttm_operation_ctx ctx = { false, false }; 1361 struct amdgpu_bo *abo; 1362 unsigned long offset, size; 1363 int r; 1364 1365 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1366 return 0; 1367 1368 abo = ttm_to_amdgpu_bo(bo); 1369 1370 /* Remember that this BO was accessed by the CPU */ 1371 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1372 1373 if (bo->mem.mem_type != TTM_PL_VRAM) 1374 return 0; 1375 1376 size = bo->mem.num_pages << PAGE_SHIFT; 1377 offset = bo->mem.start << PAGE_SHIFT; 1378 if ((offset + size) <= adev->gmc.visible_vram_size) 1379 return 0; 1380 1381 /* Can't move a pinned BO to visible VRAM */ 1382 if (abo->pin_count > 0) 1383 return -EINVAL; 1384 1385 /* hurrah the memory is not visible ! */ 1386 atomic64_inc(&adev->num_vram_cpu_page_faults); 1387 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1388 AMDGPU_GEM_DOMAIN_GTT); 1389 1390 /* Avoid costly evictions; only set GTT as a busy placement */ 1391 abo->placement.num_busy_placement = 1; 1392 abo->placement.busy_placement = &abo->placements[1]; 1393 1394 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1395 if (unlikely(r != 0)) 1396 return r; 1397 1398 offset = bo->mem.start << PAGE_SHIFT; 1399 /* this should never happen */ 1400 if (bo->mem.mem_type == TTM_PL_VRAM && 1401 (offset + size) > adev->gmc.visible_vram_size) 1402 return -EINVAL; 1403 1404 return 0; 1405 } 1406 1407 /** 1408 * amdgpu_bo_fence - add fence to buffer object 1409 * 1410 * @bo: buffer object in question 1411 * @fence: fence to add 1412 * @shared: true if fence should be added shared 1413 * 1414 */ 1415 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1416 bool shared) 1417 { 1418 struct dma_resv *resv = bo->tbo.base.resv; 1419 1420 if (shared) 1421 dma_resv_add_shared_fence(resv, fence); 1422 else 1423 dma_resv_add_excl_fence(resv, fence); 1424 } 1425 1426 /** 1427 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1428 * 1429 * @adev: amdgpu device pointer 1430 * @resv: reservation object to sync to 1431 * @sync_mode: synchronization mode 1432 * @owner: fence owner 1433 * @intr: Whether the wait is interruptible 1434 * 1435 * Extract the fences from the reservation object and waits for them to finish. 1436 * 1437 * Returns: 1438 * 0 on success, errno otherwise. 1439 */ 1440 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1441 enum amdgpu_sync_mode sync_mode, void *owner, 1442 bool intr) 1443 { 1444 struct amdgpu_sync sync; 1445 int r; 1446 1447 amdgpu_sync_create(&sync); 1448 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1449 r = amdgpu_sync_wait(&sync, intr); 1450 amdgpu_sync_free(&sync); 1451 return r; 1452 } 1453 1454 /** 1455 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1456 * @bo: buffer object to wait for 1457 * @owner: fence owner 1458 * @intr: Whether the wait is interruptible 1459 * 1460 * Wrapper to wait for fences in a BO. 1461 * Returns: 1462 * 0 on success, errno otherwise. 1463 */ 1464 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1465 { 1466 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1467 1468 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1469 AMDGPU_SYNC_NE_OWNER, owner, intr); 1470 } 1471 1472 /** 1473 * amdgpu_bo_gpu_offset - return GPU offset of bo 1474 * @bo: amdgpu object for which we query the offset 1475 * 1476 * Note: object should either be pinned or reserved when calling this 1477 * function, it might be useful to add check for this for debugging. 1478 * 1479 * Returns: 1480 * current GPU offset of the object. 1481 */ 1482 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1483 { 1484 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1485 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1486 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); 1487 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1488 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1489 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1490 1491 return amdgpu_bo_gpu_offset_no_check(bo); 1492 } 1493 1494 /** 1495 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1496 * @bo: amdgpu object for which we query the offset 1497 * 1498 * Returns: 1499 * current GPU offset of the object without raising warnings. 1500 */ 1501 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1502 { 1503 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1504 uint64_t offset; 1505 1506 offset = (bo->tbo.mem.start << PAGE_SHIFT) + 1507 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type); 1508 1509 return amdgpu_gmc_sign_extend(offset); 1510 } 1511 1512 /** 1513 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1514 * @adev: amdgpu device object 1515 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1516 * 1517 * Returns: 1518 * Which of the allowed domains is preferred for pinning the BO for scanout. 1519 */ 1520 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1521 uint32_t domain) 1522 { 1523 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1524 domain = AMDGPU_GEM_DOMAIN_VRAM; 1525 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1526 domain = AMDGPU_GEM_DOMAIN_GTT; 1527 } 1528 return domain; 1529 } 1530