1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 59 60 amdgpu_bo_kunmap(bo); 61 62 if (bo->tbo.base.import_attach) 63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 64 drm_gem_object_release(&bo->tbo.base); 65 amdgpu_bo_unref(&bo->parent); 66 kvfree(bo); 67 } 68 69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 70 { 71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 72 struct amdgpu_bo_user *ubo; 73 74 ubo = to_amdgpu_bo_user(bo); 75 kfree(ubo->metadata); 76 amdgpu_bo_destroy(tbo); 77 } 78 79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 82 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 83 struct amdgpu_bo_vm *vmbo; 84 85 vmbo = to_amdgpu_bo_vm(bo); 86 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 87 if (!list_empty(&vmbo->shadow_list)) { 88 mutex_lock(&adev->shadow_list_lock); 89 list_del_init(&vmbo->shadow_list); 90 mutex_unlock(&adev->shadow_list_lock); 91 } 92 93 amdgpu_bo_destroy(tbo); 94 } 95 96 /** 97 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 98 * @bo: buffer object to be checked 99 * 100 * Uses destroy function associated with the object to determine if this is 101 * an &amdgpu_bo. 102 * 103 * Returns: 104 * true if the object belongs to &amdgpu_bo, false if not. 105 */ 106 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 107 { 108 if (bo->destroy == &amdgpu_bo_destroy || 109 bo->destroy == &amdgpu_bo_user_destroy || 110 bo->destroy == &amdgpu_bo_vm_destroy) 111 return true; 112 113 return false; 114 } 115 116 /** 117 * amdgpu_bo_placement_from_domain - set buffer's placement 118 * @abo: &amdgpu_bo buffer object whose placement is to be set 119 * @domain: requested domain 120 * 121 * Sets buffer's placement according to requested domain and the buffer's 122 * flags. 123 */ 124 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 125 { 126 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 127 struct ttm_placement *placement = &abo->placement; 128 struct ttm_place *places = abo->placements; 129 u64 flags = abo->flags; 130 u32 c = 0; 131 132 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 133 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 134 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 135 136 if (adev->gmc.mem_partitions && mem_id >= 0) { 137 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn; 138 /* 139 * memory partition range lpfn is inclusive start + size - 1 140 * TTM place lpfn is exclusive start + size 141 */ 142 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1; 143 } else { 144 places[c].fpfn = 0; 145 places[c].lpfn = 0; 146 } 147 places[c].mem_type = TTM_PL_VRAM; 148 places[c].flags = 0; 149 150 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 151 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); 152 else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size) 153 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 154 155 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 156 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 157 c++; 158 } 159 160 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 161 places[c].fpfn = 0; 162 places[c].lpfn = 0; 163 places[c].mem_type = 164 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 165 AMDGPU_PL_PREEMPT : TTM_PL_TT; 166 places[c].flags = 0; 167 c++; 168 } 169 170 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 171 places[c].fpfn = 0; 172 places[c].lpfn = 0; 173 places[c].mem_type = TTM_PL_SYSTEM; 174 places[c].flags = 0; 175 c++; 176 } 177 178 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 179 places[c].fpfn = 0; 180 places[c].lpfn = 0; 181 places[c].mem_type = AMDGPU_PL_GDS; 182 places[c].flags = 0; 183 c++; 184 } 185 186 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 187 places[c].fpfn = 0; 188 places[c].lpfn = 0; 189 places[c].mem_type = AMDGPU_PL_GWS; 190 places[c].flags = 0; 191 c++; 192 } 193 194 if (domain & AMDGPU_GEM_DOMAIN_OA) { 195 places[c].fpfn = 0; 196 places[c].lpfn = 0; 197 places[c].mem_type = AMDGPU_PL_OA; 198 places[c].flags = 0; 199 c++; 200 } 201 202 if (!c) { 203 places[c].fpfn = 0; 204 places[c].lpfn = 0; 205 places[c].mem_type = TTM_PL_SYSTEM; 206 places[c].flags = 0; 207 c++; 208 } 209 210 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 211 212 placement->num_placement = c; 213 placement->placement = places; 214 215 placement->num_busy_placement = c; 216 placement->busy_placement = places; 217 } 218 219 /** 220 * amdgpu_bo_create_reserved - create reserved BO for kernel use 221 * 222 * @adev: amdgpu device object 223 * @size: size for the new BO 224 * @align: alignment for the new BO 225 * @domain: where to place it 226 * @bo_ptr: used to initialize BOs in structures 227 * @gpu_addr: GPU addr of the pinned BO 228 * @cpu_addr: optional CPU address mapping 229 * 230 * Allocates and pins a BO for kernel internal use, and returns it still 231 * reserved. 232 * 233 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 234 * 235 * Returns: 236 * 0 on success, negative error code otherwise. 237 */ 238 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 239 unsigned long size, int align, 240 u32 domain, struct amdgpu_bo **bo_ptr, 241 u64 *gpu_addr, void **cpu_addr) 242 { 243 struct amdgpu_bo_param bp; 244 bool free = false; 245 int r; 246 247 if (!size) { 248 amdgpu_bo_unref(bo_ptr); 249 return 0; 250 } 251 252 memset(&bp, 0, sizeof(bp)); 253 bp.size = size; 254 bp.byte_align = align; 255 bp.domain = domain; 256 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 257 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 258 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 259 bp.type = ttm_bo_type_kernel; 260 bp.resv = NULL; 261 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 262 263 if (!*bo_ptr) { 264 r = amdgpu_bo_create(adev, &bp, bo_ptr); 265 if (r) { 266 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 267 r); 268 return r; 269 } 270 free = true; 271 } 272 273 r = amdgpu_bo_reserve(*bo_ptr, false); 274 if (r) { 275 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 276 goto error_free; 277 } 278 279 r = amdgpu_bo_pin(*bo_ptr, domain); 280 if (r) { 281 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 282 goto error_unreserve; 283 } 284 285 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 286 if (r) { 287 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 288 goto error_unpin; 289 } 290 291 if (gpu_addr) 292 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 293 294 if (cpu_addr) { 295 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 296 if (r) { 297 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 298 goto error_unpin; 299 } 300 } 301 302 return 0; 303 304 error_unpin: 305 amdgpu_bo_unpin(*bo_ptr); 306 error_unreserve: 307 amdgpu_bo_unreserve(*bo_ptr); 308 309 error_free: 310 if (free) 311 amdgpu_bo_unref(bo_ptr); 312 313 return r; 314 } 315 316 /** 317 * amdgpu_bo_create_kernel - create BO for kernel use 318 * 319 * @adev: amdgpu device object 320 * @size: size for the new BO 321 * @align: alignment for the new BO 322 * @domain: where to place it 323 * @bo_ptr: used to initialize BOs in structures 324 * @gpu_addr: GPU addr of the pinned BO 325 * @cpu_addr: optional CPU address mapping 326 * 327 * Allocates and pins a BO for kernel internal use. 328 * 329 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 330 * 331 * Returns: 332 * 0 on success, negative error code otherwise. 333 */ 334 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 335 unsigned long size, int align, 336 u32 domain, struct amdgpu_bo **bo_ptr, 337 u64 *gpu_addr, void **cpu_addr) 338 { 339 int r; 340 341 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 342 gpu_addr, cpu_addr); 343 344 if (r) 345 return r; 346 347 if (*bo_ptr) 348 amdgpu_bo_unreserve(*bo_ptr); 349 350 return 0; 351 } 352 353 /** 354 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 355 * 356 * @adev: amdgpu device object 357 * @offset: offset of the BO 358 * @size: size of the BO 359 * @bo_ptr: used to initialize BOs in structures 360 * @cpu_addr: optional CPU address mapping 361 * 362 * Creates a kernel BO at a specific offset in VRAM. 363 * 364 * Returns: 365 * 0 on success, negative error code otherwise. 366 */ 367 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 368 uint64_t offset, uint64_t size, 369 struct amdgpu_bo **bo_ptr, void **cpu_addr) 370 { 371 struct ttm_operation_ctx ctx = { false, false }; 372 unsigned int i; 373 int r; 374 375 offset &= PAGE_MASK; 376 size = ALIGN(size, PAGE_SIZE); 377 378 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 379 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL, 380 cpu_addr); 381 if (r) 382 return r; 383 384 if ((*bo_ptr) == NULL) 385 return 0; 386 387 /* 388 * Remove the original mem node and create a new one at the request 389 * position. 390 */ 391 if (cpu_addr) 392 amdgpu_bo_kunmap(*bo_ptr); 393 394 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 395 396 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 397 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 398 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 399 } 400 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 401 &(*bo_ptr)->tbo.resource, &ctx); 402 if (r) 403 goto error; 404 405 if (cpu_addr) { 406 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 407 if (r) 408 goto error; 409 } 410 411 amdgpu_bo_unreserve(*bo_ptr); 412 return 0; 413 414 error: 415 amdgpu_bo_unreserve(*bo_ptr); 416 amdgpu_bo_unref(bo_ptr); 417 return r; 418 } 419 420 /** 421 * amdgpu_bo_free_kernel - free BO for kernel use 422 * 423 * @bo: amdgpu BO to free 424 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 425 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 426 * 427 * unmaps and unpin a BO for kernel internal use. 428 */ 429 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 430 void **cpu_addr) 431 { 432 if (*bo == NULL) 433 return; 434 435 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend); 436 437 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 438 if (cpu_addr) 439 amdgpu_bo_kunmap(*bo); 440 441 amdgpu_bo_unpin(*bo); 442 amdgpu_bo_unreserve(*bo); 443 } 444 amdgpu_bo_unref(bo); 445 446 if (gpu_addr) 447 *gpu_addr = 0; 448 449 if (cpu_addr) 450 *cpu_addr = NULL; 451 } 452 453 /* Validate bo size is bit bigger then the request domain */ 454 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 455 unsigned long size, u32 domain) 456 { 457 struct ttm_resource_manager *man = NULL; 458 459 /* 460 * If GTT is part of requested domains the check must succeed to 461 * allow fall back to GTT. 462 */ 463 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 464 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 465 466 if (man && size < man->size) 467 return true; 468 else if (!man) 469 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 470 goto fail; 471 } else if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 472 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 473 474 if (man && size < man->size) 475 return true; 476 goto fail; 477 } 478 479 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 480 return true; 481 482 fail: 483 if (man) 484 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 485 man->size); 486 return false; 487 } 488 489 bool amdgpu_bo_support_uswc(u64 bo_flags) 490 { 491 492 #ifdef CONFIG_X86_32 493 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 494 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 495 */ 496 return false; 497 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 498 /* Don't try to enable write-combining when it can't work, or things 499 * may be slow 500 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 501 */ 502 503 #ifndef CONFIG_COMPILE_TEST 504 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 505 thanks to write-combining 506 #endif 507 508 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 509 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 510 "better performance thanks to write-combining\n"); 511 return false; 512 #else 513 /* For architectures that don't support WC memory, 514 * mask out the WC flag from the BO 515 */ 516 if (!drm_arch_can_wc_memory()) 517 return false; 518 519 return true; 520 #endif 521 } 522 523 /** 524 * amdgpu_bo_create - create an &amdgpu_bo buffer object 525 * @adev: amdgpu device object 526 * @bp: parameters to be used for the buffer object 527 * @bo_ptr: pointer to the buffer object pointer 528 * 529 * Creates an &amdgpu_bo buffer object. 530 * 531 * Returns: 532 * 0 for success or a negative error code on failure. 533 */ 534 int amdgpu_bo_create(struct amdgpu_device *adev, 535 struct amdgpu_bo_param *bp, 536 struct amdgpu_bo **bo_ptr) 537 { 538 struct ttm_operation_ctx ctx = { 539 .interruptible = (bp->type != ttm_bo_type_kernel), 540 .no_wait_gpu = bp->no_wait_gpu, 541 /* We opt to avoid OOM on system pages allocations */ 542 .gfp_retry_mayfail = true, 543 .allow_res_evict = bp->type != ttm_bo_type_kernel, 544 .resv = bp->resv 545 }; 546 struct amdgpu_bo *bo; 547 unsigned long page_align, size = bp->size; 548 int r; 549 550 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 551 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 552 /* GWS and OA don't need any alignment. */ 553 page_align = bp->byte_align; 554 size <<= PAGE_SHIFT; 555 556 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 557 /* Both size and alignment must be a multiple of 4. */ 558 page_align = ALIGN(bp->byte_align, 4); 559 size = ALIGN(size, 4) << PAGE_SHIFT; 560 } else { 561 /* Memory should be aligned at least to a page size. */ 562 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 563 size = ALIGN(size, PAGE_SIZE); 564 } 565 566 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 567 return -ENOMEM; 568 569 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 570 571 *bo_ptr = NULL; 572 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 573 if (bo == NULL) 574 return -ENOMEM; 575 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 576 bo->vm_bo = NULL; 577 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 578 bp->domain; 579 bo->allowed_domains = bo->preferred_domains; 580 if (bp->type != ttm_bo_type_kernel && 581 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 582 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 583 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 584 585 bo->flags = bp->flags; 586 587 if (adev->gmc.mem_partitions) 588 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */ 589 bo->xcp_id = bp->xcp_id_plus1 - 1; 590 else 591 /* For GPUs without spatial partitioning */ 592 bo->xcp_id = 0; 593 594 if (!amdgpu_bo_support_uswc(bo->flags)) 595 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 596 597 if (adev->ras_enabled) 598 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 599 600 bo->tbo.bdev = &adev->mman.bdev; 601 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 602 AMDGPU_GEM_DOMAIN_GDS)) 603 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 604 else 605 amdgpu_bo_placement_from_domain(bo, bp->domain); 606 if (bp->type == ttm_bo_type_kernel) 607 bo->tbo.priority = 1; 608 609 if (!bp->destroy) 610 bp->destroy = &amdgpu_bo_destroy; 611 612 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 613 &bo->placement, page_align, &ctx, NULL, 614 bp->resv, bp->destroy); 615 if (unlikely(r != 0)) 616 return r; 617 618 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 619 bo->tbo.resource->mem_type == TTM_PL_VRAM && 620 amdgpu_bo_in_cpu_visible_vram(bo)) 621 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 622 ctx.bytes_moved); 623 else 624 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 625 626 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 627 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 628 struct dma_fence *fence; 629 630 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 631 if (unlikely(r)) 632 goto fail_unreserve; 633 634 dma_resv_add_fence(bo->tbo.base.resv, fence, 635 DMA_RESV_USAGE_KERNEL); 636 dma_fence_put(fence); 637 } 638 if (!bp->resv) 639 amdgpu_bo_unreserve(bo); 640 *bo_ptr = bo; 641 642 trace_amdgpu_bo_create(bo); 643 644 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 645 if (bp->type == ttm_bo_type_device) 646 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 647 648 return 0; 649 650 fail_unreserve: 651 if (!bp->resv) 652 dma_resv_unlock(bo->tbo.base.resv); 653 amdgpu_bo_unref(&bo); 654 return r; 655 } 656 657 /** 658 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 659 * @adev: amdgpu device object 660 * @bp: parameters to be used for the buffer object 661 * @ubo_ptr: pointer to the buffer object pointer 662 * 663 * Create a BO to be used by user application; 664 * 665 * Returns: 666 * 0 for success or a negative error code on failure. 667 */ 668 669 int amdgpu_bo_create_user(struct amdgpu_device *adev, 670 struct amdgpu_bo_param *bp, 671 struct amdgpu_bo_user **ubo_ptr) 672 { 673 struct amdgpu_bo *bo_ptr; 674 int r; 675 676 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 677 bp->destroy = &amdgpu_bo_user_destroy; 678 r = amdgpu_bo_create(adev, bp, &bo_ptr); 679 if (r) 680 return r; 681 682 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 683 return r; 684 } 685 686 /** 687 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 688 * @adev: amdgpu device object 689 * @bp: parameters to be used for the buffer object 690 * @vmbo_ptr: pointer to the buffer object pointer 691 * 692 * Create a BO to be for GPUVM. 693 * 694 * Returns: 695 * 0 for success or a negative error code on failure. 696 */ 697 698 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 699 struct amdgpu_bo_param *bp, 700 struct amdgpu_bo_vm **vmbo_ptr) 701 { 702 struct amdgpu_bo *bo_ptr; 703 int r; 704 705 /* bo_ptr_size will be determined by the caller and it depends on 706 * num of amdgpu_vm_pt entries. 707 */ 708 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 709 r = amdgpu_bo_create(adev, bp, &bo_ptr); 710 if (r) 711 return r; 712 713 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 714 INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list); 715 /* Set destroy callback to amdgpu_bo_vm_destroy after vmbo->shadow_list 716 * is initialized. 717 */ 718 bo_ptr->tbo.destroy = &amdgpu_bo_vm_destroy; 719 return r; 720 } 721 722 /** 723 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 724 * 725 * @vmbo: BO that will be inserted into the shadow list 726 * 727 * Insert a BO to the shadow list. 728 */ 729 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 730 { 731 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 732 733 mutex_lock(&adev->shadow_list_lock); 734 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 735 mutex_unlock(&adev->shadow_list_lock); 736 } 737 738 /** 739 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 740 * 741 * @shadow: &amdgpu_bo shadow to be restored 742 * @fence: dma_fence associated with the operation 743 * 744 * Copies a buffer object's shadow content back to the object. 745 * This is used for recovering a buffer from its shadow in case of a gpu 746 * reset where vram context may be lost. 747 * 748 * Returns: 749 * 0 for success or a negative error code on failure. 750 */ 751 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 752 753 { 754 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 755 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 756 uint64_t shadow_addr, parent_addr; 757 758 shadow_addr = amdgpu_bo_gpu_offset(shadow); 759 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 760 761 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 762 amdgpu_bo_size(shadow), NULL, fence, 763 true, false, false); 764 } 765 766 /** 767 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 768 * @bo: &amdgpu_bo buffer object to be mapped 769 * @ptr: kernel virtual address to be returned 770 * 771 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 772 * amdgpu_bo_kptr() to get the kernel virtual address. 773 * 774 * Returns: 775 * 0 for success or a negative error code on failure. 776 */ 777 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 778 { 779 void *kptr; 780 long r; 781 782 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 783 return -EPERM; 784 785 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 786 false, MAX_SCHEDULE_TIMEOUT); 787 if (r < 0) 788 return r; 789 790 kptr = amdgpu_bo_kptr(bo); 791 if (kptr) { 792 if (ptr) 793 *ptr = kptr; 794 return 0; 795 } 796 797 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 798 if (r) 799 return r; 800 801 if (ptr) 802 *ptr = amdgpu_bo_kptr(bo); 803 804 return 0; 805 } 806 807 /** 808 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 809 * @bo: &amdgpu_bo buffer object 810 * 811 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 812 * 813 * Returns: 814 * the virtual address of a buffer object area. 815 */ 816 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 817 { 818 bool is_iomem; 819 820 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 821 } 822 823 /** 824 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 825 * @bo: &amdgpu_bo buffer object to be unmapped 826 * 827 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 828 */ 829 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 830 { 831 if (bo->kmap.bo) 832 ttm_bo_kunmap(&bo->kmap); 833 } 834 835 /** 836 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 837 * @bo: &amdgpu_bo buffer object 838 * 839 * References the contained &ttm_buffer_object. 840 * 841 * Returns: 842 * a refcounted pointer to the &amdgpu_bo buffer object. 843 */ 844 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 845 { 846 if (bo == NULL) 847 return NULL; 848 849 ttm_bo_get(&bo->tbo); 850 return bo; 851 } 852 853 /** 854 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 855 * @bo: &amdgpu_bo buffer object 856 * 857 * Unreferences the contained &ttm_buffer_object and clear the pointer 858 */ 859 void amdgpu_bo_unref(struct amdgpu_bo **bo) 860 { 861 struct ttm_buffer_object *tbo; 862 863 if ((*bo) == NULL) 864 return; 865 866 tbo = &((*bo)->tbo); 867 ttm_bo_put(tbo); 868 *bo = NULL; 869 } 870 871 /** 872 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 873 * @bo: &amdgpu_bo buffer object to be pinned 874 * @domain: domain to be pinned to 875 * @min_offset: the start of requested address range 876 * @max_offset: the end of requested address range 877 * 878 * Pins the buffer object according to requested domain and address range. If 879 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 880 * pin_count and pin_size accordingly. 881 * 882 * Pinning means to lock pages in memory along with keeping them at a fixed 883 * offset. It is required when a buffer can not be moved, for example, when 884 * a display buffer is being scanned out. 885 * 886 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 887 * where to pin a buffer if there are specific restrictions on where a buffer 888 * must be located. 889 * 890 * Returns: 891 * 0 for success or a negative error code on failure. 892 */ 893 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 894 u64 min_offset, u64 max_offset) 895 { 896 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 897 struct ttm_operation_ctx ctx = { false, false }; 898 int r, i; 899 900 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 901 return -EPERM; 902 903 if (WARN_ON_ONCE(min_offset > max_offset)) 904 return -EINVAL; 905 906 /* Check domain to be pinned to against preferred domains */ 907 if (bo->preferred_domains & domain) 908 domain = bo->preferred_domains & domain; 909 910 /* A shared bo cannot be migrated to VRAM */ 911 if (bo->tbo.base.import_attach) { 912 if (domain & AMDGPU_GEM_DOMAIN_GTT) 913 domain = AMDGPU_GEM_DOMAIN_GTT; 914 else 915 return -EINVAL; 916 } 917 918 if (bo->tbo.pin_count) { 919 uint32_t mem_type = bo->tbo.resource->mem_type; 920 uint32_t mem_flags = bo->tbo.resource->placement; 921 922 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 923 return -EINVAL; 924 925 if ((mem_type == TTM_PL_VRAM) && 926 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 927 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 928 return -EINVAL; 929 930 ttm_bo_pin(&bo->tbo); 931 932 if (max_offset != 0) { 933 u64 domain_start = amdgpu_ttm_domain_start(adev, 934 mem_type); 935 WARN_ON_ONCE(max_offset < 936 (amdgpu_bo_gpu_offset(bo) - domain_start)); 937 } 938 939 return 0; 940 } 941 942 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 943 * See function amdgpu_display_supported_domains() 944 */ 945 domain = amdgpu_bo_get_preferred_domain(adev, domain); 946 947 if (bo->tbo.base.import_attach) 948 dma_buf_pin(bo->tbo.base.import_attach); 949 950 /* force to pin into visible video ram */ 951 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 952 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 953 amdgpu_bo_placement_from_domain(bo, domain); 954 for (i = 0; i < bo->placement.num_placement; i++) { 955 unsigned int fpfn, lpfn; 956 957 fpfn = min_offset >> PAGE_SHIFT; 958 lpfn = max_offset >> PAGE_SHIFT; 959 960 if (fpfn > bo->placements[i].fpfn) 961 bo->placements[i].fpfn = fpfn; 962 if (!bo->placements[i].lpfn || 963 (lpfn && lpfn < bo->placements[i].lpfn)) 964 bo->placements[i].lpfn = lpfn; 965 } 966 967 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 968 if (unlikely(r)) { 969 dev_err(adev->dev, "%p pin failed\n", bo); 970 goto error; 971 } 972 973 ttm_bo_pin(&bo->tbo); 974 975 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 976 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 977 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 978 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 979 &adev->visible_pin_size); 980 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 981 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 982 } 983 984 error: 985 return r; 986 } 987 988 /** 989 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 990 * @bo: &amdgpu_bo buffer object to be pinned 991 * @domain: domain to be pinned to 992 * 993 * A simple wrapper to amdgpu_bo_pin_restricted(). 994 * Provides a simpler API for buffers that do not have any strict restrictions 995 * on where a buffer must be located. 996 * 997 * Returns: 998 * 0 for success or a negative error code on failure. 999 */ 1000 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 1001 { 1002 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1003 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 1004 } 1005 1006 /** 1007 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 1008 * @bo: &amdgpu_bo buffer object to be unpinned 1009 * 1010 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 1011 * Changes placement and pin size accordingly. 1012 * 1013 * Returns: 1014 * 0 for success or a negative error code on failure. 1015 */ 1016 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1017 { 1018 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1019 1020 ttm_bo_unpin(&bo->tbo); 1021 if (bo->tbo.pin_count) 1022 return; 1023 1024 if (bo->tbo.base.import_attach) 1025 dma_buf_unpin(bo->tbo.base.import_attach); 1026 1027 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1028 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1029 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1030 &adev->visible_pin_size); 1031 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1032 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1033 } 1034 } 1035 1036 static const char * const amdgpu_vram_names[] = { 1037 "UNKNOWN", 1038 "GDDR1", 1039 "DDR2", 1040 "GDDR3", 1041 "GDDR4", 1042 "GDDR5", 1043 "HBM", 1044 "DDR3", 1045 "DDR4", 1046 "GDDR6", 1047 "DDR5", 1048 "LPDDR4", 1049 "LPDDR5" 1050 }; 1051 1052 /** 1053 * amdgpu_bo_init - initialize memory manager 1054 * @adev: amdgpu device object 1055 * 1056 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1057 * 1058 * Returns: 1059 * 0 for success or a negative error code on failure. 1060 */ 1061 int amdgpu_bo_init(struct amdgpu_device *adev) 1062 { 1063 /* On A+A platform, VRAM can be mapped as WB */ 1064 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1065 /* reserve PAT memory space to WC for VRAM */ 1066 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1067 adev->gmc.aper_size); 1068 1069 if (r) { 1070 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1071 return r; 1072 } 1073 1074 /* Add an MTRR for the VRAM */ 1075 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1076 adev->gmc.aper_size); 1077 } 1078 1079 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1080 adev->gmc.mc_vram_size >> 20, 1081 (unsigned long long)adev->gmc.aper_size >> 20); 1082 DRM_INFO("RAM width %dbits %s\n", 1083 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1084 return amdgpu_ttm_init(adev); 1085 } 1086 1087 /** 1088 * amdgpu_bo_fini - tear down memory manager 1089 * @adev: amdgpu device object 1090 * 1091 * Reverses amdgpu_bo_init() to tear down memory manager. 1092 */ 1093 void amdgpu_bo_fini(struct amdgpu_device *adev) 1094 { 1095 int idx; 1096 1097 amdgpu_ttm_fini(adev); 1098 1099 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1100 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1101 arch_phys_wc_del(adev->gmc.vram_mtrr); 1102 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1103 } 1104 drm_dev_exit(idx); 1105 } 1106 } 1107 1108 /** 1109 * amdgpu_bo_set_tiling_flags - set tiling flags 1110 * @bo: &amdgpu_bo buffer object 1111 * @tiling_flags: new flags 1112 * 1113 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1114 * kernel driver to set the tiling flags on a buffer. 1115 * 1116 * Returns: 1117 * 0 for success or a negative error code on failure. 1118 */ 1119 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1120 { 1121 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1122 struct amdgpu_bo_user *ubo; 1123 1124 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1125 if (adev->family <= AMDGPU_FAMILY_CZ && 1126 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1127 return -EINVAL; 1128 1129 ubo = to_amdgpu_bo_user(bo); 1130 ubo->tiling_flags = tiling_flags; 1131 return 0; 1132 } 1133 1134 /** 1135 * amdgpu_bo_get_tiling_flags - get tiling flags 1136 * @bo: &amdgpu_bo buffer object 1137 * @tiling_flags: returned flags 1138 * 1139 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1140 * set the tiling flags on a buffer. 1141 */ 1142 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1143 { 1144 struct amdgpu_bo_user *ubo; 1145 1146 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1147 dma_resv_assert_held(bo->tbo.base.resv); 1148 ubo = to_amdgpu_bo_user(bo); 1149 1150 if (tiling_flags) 1151 *tiling_flags = ubo->tiling_flags; 1152 } 1153 1154 /** 1155 * amdgpu_bo_set_metadata - set metadata 1156 * @bo: &amdgpu_bo buffer object 1157 * @metadata: new metadata 1158 * @metadata_size: size of the new metadata 1159 * @flags: flags of the new metadata 1160 * 1161 * Sets buffer object's metadata, its size and flags. 1162 * Used via GEM ioctl. 1163 * 1164 * Returns: 1165 * 0 for success or a negative error code on failure. 1166 */ 1167 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata, 1168 u32 metadata_size, uint64_t flags) 1169 { 1170 struct amdgpu_bo_user *ubo; 1171 void *buffer; 1172 1173 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1174 ubo = to_amdgpu_bo_user(bo); 1175 if (!metadata_size) { 1176 if (ubo->metadata_size) { 1177 kfree(ubo->metadata); 1178 ubo->metadata = NULL; 1179 ubo->metadata_size = 0; 1180 } 1181 return 0; 1182 } 1183 1184 if (metadata == NULL) 1185 return -EINVAL; 1186 1187 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1188 if (buffer == NULL) 1189 return -ENOMEM; 1190 1191 kfree(ubo->metadata); 1192 ubo->metadata_flags = flags; 1193 ubo->metadata = buffer; 1194 ubo->metadata_size = metadata_size; 1195 1196 return 0; 1197 } 1198 1199 /** 1200 * amdgpu_bo_get_metadata - get metadata 1201 * @bo: &amdgpu_bo buffer object 1202 * @buffer: returned metadata 1203 * @buffer_size: size of the buffer 1204 * @metadata_size: size of the returned metadata 1205 * @flags: flags of the returned metadata 1206 * 1207 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1208 * less than metadata_size. 1209 * Used via GEM ioctl. 1210 * 1211 * Returns: 1212 * 0 for success or a negative error code on failure. 1213 */ 1214 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1215 size_t buffer_size, uint32_t *metadata_size, 1216 uint64_t *flags) 1217 { 1218 struct amdgpu_bo_user *ubo; 1219 1220 if (!buffer && !metadata_size) 1221 return -EINVAL; 1222 1223 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1224 ubo = to_amdgpu_bo_user(bo); 1225 if (metadata_size) 1226 *metadata_size = ubo->metadata_size; 1227 1228 if (buffer) { 1229 if (buffer_size < ubo->metadata_size) 1230 return -EINVAL; 1231 1232 if (ubo->metadata_size) 1233 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1234 } 1235 1236 if (flags) 1237 *flags = ubo->metadata_flags; 1238 1239 return 0; 1240 } 1241 1242 /** 1243 * amdgpu_bo_move_notify - notification about a memory move 1244 * @bo: pointer to a buffer object 1245 * @evict: if this move is evicting the buffer from the graphics address space 1246 * @new_mem: new information of the bufer object 1247 * 1248 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1249 * bookkeeping. 1250 * TTM driver callback which is called when ttm moves a buffer. 1251 */ 1252 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1253 bool evict, 1254 struct ttm_resource *new_mem) 1255 { 1256 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1257 struct amdgpu_bo *abo; 1258 struct ttm_resource *old_mem = bo->resource; 1259 1260 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1261 return; 1262 1263 abo = ttm_to_amdgpu_bo(bo); 1264 amdgpu_vm_bo_invalidate(adev, abo, evict); 1265 1266 amdgpu_bo_kunmap(abo); 1267 1268 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1269 bo->resource->mem_type != TTM_PL_SYSTEM) 1270 dma_buf_move_notify(abo->tbo.base.dma_buf); 1271 1272 /* remember the eviction */ 1273 if (evict) 1274 atomic64_inc(&adev->num_evictions); 1275 1276 /* update statistics */ 1277 if (!new_mem) 1278 return; 1279 1280 /* move_notify is called before move happens */ 1281 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1282 } 1283 1284 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, 1285 struct amdgpu_mem_stats *stats) 1286 { 1287 unsigned int domain; 1288 uint64_t size = amdgpu_bo_size(bo); 1289 1290 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1291 switch (domain) { 1292 case AMDGPU_GEM_DOMAIN_VRAM: 1293 stats->vram += size; 1294 if (amdgpu_bo_in_cpu_visible_vram(bo)) 1295 stats->visible_vram += size; 1296 break; 1297 case AMDGPU_GEM_DOMAIN_GTT: 1298 stats->gtt += size; 1299 break; 1300 case AMDGPU_GEM_DOMAIN_CPU: 1301 default: 1302 stats->cpu += size; 1303 break; 1304 } 1305 1306 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) { 1307 stats->requested_vram += size; 1308 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1309 stats->requested_visible_vram += size; 1310 1311 if (domain != AMDGPU_GEM_DOMAIN_VRAM) { 1312 stats->evicted_vram += size; 1313 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1314 stats->evicted_visible_vram += size; 1315 } 1316 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) { 1317 stats->requested_gtt += size; 1318 } 1319 } 1320 1321 /** 1322 * amdgpu_bo_release_notify - notification about a BO being released 1323 * @bo: pointer to a buffer object 1324 * 1325 * Wipes VRAM buffers whose contents should not be leaked before the 1326 * memory is released. 1327 */ 1328 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1329 { 1330 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1331 struct dma_fence *fence = NULL; 1332 struct amdgpu_bo *abo; 1333 int r; 1334 1335 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1336 return; 1337 1338 abo = ttm_to_amdgpu_bo(bo); 1339 1340 if (abo->kfd_bo) 1341 amdgpu_amdkfd_release_notify(abo); 1342 1343 /* We only remove the fence if the resv has individualized. */ 1344 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1345 && bo->base.resv != &bo->base._resv); 1346 if (bo->base.resv == &bo->base._resv) 1347 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1348 1349 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1350 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1351 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1352 return; 1353 1354 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1355 return; 1356 1357 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1358 if (!WARN_ON(r)) { 1359 amdgpu_bo_fence(abo, fence, false); 1360 dma_fence_put(fence); 1361 } 1362 1363 dma_resv_unlock(bo->base.resv); 1364 } 1365 1366 /** 1367 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1368 * @bo: pointer to a buffer object 1369 * 1370 * Notifies the driver we are taking a fault on this BO and have reserved it, 1371 * also performs bookkeeping. 1372 * TTM driver callback for dealing with vm faults. 1373 * 1374 * Returns: 1375 * 0 for success or a negative error code on failure. 1376 */ 1377 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1378 { 1379 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1380 struct ttm_operation_ctx ctx = { false, false }; 1381 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1382 int r; 1383 1384 /* Remember that this BO was accessed by the CPU */ 1385 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1386 1387 if (bo->resource->mem_type != TTM_PL_VRAM) 1388 return 0; 1389 1390 if (amdgpu_bo_in_cpu_visible_vram(abo)) 1391 return 0; 1392 1393 /* Can't move a pinned BO to visible VRAM */ 1394 if (abo->tbo.pin_count > 0) 1395 return VM_FAULT_SIGBUS; 1396 1397 /* hurrah the memory is not visible ! */ 1398 atomic64_inc(&adev->num_vram_cpu_page_faults); 1399 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1400 AMDGPU_GEM_DOMAIN_GTT); 1401 1402 /* Avoid costly evictions; only set GTT as a busy placement */ 1403 abo->placement.num_busy_placement = 1; 1404 abo->placement.busy_placement = &abo->placements[1]; 1405 1406 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1407 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1408 return VM_FAULT_NOPAGE; 1409 else if (unlikely(r)) 1410 return VM_FAULT_SIGBUS; 1411 1412 /* this should never happen */ 1413 if (bo->resource->mem_type == TTM_PL_VRAM && 1414 !amdgpu_bo_in_cpu_visible_vram(abo)) 1415 return VM_FAULT_SIGBUS; 1416 1417 ttm_bo_move_to_lru_tail_unlocked(bo); 1418 return 0; 1419 } 1420 1421 /** 1422 * amdgpu_bo_fence - add fence to buffer object 1423 * 1424 * @bo: buffer object in question 1425 * @fence: fence to add 1426 * @shared: true if fence should be added shared 1427 * 1428 */ 1429 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1430 bool shared) 1431 { 1432 struct dma_resv *resv = bo->tbo.base.resv; 1433 int r; 1434 1435 r = dma_resv_reserve_fences(resv, 1); 1436 if (r) { 1437 /* As last resort on OOM we block for the fence */ 1438 dma_fence_wait(fence, false); 1439 return; 1440 } 1441 1442 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1443 DMA_RESV_USAGE_WRITE); 1444 } 1445 1446 /** 1447 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1448 * 1449 * @adev: amdgpu device pointer 1450 * @resv: reservation object to sync to 1451 * @sync_mode: synchronization mode 1452 * @owner: fence owner 1453 * @intr: Whether the wait is interruptible 1454 * 1455 * Extract the fences from the reservation object and waits for them to finish. 1456 * 1457 * Returns: 1458 * 0 on success, errno otherwise. 1459 */ 1460 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1461 enum amdgpu_sync_mode sync_mode, void *owner, 1462 bool intr) 1463 { 1464 struct amdgpu_sync sync; 1465 int r; 1466 1467 amdgpu_sync_create(&sync); 1468 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1469 r = amdgpu_sync_wait(&sync, intr); 1470 amdgpu_sync_free(&sync); 1471 return r; 1472 } 1473 1474 /** 1475 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1476 * @bo: buffer object to wait for 1477 * @owner: fence owner 1478 * @intr: Whether the wait is interruptible 1479 * 1480 * Wrapper to wait for fences in a BO. 1481 * Returns: 1482 * 0 on success, errno otherwise. 1483 */ 1484 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1485 { 1486 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1487 1488 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1489 AMDGPU_SYNC_NE_OWNER, owner, intr); 1490 } 1491 1492 /** 1493 * amdgpu_bo_gpu_offset - return GPU offset of bo 1494 * @bo: amdgpu object for which we query the offset 1495 * 1496 * Note: object should either be pinned or reserved when calling this 1497 * function, it might be useful to add check for this for debugging. 1498 * 1499 * Returns: 1500 * current GPU offset of the object. 1501 */ 1502 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1503 { 1504 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1505 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1506 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1507 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1508 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1509 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1510 1511 return amdgpu_bo_gpu_offset_no_check(bo); 1512 } 1513 1514 /** 1515 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1516 * @bo: amdgpu object for which we query the offset 1517 * 1518 * Returns: 1519 * current GPU offset of the object without raising warnings. 1520 */ 1521 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1522 { 1523 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1524 uint64_t offset; 1525 1526 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1527 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1528 1529 return amdgpu_gmc_sign_extend(offset); 1530 } 1531 1532 /** 1533 * amdgpu_bo_get_preferred_domain - get preferred domain 1534 * @adev: amdgpu device object 1535 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1536 * 1537 * Returns: 1538 * Which of the allowed domains is preferred for allocating the BO. 1539 */ 1540 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1541 uint32_t domain) 1542 { 1543 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1544 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1545 domain = AMDGPU_GEM_DOMAIN_VRAM; 1546 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1547 domain = AMDGPU_GEM_DOMAIN_GTT; 1548 } 1549 return domain; 1550 } 1551 1552 #if defined(CONFIG_DEBUG_FS) 1553 #define amdgpu_bo_print_flag(m, bo, flag) \ 1554 do { \ 1555 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1556 seq_printf((m), " " #flag); \ 1557 } \ 1558 } while (0) 1559 1560 /** 1561 * amdgpu_bo_print_info - print BO info in debugfs file 1562 * 1563 * @id: Index or Id of the BO 1564 * @bo: Requested BO for printing info 1565 * @m: debugfs file 1566 * 1567 * Print BO information in debugfs file 1568 * 1569 * Returns: 1570 * Size of the BO in bytes. 1571 */ 1572 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1573 { 1574 struct dma_buf_attachment *attachment; 1575 struct dma_buf *dma_buf; 1576 unsigned int domain; 1577 const char *placement; 1578 unsigned int pin_count; 1579 u64 size; 1580 1581 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1582 switch (domain) { 1583 case AMDGPU_GEM_DOMAIN_VRAM: 1584 placement = "VRAM"; 1585 break; 1586 case AMDGPU_GEM_DOMAIN_GTT: 1587 placement = " GTT"; 1588 break; 1589 case AMDGPU_GEM_DOMAIN_CPU: 1590 default: 1591 placement = " CPU"; 1592 break; 1593 } 1594 1595 size = amdgpu_bo_size(bo); 1596 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1597 id, size, placement); 1598 1599 pin_count = READ_ONCE(bo->tbo.pin_count); 1600 if (pin_count) 1601 seq_printf(m, " pin count %d", pin_count); 1602 1603 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1604 attachment = READ_ONCE(bo->tbo.base.import_attach); 1605 1606 if (attachment) 1607 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino); 1608 else if (dma_buf) 1609 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino); 1610 1611 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1612 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1613 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1614 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1615 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1616 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1617 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1618 1619 seq_puts(m, "\n"); 1620 1621 return size; 1622 } 1623 #endif 1624