1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include "amdgpu.h" 37 #include "amdgpu_trace.h" 38 39 40 int amdgpu_ttm_init(struct amdgpu_device *adev); 41 void amdgpu_ttm_fini(struct amdgpu_device *adev); 42 43 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, 44 struct ttm_mem_reg *mem) 45 { 46 u64 ret = 0; 47 if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) { 48 ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) > 49 adev->mc.visible_vram_size ? 50 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : 51 mem->size; 52 } 53 return ret; 54 } 55 56 static void amdgpu_update_memory_usage(struct amdgpu_device *adev, 57 struct ttm_mem_reg *old_mem, 58 struct ttm_mem_reg *new_mem) 59 { 60 u64 vis_size; 61 if (!adev) 62 return; 63 64 if (new_mem) { 65 switch (new_mem->mem_type) { 66 case TTM_PL_TT: 67 atomic64_add(new_mem->size, &adev->gtt_usage); 68 break; 69 case TTM_PL_VRAM: 70 atomic64_add(new_mem->size, &adev->vram_usage); 71 vis_size = amdgpu_get_vis_part_size(adev, new_mem); 72 atomic64_add(vis_size, &adev->vram_vis_usage); 73 break; 74 } 75 } 76 77 if (old_mem) { 78 switch (old_mem->mem_type) { 79 case TTM_PL_TT: 80 atomic64_sub(old_mem->size, &adev->gtt_usage); 81 break; 82 case TTM_PL_VRAM: 83 atomic64_sub(old_mem->size, &adev->vram_usage); 84 vis_size = amdgpu_get_vis_part_size(adev, old_mem); 85 atomic64_sub(vis_size, &adev->vram_vis_usage); 86 break; 87 } 88 } 89 } 90 91 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 92 { 93 struct amdgpu_bo *bo; 94 95 bo = container_of(tbo, struct amdgpu_bo, tbo); 96 97 amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); 98 99 mutex_lock(&bo->adev->gem.mutex); 100 list_del_init(&bo->list); 101 mutex_unlock(&bo->adev->gem.mutex); 102 drm_gem_object_release(&bo->gem_base); 103 kfree(bo->metadata); 104 kfree(bo); 105 } 106 107 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 108 { 109 if (bo->destroy == &amdgpu_ttm_bo_destroy) 110 return true; 111 return false; 112 } 113 114 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 115 struct ttm_placement *placement, 116 struct ttm_place *placements, 117 u32 domain, u64 flags) 118 { 119 u32 c = 0, i; 120 121 placement->placement = placements; 122 placement->busy_placement = placements; 123 124 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 125 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && 126 adev->mc.visible_vram_size < adev->mc.real_vram_size) { 127 placements[c].fpfn = 128 adev->mc.visible_vram_size >> PAGE_SHIFT; 129 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 130 TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN; 131 } 132 placements[c].fpfn = 0; 133 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 134 TTM_PL_FLAG_VRAM; 135 } 136 137 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 138 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 139 placements[c].fpfn = 0; 140 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | 141 TTM_PL_FLAG_UNCACHED; 142 } else { 143 placements[c].fpfn = 0; 144 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 145 } 146 } 147 148 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 149 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 150 placements[c].fpfn = 0; 151 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | 152 TTM_PL_FLAG_UNCACHED; 153 } else { 154 placements[c].fpfn = 0; 155 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 156 } 157 } 158 159 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 160 placements[c].fpfn = 0; 161 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 162 AMDGPU_PL_FLAG_GDS; 163 } 164 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 165 placements[c].fpfn = 0; 166 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 167 AMDGPU_PL_FLAG_GWS; 168 } 169 if (domain & AMDGPU_GEM_DOMAIN_OA) { 170 placements[c].fpfn = 0; 171 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 172 AMDGPU_PL_FLAG_OA; 173 } 174 175 if (!c) { 176 placements[c].fpfn = 0; 177 placements[c++].flags = TTM_PL_MASK_CACHING | 178 TTM_PL_FLAG_SYSTEM; 179 } 180 placement->num_placement = c; 181 placement->num_busy_placement = c; 182 183 for (i = 0; i < c; i++) { 184 if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 185 (placements[i].flags & TTM_PL_FLAG_VRAM) && 186 !placements[i].fpfn) 187 placements[i].lpfn = 188 adev->mc.visible_vram_size >> PAGE_SHIFT; 189 else 190 placements[i].lpfn = 0; 191 } 192 } 193 194 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) 195 { 196 amdgpu_ttm_placement_init(rbo->adev, &rbo->placement, 197 rbo->placements, domain, rbo->flags); 198 } 199 200 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 201 struct ttm_placement *placement) 202 { 203 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 204 205 memcpy(bo->placements, placement->placement, 206 placement->num_placement * sizeof(struct ttm_place)); 207 bo->placement.num_placement = placement->num_placement; 208 bo->placement.num_busy_placement = placement->num_busy_placement; 209 bo->placement.placement = bo->placements; 210 bo->placement.busy_placement = bo->placements; 211 } 212 213 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 214 unsigned long size, int byte_align, 215 bool kernel, u32 domain, u64 flags, 216 struct sg_table *sg, 217 struct ttm_placement *placement, 218 struct amdgpu_bo **bo_ptr) 219 { 220 struct amdgpu_bo *bo; 221 enum ttm_bo_type type; 222 unsigned long page_align; 223 size_t acc_size; 224 int r; 225 226 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 227 size = ALIGN(size, PAGE_SIZE); 228 229 if (kernel) { 230 type = ttm_bo_type_kernel; 231 } else if (sg) { 232 type = ttm_bo_type_sg; 233 } else { 234 type = ttm_bo_type_device; 235 } 236 *bo_ptr = NULL; 237 238 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 239 sizeof(struct amdgpu_bo)); 240 241 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 242 if (bo == NULL) 243 return -ENOMEM; 244 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 245 if (unlikely(r)) { 246 kfree(bo); 247 return r; 248 } 249 bo->adev = adev; 250 INIT_LIST_HEAD(&bo->list); 251 INIT_LIST_HEAD(&bo->va); 252 bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM | 253 AMDGPU_GEM_DOMAIN_GTT | 254 AMDGPU_GEM_DOMAIN_CPU | 255 AMDGPU_GEM_DOMAIN_GDS | 256 AMDGPU_GEM_DOMAIN_GWS | 257 AMDGPU_GEM_DOMAIN_OA); 258 259 bo->flags = flags; 260 amdgpu_fill_placement_to_bo(bo, placement); 261 /* Kernel allocation are uninterruptible */ 262 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 263 &bo->placement, page_align, !kernel, NULL, 264 acc_size, sg, NULL, &amdgpu_ttm_bo_destroy); 265 if (unlikely(r != 0)) { 266 return r; 267 } 268 *bo_ptr = bo; 269 270 trace_amdgpu_bo_create(bo); 271 272 return 0; 273 } 274 275 int amdgpu_bo_create(struct amdgpu_device *adev, 276 unsigned long size, int byte_align, 277 bool kernel, u32 domain, u64 flags, 278 struct sg_table *sg, struct amdgpu_bo **bo_ptr) 279 { 280 struct ttm_placement placement = {0}; 281 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 282 283 memset(&placements, 0, 284 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 285 286 amdgpu_ttm_placement_init(adev, &placement, 287 placements, domain, flags); 288 289 return amdgpu_bo_create_restricted(adev, size, byte_align, 290 kernel, domain, flags, 291 sg, 292 &placement, 293 bo_ptr); 294 } 295 296 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 297 { 298 bool is_iomem; 299 int r; 300 301 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 302 return -EPERM; 303 304 if (bo->kptr) { 305 if (ptr) { 306 *ptr = bo->kptr; 307 } 308 return 0; 309 } 310 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 311 if (r) { 312 return r; 313 } 314 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 315 if (ptr) { 316 *ptr = bo->kptr; 317 } 318 return 0; 319 } 320 321 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 322 { 323 if (bo->kptr == NULL) 324 return; 325 bo->kptr = NULL; 326 ttm_bo_kunmap(&bo->kmap); 327 } 328 329 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 330 { 331 if (bo == NULL) 332 return NULL; 333 334 ttm_bo_reference(&bo->tbo); 335 return bo; 336 } 337 338 void amdgpu_bo_unref(struct amdgpu_bo **bo) 339 { 340 struct ttm_buffer_object *tbo; 341 342 if ((*bo) == NULL) 343 return; 344 345 tbo = &((*bo)->tbo); 346 ttm_bo_unref(&tbo); 347 if (tbo == NULL) 348 *bo = NULL; 349 } 350 351 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 352 u64 min_offset, u64 max_offset, 353 u64 *gpu_addr) 354 { 355 int r, i; 356 unsigned fpfn, lpfn; 357 358 if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm)) 359 return -EPERM; 360 361 if (WARN_ON_ONCE(min_offset > max_offset)) 362 return -EINVAL; 363 364 if (bo->pin_count) { 365 bo->pin_count++; 366 if (gpu_addr) 367 *gpu_addr = amdgpu_bo_gpu_offset(bo); 368 369 if (max_offset != 0) { 370 u64 domain_start; 371 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 372 domain_start = bo->adev->mc.vram_start; 373 else 374 domain_start = bo->adev->mc.gtt_start; 375 WARN_ON_ONCE(max_offset < 376 (amdgpu_bo_gpu_offset(bo) - domain_start)); 377 } 378 379 return 0; 380 } 381 amdgpu_ttm_placement_from_domain(bo, domain); 382 for (i = 0; i < bo->placement.num_placement; i++) { 383 /* force to pin into visible video ram */ 384 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 385 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 386 (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) { 387 if (WARN_ON_ONCE(min_offset > 388 bo->adev->mc.visible_vram_size)) 389 return -EINVAL; 390 fpfn = min_offset >> PAGE_SHIFT; 391 lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT; 392 } else { 393 fpfn = min_offset >> PAGE_SHIFT; 394 lpfn = max_offset >> PAGE_SHIFT; 395 } 396 if (fpfn > bo->placements[i].fpfn) 397 bo->placements[i].fpfn = fpfn; 398 if (lpfn && lpfn < bo->placements[i].lpfn) 399 bo->placements[i].lpfn = lpfn; 400 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 401 } 402 403 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 404 if (likely(r == 0)) { 405 bo->pin_count = 1; 406 if (gpu_addr != NULL) 407 *gpu_addr = amdgpu_bo_gpu_offset(bo); 408 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 409 bo->adev->vram_pin_size += amdgpu_bo_size(bo); 410 else 411 bo->adev->gart_pin_size += amdgpu_bo_size(bo); 412 } else { 413 dev_err(bo->adev->dev, "%p pin failed\n", bo); 414 } 415 return r; 416 } 417 418 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 419 { 420 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 421 } 422 423 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 424 { 425 int r, i; 426 427 if (!bo->pin_count) { 428 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo); 429 return 0; 430 } 431 bo->pin_count--; 432 if (bo->pin_count) 433 return 0; 434 for (i = 0; i < bo->placement.num_placement; i++) { 435 bo->placements[i].lpfn = 0; 436 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 437 } 438 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 439 if (likely(r == 0)) { 440 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 441 bo->adev->vram_pin_size -= amdgpu_bo_size(bo); 442 else 443 bo->adev->gart_pin_size -= amdgpu_bo_size(bo); 444 } else { 445 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo); 446 } 447 return r; 448 } 449 450 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 451 { 452 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 453 if (0 && (adev->flags & AMD_IS_APU)) { 454 /* Useless to evict on IGP chips */ 455 return 0; 456 } 457 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 458 } 459 460 void amdgpu_bo_force_delete(struct amdgpu_device *adev) 461 { 462 struct amdgpu_bo *bo, *n; 463 464 if (list_empty(&adev->gem.objects)) { 465 return; 466 } 467 dev_err(adev->dev, "Userspace still has active objects !\n"); 468 list_for_each_entry_safe(bo, n, &adev->gem.objects, list) { 469 dev_err(adev->dev, "%p %p %lu %lu force free\n", 470 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 471 *((unsigned long *)&bo->gem_base.refcount)); 472 mutex_lock(&bo->adev->gem.mutex); 473 list_del_init(&bo->list); 474 mutex_unlock(&bo->adev->gem.mutex); 475 /* this should unref the ttm bo */ 476 drm_gem_object_unreference_unlocked(&bo->gem_base); 477 } 478 } 479 480 int amdgpu_bo_init(struct amdgpu_device *adev) 481 { 482 /* Add an MTRR for the VRAM */ 483 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 484 adev->mc.aper_size); 485 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 486 adev->mc.mc_vram_size >> 20, 487 (unsigned long long)adev->mc.aper_size >> 20); 488 DRM_INFO("RAM width %dbits DDR\n", 489 adev->mc.vram_width); 490 return amdgpu_ttm_init(adev); 491 } 492 493 void amdgpu_bo_fini(struct amdgpu_device *adev) 494 { 495 amdgpu_ttm_fini(adev); 496 arch_phys_wc_del(adev->mc.vram_mtrr); 497 } 498 499 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 500 struct vm_area_struct *vma) 501 { 502 return ttm_fbdev_mmap(vma, &bo->tbo); 503 } 504 505 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 506 { 507 if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 508 return -EINVAL; 509 510 bo->tiling_flags = tiling_flags; 511 return 0; 512 } 513 514 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 515 { 516 lockdep_assert_held(&bo->tbo.resv->lock.base); 517 518 if (tiling_flags) 519 *tiling_flags = bo->tiling_flags; 520 } 521 522 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 523 uint32_t metadata_size, uint64_t flags) 524 { 525 void *buffer; 526 527 if (!metadata_size) { 528 if (bo->metadata_size) { 529 kfree(bo->metadata); 530 bo->metadata_size = 0; 531 } 532 return 0; 533 } 534 535 if (metadata == NULL) 536 return -EINVAL; 537 538 buffer = kzalloc(metadata_size, GFP_KERNEL); 539 if (buffer == NULL) 540 return -ENOMEM; 541 542 memcpy(buffer, metadata, metadata_size); 543 544 kfree(bo->metadata); 545 bo->metadata_flags = flags; 546 bo->metadata = buffer; 547 bo->metadata_size = metadata_size; 548 549 return 0; 550 } 551 552 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 553 size_t buffer_size, uint32_t *metadata_size, 554 uint64_t *flags) 555 { 556 if (!buffer && !metadata_size) 557 return -EINVAL; 558 559 if (buffer) { 560 if (buffer_size < bo->metadata_size) 561 return -EINVAL; 562 563 if (bo->metadata_size) 564 memcpy(buffer, bo->metadata, bo->metadata_size); 565 } 566 567 if (metadata_size) 568 *metadata_size = bo->metadata_size; 569 if (flags) 570 *flags = bo->metadata_flags; 571 572 return 0; 573 } 574 575 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 576 struct ttm_mem_reg *new_mem) 577 { 578 struct amdgpu_bo *rbo; 579 580 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 581 return; 582 583 rbo = container_of(bo, struct amdgpu_bo, tbo); 584 amdgpu_vm_bo_invalidate(rbo->adev, rbo); 585 586 /* update statistics */ 587 if (!new_mem) 588 return; 589 590 /* move_notify is called before move happens */ 591 amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem); 592 } 593 594 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 595 { 596 struct amdgpu_device *adev; 597 struct amdgpu_bo *abo; 598 unsigned long offset, size, lpfn; 599 int i, r; 600 601 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 602 return 0; 603 604 abo = container_of(bo, struct amdgpu_bo, tbo); 605 adev = abo->adev; 606 if (bo->mem.mem_type != TTM_PL_VRAM) 607 return 0; 608 609 size = bo->mem.num_pages << PAGE_SHIFT; 610 offset = bo->mem.start << PAGE_SHIFT; 611 if ((offset + size) <= adev->mc.visible_vram_size) 612 return 0; 613 614 /* hurrah the memory is not visible ! */ 615 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); 616 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 617 for (i = 0; i < abo->placement.num_placement; i++) { 618 /* Force into visible VRAM */ 619 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && 620 (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn)) 621 abo->placements[i].lpfn = lpfn; 622 } 623 r = ttm_bo_validate(bo, &abo->placement, false, false); 624 if (unlikely(r == -ENOMEM)) { 625 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 626 return ttm_bo_validate(bo, &abo->placement, false, false); 627 } else if (unlikely(r != 0)) { 628 return r; 629 } 630 631 offset = bo->mem.start << PAGE_SHIFT; 632 /* this should never happen */ 633 if ((offset + size) > adev->mc.visible_vram_size) 634 return -EINVAL; 635 636 return 0; 637 } 638 639 /** 640 * amdgpu_bo_fence - add fence to buffer object 641 * 642 * @bo: buffer object in question 643 * @fence: fence to add 644 * @shared: true if fence should be added shared 645 * 646 */ 647 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, 648 bool shared) 649 { 650 struct reservation_object *resv = bo->tbo.resv; 651 652 if (shared) 653 reservation_object_add_shared_fence(resv, fence); 654 else 655 reservation_object_add_excl_fence(resv, fence); 656 } 657