1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 59 60 amdgpu_bo_kunmap(bo); 61 62 if (bo->tbo.base.import_attach) 63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 64 drm_gem_object_release(&bo->tbo.base); 65 amdgpu_bo_unref(&bo->parent); 66 kvfree(bo); 67 } 68 69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 70 { 71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 72 struct amdgpu_bo_user *ubo; 73 74 ubo = to_amdgpu_bo_user(bo); 75 kfree(ubo->metadata); 76 amdgpu_bo_destroy(tbo); 77 } 78 79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 82 struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; 83 struct amdgpu_bo_vm *vmbo; 84 85 bo = shadow_bo->parent; 86 vmbo = to_amdgpu_bo_vm(bo); 87 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 88 if (!list_empty(&vmbo->shadow_list)) { 89 mutex_lock(&adev->shadow_list_lock); 90 list_del_init(&vmbo->shadow_list); 91 mutex_unlock(&adev->shadow_list_lock); 92 } 93 94 amdgpu_bo_destroy(tbo); 95 } 96 97 /** 98 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 99 * @bo: buffer object to be checked 100 * 101 * Uses destroy function associated with the object to determine if this is 102 * an &amdgpu_bo. 103 * 104 * Returns: 105 * true if the object belongs to &amdgpu_bo, false if not. 106 */ 107 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 108 { 109 if (bo->destroy == &amdgpu_bo_destroy || 110 bo->destroy == &amdgpu_bo_user_destroy || 111 bo->destroy == &amdgpu_bo_vm_destroy) 112 return true; 113 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 136 137 if (adev->gmc.mem_partitions && mem_id >= 0) { 138 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn; 139 /* 140 * memory partition range lpfn is inclusive start + size - 1 141 * TTM place lpfn is exclusive start + size 142 */ 143 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1; 144 } else { 145 places[c].fpfn = 0; 146 places[c].lpfn = 0; 147 } 148 places[c].mem_type = TTM_PL_VRAM; 149 places[c].flags = 0; 150 151 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 152 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); 153 else 154 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 155 156 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 157 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 158 c++; 159 } 160 161 if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) { 162 places[c].fpfn = 0; 163 places[c].lpfn = 0; 164 places[c].mem_type = AMDGPU_PL_DOORBELL; 165 places[c].flags = 0; 166 c++; 167 } 168 169 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 170 places[c].fpfn = 0; 171 places[c].lpfn = 0; 172 places[c].mem_type = 173 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 174 AMDGPU_PL_PREEMPT : TTM_PL_TT; 175 places[c].flags = 0; 176 c++; 177 } 178 179 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 180 places[c].fpfn = 0; 181 places[c].lpfn = 0; 182 places[c].mem_type = TTM_PL_SYSTEM; 183 places[c].flags = 0; 184 c++; 185 } 186 187 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 188 places[c].fpfn = 0; 189 places[c].lpfn = 0; 190 places[c].mem_type = AMDGPU_PL_GDS; 191 places[c].flags = 0; 192 c++; 193 } 194 195 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 196 places[c].fpfn = 0; 197 places[c].lpfn = 0; 198 places[c].mem_type = AMDGPU_PL_GWS; 199 places[c].flags = 0; 200 c++; 201 } 202 203 if (domain & AMDGPU_GEM_DOMAIN_OA) { 204 places[c].fpfn = 0; 205 places[c].lpfn = 0; 206 places[c].mem_type = AMDGPU_PL_OA; 207 places[c].flags = 0; 208 c++; 209 } 210 211 if (!c) { 212 places[c].fpfn = 0; 213 places[c].lpfn = 0; 214 places[c].mem_type = TTM_PL_SYSTEM; 215 places[c].flags = 0; 216 c++; 217 } 218 219 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 220 221 placement->num_placement = c; 222 placement->placement = places; 223 224 placement->num_busy_placement = c; 225 placement->busy_placement = places; 226 } 227 228 /** 229 * amdgpu_bo_create_reserved - create reserved BO for kernel use 230 * 231 * @adev: amdgpu device object 232 * @size: size for the new BO 233 * @align: alignment for the new BO 234 * @domain: where to place it 235 * @bo_ptr: used to initialize BOs in structures 236 * @gpu_addr: GPU addr of the pinned BO 237 * @cpu_addr: optional CPU address mapping 238 * 239 * Allocates and pins a BO for kernel internal use, and returns it still 240 * reserved. 241 * 242 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 243 * 244 * Returns: 245 * 0 on success, negative error code otherwise. 246 */ 247 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 248 unsigned long size, int align, 249 u32 domain, struct amdgpu_bo **bo_ptr, 250 u64 *gpu_addr, void **cpu_addr) 251 { 252 struct amdgpu_bo_param bp; 253 bool free = false; 254 int r; 255 256 if (!size) { 257 amdgpu_bo_unref(bo_ptr); 258 return 0; 259 } 260 261 memset(&bp, 0, sizeof(bp)); 262 bp.size = size; 263 bp.byte_align = align; 264 bp.domain = domain; 265 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 266 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 267 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 268 bp.type = ttm_bo_type_kernel; 269 bp.resv = NULL; 270 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 271 272 if (!*bo_ptr) { 273 r = amdgpu_bo_create(adev, &bp, bo_ptr); 274 if (r) { 275 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 276 r); 277 return r; 278 } 279 free = true; 280 } 281 282 r = amdgpu_bo_reserve(*bo_ptr, false); 283 if (r) { 284 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 285 goto error_free; 286 } 287 288 r = amdgpu_bo_pin(*bo_ptr, domain); 289 if (r) { 290 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 291 goto error_unreserve; 292 } 293 294 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 295 if (r) { 296 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 297 goto error_unpin; 298 } 299 300 if (gpu_addr) 301 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 302 303 if (cpu_addr) { 304 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 305 if (r) { 306 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 307 goto error_unpin; 308 } 309 } 310 311 return 0; 312 313 error_unpin: 314 amdgpu_bo_unpin(*bo_ptr); 315 error_unreserve: 316 amdgpu_bo_unreserve(*bo_ptr); 317 318 error_free: 319 if (free) 320 amdgpu_bo_unref(bo_ptr); 321 322 return r; 323 } 324 325 /** 326 * amdgpu_bo_create_kernel - create BO for kernel use 327 * 328 * @adev: amdgpu device object 329 * @size: size for the new BO 330 * @align: alignment for the new BO 331 * @domain: where to place it 332 * @bo_ptr: used to initialize BOs in structures 333 * @gpu_addr: GPU addr of the pinned BO 334 * @cpu_addr: optional CPU address mapping 335 * 336 * Allocates and pins a BO for kernel internal use. 337 * 338 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 339 * 340 * Returns: 341 * 0 on success, negative error code otherwise. 342 */ 343 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 344 unsigned long size, int align, 345 u32 domain, struct amdgpu_bo **bo_ptr, 346 u64 *gpu_addr, void **cpu_addr) 347 { 348 int r; 349 350 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 351 gpu_addr, cpu_addr); 352 353 if (r) 354 return r; 355 356 if (*bo_ptr) 357 amdgpu_bo_unreserve(*bo_ptr); 358 359 return 0; 360 } 361 362 /** 363 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 364 * 365 * @adev: amdgpu device object 366 * @offset: offset of the BO 367 * @size: size of the BO 368 * @bo_ptr: used to initialize BOs in structures 369 * @cpu_addr: optional CPU address mapping 370 * 371 * Creates a kernel BO at a specific offset in VRAM. 372 * 373 * Returns: 374 * 0 on success, negative error code otherwise. 375 */ 376 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 377 uint64_t offset, uint64_t size, 378 struct amdgpu_bo **bo_ptr, void **cpu_addr) 379 { 380 struct ttm_operation_ctx ctx = { false, false }; 381 unsigned int i; 382 int r; 383 384 offset &= PAGE_MASK; 385 size = ALIGN(size, PAGE_SIZE); 386 387 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 388 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL, 389 cpu_addr); 390 if (r) 391 return r; 392 393 if ((*bo_ptr) == NULL) 394 return 0; 395 396 /* 397 * Remove the original mem node and create a new one at the request 398 * position. 399 */ 400 if (cpu_addr) 401 amdgpu_bo_kunmap(*bo_ptr); 402 403 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 404 405 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 406 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 407 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 408 } 409 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 410 &(*bo_ptr)->tbo.resource, &ctx); 411 if (r) 412 goto error; 413 414 if (cpu_addr) { 415 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 416 if (r) 417 goto error; 418 } 419 420 amdgpu_bo_unreserve(*bo_ptr); 421 return 0; 422 423 error: 424 amdgpu_bo_unreserve(*bo_ptr); 425 amdgpu_bo_unref(bo_ptr); 426 return r; 427 } 428 429 /** 430 * amdgpu_bo_free_kernel - free BO for kernel use 431 * 432 * @bo: amdgpu BO to free 433 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 434 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 435 * 436 * unmaps and unpin a BO for kernel internal use. 437 */ 438 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 439 void **cpu_addr) 440 { 441 if (*bo == NULL) 442 return; 443 444 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend); 445 446 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 447 if (cpu_addr) 448 amdgpu_bo_kunmap(*bo); 449 450 amdgpu_bo_unpin(*bo); 451 amdgpu_bo_unreserve(*bo); 452 } 453 amdgpu_bo_unref(bo); 454 455 if (gpu_addr) 456 *gpu_addr = 0; 457 458 if (cpu_addr) 459 *cpu_addr = NULL; 460 } 461 462 /* Validate bo size is bit bigger then the request domain */ 463 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 464 unsigned long size, u32 domain) 465 { 466 struct ttm_resource_manager *man = NULL; 467 468 /* 469 * If GTT is part of requested domains the check must succeed to 470 * allow fall back to GTT. 471 */ 472 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 473 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 474 475 if (man && size < man->size) 476 return true; 477 else if (!man) 478 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 479 goto fail; 480 } else if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 481 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 482 483 if (man && size < man->size) 484 return true; 485 goto fail; 486 } 487 488 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */ 489 return true; 490 491 fail: 492 if (man) 493 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 494 man->size); 495 return false; 496 } 497 498 bool amdgpu_bo_support_uswc(u64 bo_flags) 499 { 500 501 #ifdef CONFIG_X86_32 502 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 503 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 504 */ 505 return false; 506 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 507 /* Don't try to enable write-combining when it can't work, or things 508 * may be slow 509 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 510 */ 511 512 #ifndef CONFIG_COMPILE_TEST 513 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 514 thanks to write-combining 515 #endif 516 517 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 518 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 519 "better performance thanks to write-combining\n"); 520 return false; 521 #else 522 /* For architectures that don't support WC memory, 523 * mask out the WC flag from the BO 524 */ 525 if (!drm_arch_can_wc_memory()) 526 return false; 527 528 return true; 529 #endif 530 } 531 532 /** 533 * amdgpu_bo_create - create an &amdgpu_bo buffer object 534 * @adev: amdgpu device object 535 * @bp: parameters to be used for the buffer object 536 * @bo_ptr: pointer to the buffer object pointer 537 * 538 * Creates an &amdgpu_bo buffer object. 539 * 540 * Returns: 541 * 0 for success or a negative error code on failure. 542 */ 543 int amdgpu_bo_create(struct amdgpu_device *adev, 544 struct amdgpu_bo_param *bp, 545 struct amdgpu_bo **bo_ptr) 546 { 547 struct ttm_operation_ctx ctx = { 548 .interruptible = (bp->type != ttm_bo_type_kernel), 549 .no_wait_gpu = bp->no_wait_gpu, 550 /* We opt to avoid OOM on system pages allocations */ 551 .gfp_retry_mayfail = true, 552 .allow_res_evict = bp->type != ttm_bo_type_kernel, 553 .resv = bp->resv 554 }; 555 struct amdgpu_bo *bo; 556 unsigned long page_align, size = bp->size; 557 int r; 558 559 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 560 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 561 /* GWS and OA don't need any alignment. */ 562 page_align = bp->byte_align; 563 size <<= PAGE_SHIFT; 564 565 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 566 /* Both size and alignment must be a multiple of 4. */ 567 page_align = ALIGN(bp->byte_align, 4); 568 size = ALIGN(size, 4) << PAGE_SHIFT; 569 } else { 570 /* Memory should be aligned at least to a page size. */ 571 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 572 size = ALIGN(size, PAGE_SIZE); 573 } 574 575 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 576 return -ENOMEM; 577 578 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 579 580 *bo_ptr = NULL; 581 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 582 if (bo == NULL) 583 return -ENOMEM; 584 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 585 bo->vm_bo = NULL; 586 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 587 bp->domain; 588 bo->allowed_domains = bo->preferred_domains; 589 if (bp->type != ttm_bo_type_kernel && 590 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 591 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 592 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 593 594 bo->flags = bp->flags; 595 596 if (adev->gmc.mem_partitions) 597 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */ 598 bo->xcp_id = bp->xcp_id_plus1 - 1; 599 else 600 /* For GPUs without spatial partitioning */ 601 bo->xcp_id = 0; 602 603 if (!amdgpu_bo_support_uswc(bo->flags)) 604 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 605 606 if (adev->ras_enabled) 607 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 608 609 bo->tbo.bdev = &adev->mman.bdev; 610 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 611 AMDGPU_GEM_DOMAIN_GDS)) 612 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 613 else 614 amdgpu_bo_placement_from_domain(bo, bp->domain); 615 if (bp->type == ttm_bo_type_kernel) 616 bo->tbo.priority = 1; 617 618 if (!bp->destroy) 619 bp->destroy = &amdgpu_bo_destroy; 620 621 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 622 &bo->placement, page_align, &ctx, NULL, 623 bp->resv, bp->destroy); 624 if (unlikely(r != 0)) 625 return r; 626 627 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 628 bo->tbo.resource->mem_type == TTM_PL_VRAM && 629 amdgpu_bo_in_cpu_visible_vram(bo)) 630 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 631 ctx.bytes_moved); 632 else 633 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 634 635 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 636 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 637 struct dma_fence *fence; 638 639 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence, true); 640 if (unlikely(r)) 641 goto fail_unreserve; 642 643 dma_resv_add_fence(bo->tbo.base.resv, fence, 644 DMA_RESV_USAGE_KERNEL); 645 dma_fence_put(fence); 646 } 647 if (!bp->resv) 648 amdgpu_bo_unreserve(bo); 649 *bo_ptr = bo; 650 651 trace_amdgpu_bo_create(bo); 652 653 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 654 if (bp->type == ttm_bo_type_device) 655 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 656 657 return 0; 658 659 fail_unreserve: 660 if (!bp->resv) 661 dma_resv_unlock(bo->tbo.base.resv); 662 amdgpu_bo_unref(&bo); 663 return r; 664 } 665 666 /** 667 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 668 * @adev: amdgpu device object 669 * @bp: parameters to be used for the buffer object 670 * @ubo_ptr: pointer to the buffer object pointer 671 * 672 * Create a BO to be used by user application; 673 * 674 * Returns: 675 * 0 for success or a negative error code on failure. 676 */ 677 678 int amdgpu_bo_create_user(struct amdgpu_device *adev, 679 struct amdgpu_bo_param *bp, 680 struct amdgpu_bo_user **ubo_ptr) 681 { 682 struct amdgpu_bo *bo_ptr; 683 int r; 684 685 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 686 bp->destroy = &amdgpu_bo_user_destroy; 687 r = amdgpu_bo_create(adev, bp, &bo_ptr); 688 if (r) 689 return r; 690 691 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 692 return r; 693 } 694 695 /** 696 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 697 * @adev: amdgpu device object 698 * @bp: parameters to be used for the buffer object 699 * @vmbo_ptr: pointer to the buffer object pointer 700 * 701 * Create a BO to be for GPUVM. 702 * 703 * Returns: 704 * 0 for success or a negative error code on failure. 705 */ 706 707 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 708 struct amdgpu_bo_param *bp, 709 struct amdgpu_bo_vm **vmbo_ptr) 710 { 711 struct amdgpu_bo *bo_ptr; 712 int r; 713 714 /* bo_ptr_size will be determined by the caller and it depends on 715 * num of amdgpu_vm_pt entries. 716 */ 717 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 718 r = amdgpu_bo_create(adev, bp, &bo_ptr); 719 if (r) 720 return r; 721 722 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 723 return r; 724 } 725 726 /** 727 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 728 * 729 * @vmbo: BO that will be inserted into the shadow list 730 * 731 * Insert a BO to the shadow list. 732 */ 733 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 734 { 735 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 736 737 mutex_lock(&adev->shadow_list_lock); 738 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 739 vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); 740 vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; 741 mutex_unlock(&adev->shadow_list_lock); 742 } 743 744 /** 745 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 746 * 747 * @shadow: &amdgpu_bo shadow to be restored 748 * @fence: dma_fence associated with the operation 749 * 750 * Copies a buffer object's shadow content back to the object. 751 * This is used for recovering a buffer from its shadow in case of a gpu 752 * reset where vram context may be lost. 753 * 754 * Returns: 755 * 0 for success or a negative error code on failure. 756 */ 757 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 758 759 { 760 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 761 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 762 uint64_t shadow_addr, parent_addr; 763 764 shadow_addr = amdgpu_bo_gpu_offset(shadow); 765 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 766 767 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 768 amdgpu_bo_size(shadow), NULL, fence, 769 true, false, false); 770 } 771 772 /** 773 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 774 * @bo: &amdgpu_bo buffer object to be mapped 775 * @ptr: kernel virtual address to be returned 776 * 777 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 778 * amdgpu_bo_kptr() to get the kernel virtual address. 779 * 780 * Returns: 781 * 0 for success or a negative error code on failure. 782 */ 783 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 784 { 785 void *kptr; 786 long r; 787 788 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 789 return -EPERM; 790 791 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 792 false, MAX_SCHEDULE_TIMEOUT); 793 if (r < 0) 794 return r; 795 796 kptr = amdgpu_bo_kptr(bo); 797 if (kptr) { 798 if (ptr) 799 *ptr = kptr; 800 return 0; 801 } 802 803 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 804 if (r) 805 return r; 806 807 if (ptr) 808 *ptr = amdgpu_bo_kptr(bo); 809 810 return 0; 811 } 812 813 /** 814 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 815 * @bo: &amdgpu_bo buffer object 816 * 817 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 818 * 819 * Returns: 820 * the virtual address of a buffer object area. 821 */ 822 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 823 { 824 bool is_iomem; 825 826 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 827 } 828 829 /** 830 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 831 * @bo: &amdgpu_bo buffer object to be unmapped 832 * 833 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 834 */ 835 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 836 { 837 if (bo->kmap.bo) 838 ttm_bo_kunmap(&bo->kmap); 839 } 840 841 /** 842 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 843 * @bo: &amdgpu_bo buffer object 844 * 845 * References the contained &ttm_buffer_object. 846 * 847 * Returns: 848 * a refcounted pointer to the &amdgpu_bo buffer object. 849 */ 850 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 851 { 852 if (bo == NULL) 853 return NULL; 854 855 ttm_bo_get(&bo->tbo); 856 return bo; 857 } 858 859 /** 860 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 861 * @bo: &amdgpu_bo buffer object 862 * 863 * Unreferences the contained &ttm_buffer_object and clear the pointer 864 */ 865 void amdgpu_bo_unref(struct amdgpu_bo **bo) 866 { 867 struct ttm_buffer_object *tbo; 868 869 if ((*bo) == NULL) 870 return; 871 872 tbo = &((*bo)->tbo); 873 ttm_bo_put(tbo); 874 *bo = NULL; 875 } 876 877 /** 878 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 879 * @bo: &amdgpu_bo buffer object to be pinned 880 * @domain: domain to be pinned to 881 * @min_offset: the start of requested address range 882 * @max_offset: the end of requested address range 883 * 884 * Pins the buffer object according to requested domain and address range. If 885 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 886 * pin_count and pin_size accordingly. 887 * 888 * Pinning means to lock pages in memory along with keeping them at a fixed 889 * offset. It is required when a buffer can not be moved, for example, when 890 * a display buffer is being scanned out. 891 * 892 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 893 * where to pin a buffer if there are specific restrictions on where a buffer 894 * must be located. 895 * 896 * Returns: 897 * 0 for success or a negative error code on failure. 898 */ 899 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 900 u64 min_offset, u64 max_offset) 901 { 902 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 903 struct ttm_operation_ctx ctx = { false, false }; 904 int r, i; 905 906 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 907 return -EPERM; 908 909 if (WARN_ON_ONCE(min_offset > max_offset)) 910 return -EINVAL; 911 912 /* Check domain to be pinned to against preferred domains */ 913 if (bo->preferred_domains & domain) 914 domain = bo->preferred_domains & domain; 915 916 /* A shared bo cannot be migrated to VRAM */ 917 if (bo->tbo.base.import_attach) { 918 if (domain & AMDGPU_GEM_DOMAIN_GTT) 919 domain = AMDGPU_GEM_DOMAIN_GTT; 920 else 921 return -EINVAL; 922 } 923 924 if (bo->tbo.pin_count) { 925 uint32_t mem_type = bo->tbo.resource->mem_type; 926 uint32_t mem_flags = bo->tbo.resource->placement; 927 928 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 929 return -EINVAL; 930 931 if ((mem_type == TTM_PL_VRAM) && 932 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 933 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 934 return -EINVAL; 935 936 ttm_bo_pin(&bo->tbo); 937 938 if (max_offset != 0) { 939 u64 domain_start = amdgpu_ttm_domain_start(adev, 940 mem_type); 941 WARN_ON_ONCE(max_offset < 942 (amdgpu_bo_gpu_offset(bo) - domain_start)); 943 } 944 945 return 0; 946 } 947 948 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 949 * See function amdgpu_display_supported_domains() 950 */ 951 domain = amdgpu_bo_get_preferred_domain(adev, domain); 952 953 if (bo->tbo.base.import_attach) 954 dma_buf_pin(bo->tbo.base.import_attach); 955 956 /* force to pin into visible video ram */ 957 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 958 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 959 amdgpu_bo_placement_from_domain(bo, domain); 960 for (i = 0; i < bo->placement.num_placement; i++) { 961 unsigned int fpfn, lpfn; 962 963 fpfn = min_offset >> PAGE_SHIFT; 964 lpfn = max_offset >> PAGE_SHIFT; 965 966 if (fpfn > bo->placements[i].fpfn) 967 bo->placements[i].fpfn = fpfn; 968 if (!bo->placements[i].lpfn || 969 (lpfn && lpfn < bo->placements[i].lpfn)) 970 bo->placements[i].lpfn = lpfn; 971 } 972 973 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 974 if (unlikely(r)) { 975 dev_err(adev->dev, "%p pin failed\n", bo); 976 goto error; 977 } 978 979 ttm_bo_pin(&bo->tbo); 980 981 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 982 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 983 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 984 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 985 &adev->visible_pin_size); 986 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 987 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 988 } 989 990 error: 991 return r; 992 } 993 994 /** 995 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 996 * @bo: &amdgpu_bo buffer object to be pinned 997 * @domain: domain to be pinned to 998 * 999 * A simple wrapper to amdgpu_bo_pin_restricted(). 1000 * Provides a simpler API for buffers that do not have any strict restrictions 1001 * on where a buffer must be located. 1002 * 1003 * Returns: 1004 * 0 for success or a negative error code on failure. 1005 */ 1006 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 1007 { 1008 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1009 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 1010 } 1011 1012 /** 1013 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 1014 * @bo: &amdgpu_bo buffer object to be unpinned 1015 * 1016 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 1017 * Changes placement and pin size accordingly. 1018 * 1019 * Returns: 1020 * 0 for success or a negative error code on failure. 1021 */ 1022 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1023 { 1024 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1025 1026 ttm_bo_unpin(&bo->tbo); 1027 if (bo->tbo.pin_count) 1028 return; 1029 1030 if (bo->tbo.base.import_attach) 1031 dma_buf_unpin(bo->tbo.base.import_attach); 1032 1033 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1034 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1035 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1036 &adev->visible_pin_size); 1037 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1038 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1039 } 1040 1041 } 1042 1043 static const char * const amdgpu_vram_names[] = { 1044 "UNKNOWN", 1045 "GDDR1", 1046 "DDR2", 1047 "GDDR3", 1048 "GDDR4", 1049 "GDDR5", 1050 "HBM", 1051 "DDR3", 1052 "DDR4", 1053 "GDDR6", 1054 "DDR5", 1055 "LPDDR4", 1056 "LPDDR5" 1057 }; 1058 1059 /** 1060 * amdgpu_bo_init - initialize memory manager 1061 * @adev: amdgpu device object 1062 * 1063 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1064 * 1065 * Returns: 1066 * 0 for success or a negative error code on failure. 1067 */ 1068 int amdgpu_bo_init(struct amdgpu_device *adev) 1069 { 1070 /* On A+A platform, VRAM can be mapped as WB */ 1071 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1072 /* reserve PAT memory space to WC for VRAM */ 1073 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1074 adev->gmc.aper_size); 1075 1076 if (r) { 1077 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1078 return r; 1079 } 1080 1081 /* Add an MTRR for the VRAM */ 1082 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1083 adev->gmc.aper_size); 1084 } 1085 1086 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1087 adev->gmc.mc_vram_size >> 20, 1088 (unsigned long long)adev->gmc.aper_size >> 20); 1089 DRM_INFO("RAM width %dbits %s\n", 1090 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1091 return amdgpu_ttm_init(adev); 1092 } 1093 1094 /** 1095 * amdgpu_bo_fini - tear down memory manager 1096 * @adev: amdgpu device object 1097 * 1098 * Reverses amdgpu_bo_init() to tear down memory manager. 1099 */ 1100 void amdgpu_bo_fini(struct amdgpu_device *adev) 1101 { 1102 int idx; 1103 1104 amdgpu_ttm_fini(adev); 1105 1106 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1107 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1108 arch_phys_wc_del(adev->gmc.vram_mtrr); 1109 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1110 } 1111 drm_dev_exit(idx); 1112 } 1113 } 1114 1115 /** 1116 * amdgpu_bo_set_tiling_flags - set tiling flags 1117 * @bo: &amdgpu_bo buffer object 1118 * @tiling_flags: new flags 1119 * 1120 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1121 * kernel driver to set the tiling flags on a buffer. 1122 * 1123 * Returns: 1124 * 0 for success or a negative error code on failure. 1125 */ 1126 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1127 { 1128 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1129 struct amdgpu_bo_user *ubo; 1130 1131 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1132 if (adev->family <= AMDGPU_FAMILY_CZ && 1133 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1134 return -EINVAL; 1135 1136 ubo = to_amdgpu_bo_user(bo); 1137 ubo->tiling_flags = tiling_flags; 1138 return 0; 1139 } 1140 1141 /** 1142 * amdgpu_bo_get_tiling_flags - get tiling flags 1143 * @bo: &amdgpu_bo buffer object 1144 * @tiling_flags: returned flags 1145 * 1146 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1147 * set the tiling flags on a buffer. 1148 */ 1149 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1150 { 1151 struct amdgpu_bo_user *ubo; 1152 1153 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1154 dma_resv_assert_held(bo->tbo.base.resv); 1155 ubo = to_amdgpu_bo_user(bo); 1156 1157 if (tiling_flags) 1158 *tiling_flags = ubo->tiling_flags; 1159 } 1160 1161 /** 1162 * amdgpu_bo_set_metadata - set metadata 1163 * @bo: &amdgpu_bo buffer object 1164 * @metadata: new metadata 1165 * @metadata_size: size of the new metadata 1166 * @flags: flags of the new metadata 1167 * 1168 * Sets buffer object's metadata, its size and flags. 1169 * Used via GEM ioctl. 1170 * 1171 * Returns: 1172 * 0 for success or a negative error code on failure. 1173 */ 1174 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata, 1175 u32 metadata_size, uint64_t flags) 1176 { 1177 struct amdgpu_bo_user *ubo; 1178 void *buffer; 1179 1180 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1181 ubo = to_amdgpu_bo_user(bo); 1182 if (!metadata_size) { 1183 if (ubo->metadata_size) { 1184 kfree(ubo->metadata); 1185 ubo->metadata = NULL; 1186 ubo->metadata_size = 0; 1187 } 1188 return 0; 1189 } 1190 1191 if (metadata == NULL) 1192 return -EINVAL; 1193 1194 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1195 if (buffer == NULL) 1196 return -ENOMEM; 1197 1198 kfree(ubo->metadata); 1199 ubo->metadata_flags = flags; 1200 ubo->metadata = buffer; 1201 ubo->metadata_size = metadata_size; 1202 1203 return 0; 1204 } 1205 1206 /** 1207 * amdgpu_bo_get_metadata - get metadata 1208 * @bo: &amdgpu_bo buffer object 1209 * @buffer: returned metadata 1210 * @buffer_size: size of the buffer 1211 * @metadata_size: size of the returned metadata 1212 * @flags: flags of the returned metadata 1213 * 1214 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1215 * less than metadata_size. 1216 * Used via GEM ioctl. 1217 * 1218 * Returns: 1219 * 0 for success or a negative error code on failure. 1220 */ 1221 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1222 size_t buffer_size, uint32_t *metadata_size, 1223 uint64_t *flags) 1224 { 1225 struct amdgpu_bo_user *ubo; 1226 1227 if (!buffer && !metadata_size) 1228 return -EINVAL; 1229 1230 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1231 ubo = to_amdgpu_bo_user(bo); 1232 if (metadata_size) 1233 *metadata_size = ubo->metadata_size; 1234 1235 if (buffer) { 1236 if (buffer_size < ubo->metadata_size) 1237 return -EINVAL; 1238 1239 if (ubo->metadata_size) 1240 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1241 } 1242 1243 if (flags) 1244 *flags = ubo->metadata_flags; 1245 1246 return 0; 1247 } 1248 1249 /** 1250 * amdgpu_bo_move_notify - notification about a memory move 1251 * @bo: pointer to a buffer object 1252 * @evict: if this move is evicting the buffer from the graphics address space 1253 * 1254 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1255 * bookkeeping. 1256 * TTM driver callback which is called when ttm moves a buffer. 1257 */ 1258 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict) 1259 { 1260 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1261 struct amdgpu_bo *abo; 1262 1263 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1264 return; 1265 1266 abo = ttm_to_amdgpu_bo(bo); 1267 amdgpu_vm_bo_invalidate(adev, abo, evict); 1268 1269 amdgpu_bo_kunmap(abo); 1270 1271 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1272 bo->resource->mem_type != TTM_PL_SYSTEM) 1273 dma_buf_move_notify(abo->tbo.base.dma_buf); 1274 1275 /* remember the eviction */ 1276 if (evict) 1277 atomic64_inc(&adev->num_evictions); 1278 } 1279 1280 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, 1281 struct amdgpu_mem_stats *stats) 1282 { 1283 uint64_t size = amdgpu_bo_size(bo); 1284 unsigned int domain; 1285 1286 /* Abort if the BO doesn't currently have a backing store */ 1287 if (!bo->tbo.resource) 1288 return; 1289 1290 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1291 switch (domain) { 1292 case AMDGPU_GEM_DOMAIN_VRAM: 1293 stats->vram += size; 1294 if (amdgpu_bo_in_cpu_visible_vram(bo)) 1295 stats->visible_vram += size; 1296 break; 1297 case AMDGPU_GEM_DOMAIN_GTT: 1298 stats->gtt += size; 1299 break; 1300 case AMDGPU_GEM_DOMAIN_CPU: 1301 default: 1302 stats->cpu += size; 1303 break; 1304 } 1305 1306 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) { 1307 stats->requested_vram += size; 1308 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1309 stats->requested_visible_vram += size; 1310 1311 if (domain != AMDGPU_GEM_DOMAIN_VRAM) { 1312 stats->evicted_vram += size; 1313 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1314 stats->evicted_visible_vram += size; 1315 } 1316 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) { 1317 stats->requested_gtt += size; 1318 } 1319 } 1320 1321 /** 1322 * amdgpu_bo_release_notify - notification about a BO being released 1323 * @bo: pointer to a buffer object 1324 * 1325 * Wipes VRAM buffers whose contents should not be leaked before the 1326 * memory is released. 1327 */ 1328 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1329 { 1330 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1331 struct dma_fence *fence = NULL; 1332 struct amdgpu_bo *abo; 1333 int r; 1334 1335 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1336 return; 1337 1338 abo = ttm_to_amdgpu_bo(bo); 1339 1340 if (abo->kfd_bo) 1341 amdgpu_amdkfd_release_notify(abo); 1342 1343 /* We only remove the fence if the resv has individualized. */ 1344 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1345 && bo->base.resv != &bo->base._resv); 1346 if (bo->base.resv == &bo->base._resv) 1347 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1348 1349 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1350 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1351 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1352 return; 1353 1354 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1355 return; 1356 1357 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence, true); 1358 if (!WARN_ON(r)) { 1359 amdgpu_bo_fence(abo, fence, false); 1360 dma_fence_put(fence); 1361 } 1362 1363 dma_resv_unlock(bo->base.resv); 1364 } 1365 1366 /** 1367 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1368 * @bo: pointer to a buffer object 1369 * 1370 * Notifies the driver we are taking a fault on this BO and have reserved it, 1371 * also performs bookkeeping. 1372 * TTM driver callback for dealing with vm faults. 1373 * 1374 * Returns: 1375 * 0 for success or a negative error code on failure. 1376 */ 1377 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1378 { 1379 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1380 struct ttm_operation_ctx ctx = { false, false }; 1381 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1382 int r; 1383 1384 /* Remember that this BO was accessed by the CPU */ 1385 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1386 1387 if (bo->resource->mem_type != TTM_PL_VRAM) 1388 return 0; 1389 1390 if (amdgpu_bo_in_cpu_visible_vram(abo)) 1391 return 0; 1392 1393 /* Can't move a pinned BO to visible VRAM */ 1394 if (abo->tbo.pin_count > 0) 1395 return VM_FAULT_SIGBUS; 1396 1397 /* hurrah the memory is not visible ! */ 1398 atomic64_inc(&adev->num_vram_cpu_page_faults); 1399 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1400 AMDGPU_GEM_DOMAIN_GTT); 1401 1402 /* Avoid costly evictions; only set GTT as a busy placement */ 1403 abo->placement.num_busy_placement = 1; 1404 abo->placement.busy_placement = &abo->placements[1]; 1405 1406 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1407 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1408 return VM_FAULT_NOPAGE; 1409 else if (unlikely(r)) 1410 return VM_FAULT_SIGBUS; 1411 1412 /* this should never happen */ 1413 if (bo->resource->mem_type == TTM_PL_VRAM && 1414 !amdgpu_bo_in_cpu_visible_vram(abo)) 1415 return VM_FAULT_SIGBUS; 1416 1417 ttm_bo_move_to_lru_tail_unlocked(bo); 1418 return 0; 1419 } 1420 1421 /** 1422 * amdgpu_bo_fence - add fence to buffer object 1423 * 1424 * @bo: buffer object in question 1425 * @fence: fence to add 1426 * @shared: true if fence should be added shared 1427 * 1428 */ 1429 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1430 bool shared) 1431 { 1432 struct dma_resv *resv = bo->tbo.base.resv; 1433 int r; 1434 1435 r = dma_resv_reserve_fences(resv, 1); 1436 if (r) { 1437 /* As last resort on OOM we block for the fence */ 1438 dma_fence_wait(fence, false); 1439 return; 1440 } 1441 1442 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1443 DMA_RESV_USAGE_WRITE); 1444 } 1445 1446 /** 1447 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1448 * 1449 * @adev: amdgpu device pointer 1450 * @resv: reservation object to sync to 1451 * @sync_mode: synchronization mode 1452 * @owner: fence owner 1453 * @intr: Whether the wait is interruptible 1454 * 1455 * Extract the fences from the reservation object and waits for them to finish. 1456 * 1457 * Returns: 1458 * 0 on success, errno otherwise. 1459 */ 1460 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1461 enum amdgpu_sync_mode sync_mode, void *owner, 1462 bool intr) 1463 { 1464 struct amdgpu_sync sync; 1465 int r; 1466 1467 amdgpu_sync_create(&sync); 1468 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1469 r = amdgpu_sync_wait(&sync, intr); 1470 amdgpu_sync_free(&sync); 1471 return r; 1472 } 1473 1474 /** 1475 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1476 * @bo: buffer object to wait for 1477 * @owner: fence owner 1478 * @intr: Whether the wait is interruptible 1479 * 1480 * Wrapper to wait for fences in a BO. 1481 * Returns: 1482 * 0 on success, errno otherwise. 1483 */ 1484 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1485 { 1486 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1487 1488 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1489 AMDGPU_SYNC_NE_OWNER, owner, intr); 1490 } 1491 1492 /** 1493 * amdgpu_bo_gpu_offset - return GPU offset of bo 1494 * @bo: amdgpu object for which we query the offset 1495 * 1496 * Note: object should either be pinned or reserved when calling this 1497 * function, it might be useful to add check for this for debugging. 1498 * 1499 * Returns: 1500 * current GPU offset of the object. 1501 */ 1502 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1503 { 1504 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1505 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1506 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1507 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1508 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1509 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1510 1511 return amdgpu_bo_gpu_offset_no_check(bo); 1512 } 1513 1514 /** 1515 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1516 * @bo: amdgpu object for which we query the offset 1517 * 1518 * Returns: 1519 * current GPU offset of the object without raising warnings. 1520 */ 1521 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1522 { 1523 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1524 uint64_t offset; 1525 1526 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1527 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1528 1529 return amdgpu_gmc_sign_extend(offset); 1530 } 1531 1532 /** 1533 * amdgpu_bo_get_preferred_domain - get preferred domain 1534 * @adev: amdgpu device object 1535 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1536 * 1537 * Returns: 1538 * Which of the allowed domains is preferred for allocating the BO. 1539 */ 1540 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1541 uint32_t domain) 1542 { 1543 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1544 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1545 domain = AMDGPU_GEM_DOMAIN_VRAM; 1546 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1547 domain = AMDGPU_GEM_DOMAIN_GTT; 1548 } 1549 return domain; 1550 } 1551 1552 #if defined(CONFIG_DEBUG_FS) 1553 #define amdgpu_bo_print_flag(m, bo, flag) \ 1554 do { \ 1555 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1556 seq_printf((m), " " #flag); \ 1557 } \ 1558 } while (0) 1559 1560 /** 1561 * amdgpu_bo_print_info - print BO info in debugfs file 1562 * 1563 * @id: Index or Id of the BO 1564 * @bo: Requested BO for printing info 1565 * @m: debugfs file 1566 * 1567 * Print BO information in debugfs file 1568 * 1569 * Returns: 1570 * Size of the BO in bytes. 1571 */ 1572 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1573 { 1574 struct dma_buf_attachment *attachment; 1575 struct dma_buf *dma_buf; 1576 const char *placement; 1577 unsigned int pin_count; 1578 u64 size; 1579 1580 if (dma_resv_trylock(bo->tbo.base.resv)) { 1581 unsigned int domain; 1582 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1583 switch (domain) { 1584 case AMDGPU_GEM_DOMAIN_VRAM: 1585 if (amdgpu_bo_in_cpu_visible_vram(bo)) 1586 placement = "VRAM VISIBLE"; 1587 else 1588 placement = "VRAM"; 1589 break; 1590 case AMDGPU_GEM_DOMAIN_GTT: 1591 placement = "GTT"; 1592 break; 1593 case AMDGPU_GEM_DOMAIN_CPU: 1594 default: 1595 placement = "CPU"; 1596 break; 1597 } 1598 dma_resv_unlock(bo->tbo.base.resv); 1599 } else { 1600 placement = "UNKNOWN"; 1601 } 1602 1603 size = amdgpu_bo_size(bo); 1604 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1605 id, size, placement); 1606 1607 pin_count = READ_ONCE(bo->tbo.pin_count); 1608 if (pin_count) 1609 seq_printf(m, " pin count %d", pin_count); 1610 1611 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1612 attachment = READ_ONCE(bo->tbo.base.import_attach); 1613 1614 if (attachment) 1615 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino); 1616 else if (dma_buf) 1617 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino); 1618 1619 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1620 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1621 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1622 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1623 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1624 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1625 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1626 1627 seq_puts(m, "\n"); 1628 1629 return size; 1630 } 1631 #endif 1632