1078ef4e9SHawking Zhang /* 2078ef4e9SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3078ef4e9SHawking Zhang * 4078ef4e9SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5078ef4e9SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6078ef4e9SHawking Zhang * to deal in the Software without restriction, including without limitation 7078ef4e9SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8078ef4e9SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9078ef4e9SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10078ef4e9SHawking Zhang * 11078ef4e9SHawking Zhang * The above copyright notice and this permission notice shall be included in 12078ef4e9SHawking Zhang * all copies or substantial portions of the Software. 13078ef4e9SHawking Zhang * 14078ef4e9SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15078ef4e9SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16078ef4e9SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17078ef4e9SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18078ef4e9SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19078ef4e9SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20078ef4e9SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21078ef4e9SHawking Zhang * 22078ef4e9SHawking Zhang */ 23078ef4e9SHawking Zhang #ifndef __AMDGPU_NBIO_H__ 24078ef4e9SHawking Zhang #define __AMDGPU_NBIO_H__ 25078ef4e9SHawking Zhang 26078ef4e9SHawking Zhang /* 27078ef4e9SHawking Zhang * amdgpu nbio functions 28078ef4e9SHawking Zhang */ 29078ef4e9SHawking Zhang struct nbio_hdp_flush_reg { 30078ef4e9SHawking Zhang u32 ref_and_mask_cp0; 31078ef4e9SHawking Zhang u32 ref_and_mask_cp1; 32078ef4e9SHawking Zhang u32 ref_and_mask_cp2; 33078ef4e9SHawking Zhang u32 ref_and_mask_cp3; 34078ef4e9SHawking Zhang u32 ref_and_mask_cp4; 35078ef4e9SHawking Zhang u32 ref_and_mask_cp5; 36078ef4e9SHawking Zhang u32 ref_and_mask_cp6; 37078ef4e9SHawking Zhang u32 ref_and_mask_cp7; 38078ef4e9SHawking Zhang u32 ref_and_mask_cp8; 39078ef4e9SHawking Zhang u32 ref_and_mask_cp9; 40078ef4e9SHawking Zhang u32 ref_and_mask_sdma0; 41078ef4e9SHawking Zhang u32 ref_and_mask_sdma1; 42078ef4e9SHawking Zhang u32 ref_and_mask_sdma2; 43078ef4e9SHawking Zhang u32 ref_and_mask_sdma3; 44078ef4e9SHawking Zhang u32 ref_and_mask_sdma4; 45078ef4e9SHawking Zhang u32 ref_and_mask_sdma5; 46078ef4e9SHawking Zhang u32 ref_and_mask_sdma6; 47078ef4e9SHawking Zhang u32 ref_and_mask_sdma7; 48078ef4e9SHawking Zhang }; 49078ef4e9SHawking Zhang 506e36f231SHawking Zhang struct amdgpu_nbio_ras_funcs { 516e36f231SHawking Zhang void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev); 526e36f231SHawking Zhang void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev); 536e36f231SHawking Zhang int (*init_ras_controller_interrupt)(struct amdgpu_device *adev); 546e36f231SHawking Zhang int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev); 556e36f231SHawking Zhang void (*query_ras_error_count)(struct amdgpu_device *adev, 566e36f231SHawking Zhang void *ras_error_status); 576e36f231SHawking Zhang int (*ras_late_init)(struct amdgpu_device *adev); 586e36f231SHawking Zhang void (*ras_fini)(struct amdgpu_device *adev); 596e36f231SHawking Zhang }; 606e36f231SHawking Zhang 61078ef4e9SHawking Zhang struct amdgpu_nbio_funcs { 62078ef4e9SHawking Zhang const struct nbio_hdp_flush_reg *hdp_flush_reg; 63078ef4e9SHawking Zhang u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 64078ef4e9SHawking Zhang u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 65078ef4e9SHawking Zhang u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 66078ef4e9SHawking Zhang u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 675de54343SHuang Rui u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev); 685de54343SHuang Rui u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev); 69078ef4e9SHawking Zhang u32 (*get_rev_id)(struct amdgpu_device *adev); 70078ef4e9SHawking Zhang void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 71078ef4e9SHawking Zhang u32 (*get_memsize)(struct amdgpu_device *adev); 72078ef4e9SHawking Zhang void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 73078ef4e9SHawking Zhang bool use_doorbell, int doorbell_index, int doorbell_size); 74078ef4e9SHawking Zhang void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell, 75078ef4e9SHawking Zhang int doorbell_index, int instance); 76078ef4e9SHawking Zhang void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 77078ef4e9SHawking Zhang bool enable); 78078ef4e9SHawking Zhang void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 79078ef4e9SHawking Zhang bool enable); 80078ef4e9SHawking Zhang void (*ih_doorbell_range)(struct amdgpu_device *adev, 81078ef4e9SHawking Zhang bool use_doorbell, int doorbell_index); 82956f6705SLe Ma void (*enable_doorbell_interrupt)(struct amdgpu_device *adev, 83956f6705SLe Ma bool enable); 84078ef4e9SHawking Zhang void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 85078ef4e9SHawking Zhang bool enable); 86078ef4e9SHawking Zhang void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 87078ef4e9SHawking Zhang bool enable); 88078ef4e9SHawking Zhang void (*get_clockgating_state)(struct amdgpu_device *adev, 89078ef4e9SHawking Zhang u32 *flags); 90078ef4e9SHawking Zhang void (*ih_control)(struct amdgpu_device *adev); 91078ef4e9SHawking Zhang void (*init_registers)(struct amdgpu_device *adev); 92078ef4e9SHawking Zhang void (*remap_hdp_registers)(struct amdgpu_device *adev); 93f1213b15SEvan Quan void (*enable_aspm)(struct amdgpu_device *adev, 94f1213b15SEvan Quan bool enable); 95e1edaeafSLikun Gao void (*program_aspm)(struct amdgpu_device *adev); 965a5da8aeSEvan Quan void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev); 97*adcf949eSEvan Quan void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev); 98078ef4e9SHawking Zhang }; 99078ef4e9SHawking Zhang 100078ef4e9SHawking Zhang struct amdgpu_nbio { 101078ef4e9SHawking Zhang const struct nbio_hdp_flush_reg *hdp_flush_reg; 1024e644fffSHawking Zhang struct amdgpu_irq_src ras_controller_irq; 1034e644fffSHawking Zhang struct amdgpu_irq_src ras_err_event_athub_irq; 1049ad1dc29SHawking Zhang struct ras_common_if *ras_if; 105078ef4e9SHawking Zhang const struct amdgpu_nbio_funcs *funcs; 1066e36f231SHawking Zhang const struct amdgpu_nbio_ras_funcs *ras_funcs; 107078ef4e9SHawking Zhang }; 108078ef4e9SHawking Zhang 1091c70d3d9SHawking Zhang int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev); 110de9bbd52STao Zhou void amdgpu_nbio_ras_fini(struct amdgpu_device *adev); 111078ef4e9SHawking Zhang #endif 112