1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 
22 #include "amdgpu.h"
23 #include "amdgpu_ras.h"
24 
25 int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev)
26 {
27 	int err;
28 	struct amdgpu_nbio_ras *ras;
29 
30 	if (!adev->nbio.ras)
31 		return 0;
32 
33 	ras = adev->nbio.ras;
34 	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
35 	if (err) {
36 		dev_err(adev->dev, "Failed to register pcie_bif ras block!\n");
37 		return err;
38 	}
39 
40 	strcpy(ras->ras_block.ras_comm.name, "pcie_bif");
41 	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF;
42 	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
43 	adev->nbio.ras_if = &ras->ras_block.ras_comm;
44 
45 	return 0;
46 }
47 
48 u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev)
49 {
50 	if (adev->nbio.funcs && adev->nbio.funcs->get_pcie_replay_count)
51 		return adev->nbio.funcs->get_pcie_replay_count(adev);
52 
53 	return 0;
54 }
55 
56 void amdgpu_nbio_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
57 				uint64_t *count1)
58 {
59 	if (adev->nbio.funcs->get_pcie_usage)
60 		adev->nbio.funcs->get_pcie_usage(adev, count0, count1);
61 
62 }
63 
64 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
65 {
66 	int r;
67 	r = amdgpu_ras_block_late_init(adev, ras_block);
68 	if (r)
69 		return r;
70 
71 	if (amdgpu_ras_is_supported(adev, ras_block->block)) {
72 		r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
73 		if (r)
74 			goto late_fini;
75 		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
76 		if (r)
77 			goto late_fini;
78 	}
79 
80 	return 0;
81 late_fini:
82 	amdgpu_ras_block_late_fini(adev, ras_block);
83 	return r;
84 }
85