1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_fb_helper.h> 39 #include <drm/drm_plane_helper.h> 40 #include <linux/i2c.h> 41 #include <linux/i2c-algo-bit.h> 42 #include <linux/hrtimer.h> 43 #include "amdgpu_irq.h" 44 45 struct amdgpu_bo; 46 struct amdgpu_device; 47 struct amdgpu_encoder; 48 struct amdgpu_router; 49 struct amdgpu_hpd; 50 51 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 52 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 53 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 54 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 55 56 #define AMDGPU_MAX_HPD_PINS 6 57 #define AMDGPU_MAX_CRTCS 6 58 #define AMDGPU_MAX_AFMT_BLOCKS 9 59 60 enum amdgpu_rmx_type { 61 RMX_OFF, 62 RMX_FULL, 63 RMX_CENTER, 64 RMX_ASPECT 65 }; 66 67 enum amdgpu_underscan_type { 68 UNDERSCAN_OFF, 69 UNDERSCAN_ON, 70 UNDERSCAN_AUTO, 71 }; 72 73 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 74 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 75 76 enum amdgpu_hpd_id { 77 AMDGPU_HPD_1 = 0, 78 AMDGPU_HPD_2, 79 AMDGPU_HPD_3, 80 AMDGPU_HPD_4, 81 AMDGPU_HPD_5, 82 AMDGPU_HPD_6, 83 AMDGPU_HPD_LAST, 84 AMDGPU_HPD_NONE = 0xff, 85 }; 86 87 enum amdgpu_crtc_irq { 88 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 89 AMDGPU_CRTC_IRQ_VBLANK2, 90 AMDGPU_CRTC_IRQ_VBLANK3, 91 AMDGPU_CRTC_IRQ_VBLANK4, 92 AMDGPU_CRTC_IRQ_VBLANK5, 93 AMDGPU_CRTC_IRQ_VBLANK6, 94 AMDGPU_CRTC_IRQ_VLINE1, 95 AMDGPU_CRTC_IRQ_VLINE2, 96 AMDGPU_CRTC_IRQ_VLINE3, 97 AMDGPU_CRTC_IRQ_VLINE4, 98 AMDGPU_CRTC_IRQ_VLINE5, 99 AMDGPU_CRTC_IRQ_VLINE6, 100 AMDGPU_CRTC_IRQ_LAST, 101 AMDGPU_CRTC_IRQ_NONE = 0xff 102 }; 103 104 enum amdgpu_pageflip_irq { 105 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 106 AMDGPU_PAGEFLIP_IRQ_D2, 107 AMDGPU_PAGEFLIP_IRQ_D3, 108 AMDGPU_PAGEFLIP_IRQ_D4, 109 AMDGPU_PAGEFLIP_IRQ_D5, 110 AMDGPU_PAGEFLIP_IRQ_D6, 111 AMDGPU_PAGEFLIP_IRQ_LAST, 112 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 113 }; 114 115 enum amdgpu_flip_status { 116 AMDGPU_FLIP_NONE, 117 AMDGPU_FLIP_PENDING, 118 AMDGPU_FLIP_SUBMITTED 119 }; 120 121 #define AMDGPU_MAX_I2C_BUS 16 122 123 /* amdgpu gpio-based i2c 124 * 1. "mask" reg and bits 125 * grabs the gpio pins for software use 126 * 0=not held 1=held 127 * 2. "a" reg and bits 128 * output pin value 129 * 0=low 1=high 130 * 3. "en" reg and bits 131 * sets the pin direction 132 * 0=input 1=output 133 * 4. "y" reg and bits 134 * input pin value 135 * 0=low 1=high 136 */ 137 struct amdgpu_i2c_bus_rec { 138 bool valid; 139 /* id used by atom */ 140 uint8_t i2c_id; 141 /* id used by atom */ 142 enum amdgpu_hpd_id hpd; 143 /* can be used with hw i2c engine */ 144 bool hw_capable; 145 /* uses multi-media i2c engine */ 146 bool mm_i2c; 147 /* regs and bits */ 148 uint32_t mask_clk_reg; 149 uint32_t mask_data_reg; 150 uint32_t a_clk_reg; 151 uint32_t a_data_reg; 152 uint32_t en_clk_reg; 153 uint32_t en_data_reg; 154 uint32_t y_clk_reg; 155 uint32_t y_data_reg; 156 uint32_t mask_clk_mask; 157 uint32_t mask_data_mask; 158 uint32_t a_clk_mask; 159 uint32_t a_data_mask; 160 uint32_t en_clk_mask; 161 uint32_t en_data_mask; 162 uint32_t y_clk_mask; 163 uint32_t y_data_mask; 164 }; 165 166 #define AMDGPU_MAX_BIOS_CONNECTOR 16 167 168 /* pll flags */ 169 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 170 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 171 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 172 #define AMDGPU_PLL_LEGACY (1 << 3) 173 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 174 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 175 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 176 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 177 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 178 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 179 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 180 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 181 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 182 #define AMDGPU_PLL_IS_LCD (1 << 13) 183 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 184 185 struct amdgpu_pll { 186 /* reference frequency */ 187 uint32_t reference_freq; 188 189 /* fixed dividers */ 190 uint32_t reference_div; 191 uint32_t post_div; 192 193 /* pll in/out limits */ 194 uint32_t pll_in_min; 195 uint32_t pll_in_max; 196 uint32_t pll_out_min; 197 uint32_t pll_out_max; 198 uint32_t lcd_pll_out_min; 199 uint32_t lcd_pll_out_max; 200 uint32_t best_vco; 201 202 /* divider limits */ 203 uint32_t min_ref_div; 204 uint32_t max_ref_div; 205 uint32_t min_post_div; 206 uint32_t max_post_div; 207 uint32_t min_feedback_div; 208 uint32_t max_feedback_div; 209 uint32_t min_frac_feedback_div; 210 uint32_t max_frac_feedback_div; 211 212 /* flags for the current clock */ 213 uint32_t flags; 214 215 /* pll id */ 216 uint32_t id; 217 }; 218 219 struct amdgpu_i2c_chan { 220 struct i2c_adapter adapter; 221 struct drm_device *dev; 222 struct i2c_algo_bit_data bit; 223 struct amdgpu_i2c_bus_rec rec; 224 struct drm_dp_aux aux; 225 bool has_aux; 226 struct mutex mutex; 227 }; 228 229 struct amdgpu_fbdev; 230 231 struct amdgpu_afmt { 232 bool enabled; 233 int offset; 234 bool last_buffer_filled_status; 235 int id; 236 struct amdgpu_audio_pin *pin; 237 }; 238 239 /* 240 * Audio 241 */ 242 struct amdgpu_audio_pin { 243 int channels; 244 int rate; 245 int bits_per_sample; 246 u8 status_bits; 247 u8 category_code; 248 u32 offset; 249 bool connected; 250 u32 id; 251 }; 252 253 struct amdgpu_audio { 254 bool enabled; 255 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 256 int num_pins; 257 }; 258 259 struct amdgpu_mode_mc_save { 260 u32 vga_render_control; 261 u32 vga_hdp_control; 262 bool crtc_enabled[AMDGPU_MAX_CRTCS]; 263 }; 264 265 struct amdgpu_display_funcs { 266 /* vga render */ 267 void (*set_vga_render_state)(struct amdgpu_device *adev, bool render); 268 /* display watermarks */ 269 void (*bandwidth_update)(struct amdgpu_device *adev); 270 /* get frame count */ 271 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 272 /* wait for vblank */ 273 void (*vblank_wait)(struct amdgpu_device *adev, int crtc); 274 /* is dce hung */ 275 bool (*is_display_hung)(struct amdgpu_device *adev); 276 /* set backlight level */ 277 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 278 u8 level); 279 /* get backlight level */ 280 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 281 /* hotplug detect */ 282 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 283 void (*hpd_set_polarity)(struct amdgpu_device *adev, 284 enum amdgpu_hpd_id hpd); 285 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 286 /* pageflipping */ 287 void (*page_flip)(struct amdgpu_device *adev, 288 int crtc_id, u64 crtc_base, bool async); 289 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 290 u32 *vbl, u32 *position); 291 /* display topology setup */ 292 void (*add_encoder)(struct amdgpu_device *adev, 293 uint32_t encoder_enum, 294 uint32_t supported_device, 295 u16 caps); 296 void (*add_connector)(struct amdgpu_device *adev, 297 uint32_t connector_id, 298 uint32_t supported_device, 299 int connector_type, 300 struct amdgpu_i2c_bus_rec *i2c_bus, 301 uint16_t connector_object_id, 302 struct amdgpu_hpd *hpd, 303 struct amdgpu_router *router); 304 void (*stop_mc_access)(struct amdgpu_device *adev, 305 struct amdgpu_mode_mc_save *save); 306 void (*resume_mc_access)(struct amdgpu_device *adev, 307 struct amdgpu_mode_mc_save *save); 308 }; 309 310 struct amdgpu_mode_info { 311 struct atom_context *atom_context; 312 struct card_info *atom_card_info; 313 bool mode_config_initialized; 314 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 315 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 316 /* DVI-I properties */ 317 struct drm_property *coherent_mode_property; 318 /* DAC enable load detect */ 319 struct drm_property *load_detect_property; 320 /* underscan */ 321 struct drm_property *underscan_property; 322 struct drm_property *underscan_hborder_property; 323 struct drm_property *underscan_vborder_property; 324 /* audio */ 325 struct drm_property *audio_property; 326 /* FMT dithering */ 327 struct drm_property *dither_property; 328 /* hardcoded DFP edid from BIOS */ 329 struct edid *bios_hardcoded_edid; 330 int bios_hardcoded_edid_size; 331 332 /* pointer to fbdev info structure */ 333 struct amdgpu_fbdev *rfbdev; 334 /* firmware flags */ 335 u16 firmware_flags; 336 /* pointer to backlight encoder */ 337 struct amdgpu_encoder *bl_encoder; 338 struct amdgpu_audio audio; /* audio stuff */ 339 int num_crtc; /* number of crtcs */ 340 int num_hpd; /* number of hpd pins */ 341 int num_dig; /* number of dig blocks */ 342 int disp_priority; 343 const struct amdgpu_display_funcs *funcs; 344 }; 345 346 #define AMDGPU_MAX_BL_LEVEL 0xFF 347 348 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 349 350 struct amdgpu_backlight_privdata { 351 struct amdgpu_encoder *encoder; 352 uint8_t negative; 353 }; 354 355 #endif 356 357 struct amdgpu_atom_ss { 358 uint16_t percentage; 359 uint16_t percentage_divider; 360 uint8_t type; 361 uint16_t step; 362 uint8_t delay; 363 uint8_t range; 364 uint8_t refdiv; 365 /* asic_ss */ 366 uint16_t rate; 367 uint16_t amount; 368 }; 369 370 struct amdgpu_crtc { 371 struct drm_crtc base; 372 int crtc_id; 373 u16 lut_r[256], lut_g[256], lut_b[256]; 374 bool enabled; 375 bool can_tile; 376 uint32_t crtc_offset; 377 struct drm_gem_object *cursor_bo; 378 uint64_t cursor_addr; 379 int cursor_x; 380 int cursor_y; 381 int cursor_hot_x; 382 int cursor_hot_y; 383 int cursor_width; 384 int cursor_height; 385 int max_cursor_width; 386 int max_cursor_height; 387 enum amdgpu_rmx_type rmx_type; 388 u8 h_border; 389 u8 v_border; 390 fixed20_12 vsc; 391 fixed20_12 hsc; 392 struct drm_display_mode native_mode; 393 u32 pll_id; 394 /* page flipping */ 395 struct amdgpu_flip_work *pflip_works; 396 enum amdgpu_flip_status pflip_status; 397 int deferred_flip_completion; 398 /* pll sharing */ 399 struct amdgpu_atom_ss ss; 400 bool ss_enabled; 401 u32 adjusted_clock; 402 int bpc; 403 u32 pll_reference_div; 404 u32 pll_post_div; 405 u32 pll_flags; 406 struct drm_encoder *encoder; 407 struct drm_connector *connector; 408 /* for dpm */ 409 u32 line_time; 410 u32 wm_low; 411 u32 wm_high; 412 u32 lb_vblank_lead_lines; 413 struct drm_display_mode hw_mode; 414 /* for virtual dce */ 415 struct hrtimer vblank_timer; 416 enum amdgpu_interrupt_state vsync_timer_enabled; 417 }; 418 419 struct amdgpu_encoder_atom_dig { 420 bool linkb; 421 /* atom dig */ 422 bool coherent_mode; 423 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 424 /* atom lvds/edp */ 425 uint32_t lcd_misc; 426 uint16_t panel_pwr_delay; 427 uint32_t lcd_ss_id; 428 /* panel mode */ 429 struct drm_display_mode native_mode; 430 struct backlight_device *bl_dev; 431 int dpms_mode; 432 uint8_t backlight_level; 433 int panel_mode; 434 struct amdgpu_afmt *afmt; 435 }; 436 437 struct amdgpu_encoder { 438 struct drm_encoder base; 439 uint32_t encoder_enum; 440 uint32_t encoder_id; 441 uint32_t devices; 442 uint32_t active_device; 443 uint32_t flags; 444 uint32_t pixel_clock; 445 enum amdgpu_rmx_type rmx_type; 446 enum amdgpu_underscan_type underscan_type; 447 uint32_t underscan_hborder; 448 uint32_t underscan_vborder; 449 struct drm_display_mode native_mode; 450 void *enc_priv; 451 int audio_polling_active; 452 bool is_ext_encoder; 453 u16 caps; 454 }; 455 456 struct amdgpu_connector_atom_dig { 457 /* displayport */ 458 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 459 u8 dp_sink_type; 460 int dp_clock; 461 int dp_lane_count; 462 bool edp_on; 463 }; 464 465 struct amdgpu_gpio_rec { 466 bool valid; 467 u8 id; 468 u32 reg; 469 u32 mask; 470 u32 shift; 471 }; 472 473 struct amdgpu_hpd { 474 enum amdgpu_hpd_id hpd; 475 u8 plugged_state; 476 struct amdgpu_gpio_rec gpio; 477 }; 478 479 struct amdgpu_router { 480 u32 router_id; 481 struct amdgpu_i2c_bus_rec i2c_info; 482 u8 i2c_addr; 483 /* i2c mux */ 484 bool ddc_valid; 485 u8 ddc_mux_type; 486 u8 ddc_mux_control_pin; 487 u8 ddc_mux_state; 488 /* clock/data mux */ 489 bool cd_valid; 490 u8 cd_mux_type; 491 u8 cd_mux_control_pin; 492 u8 cd_mux_state; 493 }; 494 495 enum amdgpu_connector_audio { 496 AMDGPU_AUDIO_DISABLE = 0, 497 AMDGPU_AUDIO_ENABLE = 1, 498 AMDGPU_AUDIO_AUTO = 2 499 }; 500 501 enum amdgpu_connector_dither { 502 AMDGPU_FMT_DITHER_DISABLE = 0, 503 AMDGPU_FMT_DITHER_ENABLE = 1, 504 }; 505 506 struct amdgpu_connector { 507 struct drm_connector base; 508 uint32_t connector_id; 509 uint32_t devices; 510 struct amdgpu_i2c_chan *ddc_bus; 511 /* some systems have an hdmi and vga port with a shared ddc line */ 512 bool shared_ddc; 513 bool use_digital; 514 /* we need to mind the EDID between detect 515 and get modes due to analog/digital/tvencoder */ 516 struct edid *edid; 517 void *con_priv; 518 bool dac_load_detect; 519 bool detected_by_load; /* if the connection status was determined by load */ 520 uint16_t connector_object_id; 521 struct amdgpu_hpd hpd; 522 struct amdgpu_router router; 523 struct amdgpu_i2c_chan *router_bus; 524 enum amdgpu_connector_audio audio; 525 enum amdgpu_connector_dither dither; 526 unsigned pixelclock_for_modeset; 527 }; 528 529 struct amdgpu_framebuffer { 530 struct drm_framebuffer base; 531 struct drm_gem_object *obj; 532 }; 533 534 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 535 ((em) == ATOM_ENCODER_MODE_DP_MST)) 536 537 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ 538 #define USE_REAL_VBLANKSTART (1 << 30) 539 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 540 541 void amdgpu_link_encoder_connector(struct drm_device *dev); 542 543 struct drm_connector * 544 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 545 struct drm_connector * 546 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 547 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 548 u32 pixel_clock); 549 550 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 551 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 552 553 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux); 554 555 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 556 557 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 558 unsigned int flags, int *vpos, int *hpos, 559 ktime_t *stime, ktime_t *etime, 560 const struct drm_display_mode *mode); 561 562 int amdgpu_framebuffer_init(struct drm_device *dev, 563 struct amdgpu_framebuffer *rfb, 564 const struct drm_mode_fb_cmd2 *mode_cmd, 565 struct drm_gem_object *obj); 566 567 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 568 569 void amdgpu_enc_destroy(struct drm_encoder *encoder); 570 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 571 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 572 const struct drm_display_mode *mode, 573 struct drm_display_mode *adjusted_mode); 574 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 575 struct drm_display_mode *adjusted_mode); 576 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 577 578 /* fbdev layer */ 579 int amdgpu_fbdev_init(struct amdgpu_device *adev); 580 void amdgpu_fbdev_fini(struct amdgpu_device *adev); 581 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 582 int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 583 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 584 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); 585 586 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); 587 588 589 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 590 591 /* amdgpu_display.c */ 592 void amdgpu_print_display_setup(struct drm_device *dev); 593 int amdgpu_modeset_create_props(struct amdgpu_device *adev); 594 int amdgpu_crtc_set_config(struct drm_mode_set *set); 595 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc, 596 struct drm_framebuffer *fb, 597 struct drm_pending_vblank_event *event, 598 uint32_t page_flip_flags, uint32_t target); 599 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 600 601 #endif 602