1 /*
2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3  *                VA Linux Systems Inc., Fremont, California.
4  * Copyright 2008 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Original Authors:
25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26  *
27  * Kernel port Author: Dave Airlie
28  */
29 
30 #ifndef AMDGPU_MODE_H
31 #define AMDGPU_MODE_H
32 
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <drm/drm_plane_helper.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 
42 struct amdgpu_bo;
43 struct amdgpu_device;
44 struct amdgpu_encoder;
45 struct amdgpu_router;
46 struct amdgpu_hpd;
47 
48 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
49 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
50 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
51 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
52 
53 #define AMDGPU_MAX_HPD_PINS 6
54 #define AMDGPU_MAX_CRTCS 6
55 #define AMDGPU_MAX_AFMT_BLOCKS 7
56 
57 enum amdgpu_rmx_type {
58 	RMX_OFF,
59 	RMX_FULL,
60 	RMX_CENTER,
61 	RMX_ASPECT
62 };
63 
64 enum amdgpu_underscan_type {
65 	UNDERSCAN_OFF,
66 	UNDERSCAN_ON,
67 	UNDERSCAN_AUTO,
68 };
69 
70 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
71 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
72 
73 enum amdgpu_hpd_id {
74 	AMDGPU_HPD_1 = 0,
75 	AMDGPU_HPD_2,
76 	AMDGPU_HPD_3,
77 	AMDGPU_HPD_4,
78 	AMDGPU_HPD_5,
79 	AMDGPU_HPD_6,
80 	AMDGPU_HPD_LAST,
81 	AMDGPU_HPD_NONE = 0xff,
82 };
83 
84 enum amdgpu_crtc_irq {
85 	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
86 	AMDGPU_CRTC_IRQ_VBLANK2,
87 	AMDGPU_CRTC_IRQ_VBLANK3,
88 	AMDGPU_CRTC_IRQ_VBLANK4,
89 	AMDGPU_CRTC_IRQ_VBLANK5,
90 	AMDGPU_CRTC_IRQ_VBLANK6,
91 	AMDGPU_CRTC_IRQ_VLINE1,
92 	AMDGPU_CRTC_IRQ_VLINE2,
93 	AMDGPU_CRTC_IRQ_VLINE3,
94 	AMDGPU_CRTC_IRQ_VLINE4,
95 	AMDGPU_CRTC_IRQ_VLINE5,
96 	AMDGPU_CRTC_IRQ_VLINE6,
97 	AMDGPU_CRTC_IRQ_LAST,
98 	AMDGPU_CRTC_IRQ_NONE = 0xff
99 };
100 
101 enum amdgpu_pageflip_irq {
102 	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
103 	AMDGPU_PAGEFLIP_IRQ_D2,
104 	AMDGPU_PAGEFLIP_IRQ_D3,
105 	AMDGPU_PAGEFLIP_IRQ_D4,
106 	AMDGPU_PAGEFLIP_IRQ_D5,
107 	AMDGPU_PAGEFLIP_IRQ_D6,
108 	AMDGPU_PAGEFLIP_IRQ_LAST,
109 	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
110 };
111 
112 enum amdgpu_flip_status {
113 	AMDGPU_FLIP_NONE,
114 	AMDGPU_FLIP_PENDING,
115 	AMDGPU_FLIP_SUBMITTED
116 };
117 
118 #define AMDGPU_MAX_I2C_BUS 16
119 
120 /* amdgpu gpio-based i2c
121  * 1. "mask" reg and bits
122  *    grabs the gpio pins for software use
123  *    0=not held  1=held
124  * 2. "a" reg and bits
125  *    output pin value
126  *    0=low 1=high
127  * 3. "en" reg and bits
128  *    sets the pin direction
129  *    0=input 1=output
130  * 4. "y" reg and bits
131  *    input pin value
132  *    0=low 1=high
133  */
134 struct amdgpu_i2c_bus_rec {
135 	bool valid;
136 	/* id used by atom */
137 	uint8_t i2c_id;
138 	/* id used by atom */
139 	enum amdgpu_hpd_id hpd;
140 	/* can be used with hw i2c engine */
141 	bool hw_capable;
142 	/* uses multi-media i2c engine */
143 	bool mm_i2c;
144 	/* regs and bits */
145 	uint32_t mask_clk_reg;
146 	uint32_t mask_data_reg;
147 	uint32_t a_clk_reg;
148 	uint32_t a_data_reg;
149 	uint32_t en_clk_reg;
150 	uint32_t en_data_reg;
151 	uint32_t y_clk_reg;
152 	uint32_t y_data_reg;
153 	uint32_t mask_clk_mask;
154 	uint32_t mask_data_mask;
155 	uint32_t a_clk_mask;
156 	uint32_t a_data_mask;
157 	uint32_t en_clk_mask;
158 	uint32_t en_data_mask;
159 	uint32_t y_clk_mask;
160 	uint32_t y_data_mask;
161 };
162 
163 #define AMDGPU_MAX_BIOS_CONNECTOR 16
164 
165 /* pll flags */
166 #define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
167 #define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
168 #define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
169 #define AMDGPU_PLL_LEGACY               (1 << 3)
170 #define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
171 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
172 #define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
173 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
174 #define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
175 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
176 #define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
177 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
178 #define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
179 #define AMDGPU_PLL_IS_LCD               (1 << 13)
180 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
181 
182 struct amdgpu_pll {
183 	/* reference frequency */
184 	uint32_t reference_freq;
185 
186 	/* fixed dividers */
187 	uint32_t reference_div;
188 	uint32_t post_div;
189 
190 	/* pll in/out limits */
191 	uint32_t pll_in_min;
192 	uint32_t pll_in_max;
193 	uint32_t pll_out_min;
194 	uint32_t pll_out_max;
195 	uint32_t lcd_pll_out_min;
196 	uint32_t lcd_pll_out_max;
197 	uint32_t best_vco;
198 
199 	/* divider limits */
200 	uint32_t min_ref_div;
201 	uint32_t max_ref_div;
202 	uint32_t min_post_div;
203 	uint32_t max_post_div;
204 	uint32_t min_feedback_div;
205 	uint32_t max_feedback_div;
206 	uint32_t min_frac_feedback_div;
207 	uint32_t max_frac_feedback_div;
208 
209 	/* flags for the current clock */
210 	uint32_t flags;
211 
212 	/* pll id */
213 	uint32_t id;
214 };
215 
216 struct amdgpu_i2c_chan {
217 	struct i2c_adapter adapter;
218 	struct drm_device *dev;
219 	struct i2c_algo_bit_data bit;
220 	struct amdgpu_i2c_bus_rec rec;
221 	struct drm_dp_aux aux;
222 	bool has_aux;
223 	struct mutex mutex;
224 };
225 
226 struct amdgpu_fbdev;
227 
228 struct amdgpu_afmt {
229 	bool enabled;
230 	int offset;
231 	bool last_buffer_filled_status;
232 	int id;
233 	struct amdgpu_audio_pin *pin;
234 };
235 
236 /*
237  * Audio
238  */
239 struct amdgpu_audio_pin {
240 	int			channels;
241 	int			rate;
242 	int			bits_per_sample;
243 	u8			status_bits;
244 	u8			category_code;
245 	u32			offset;
246 	bool			connected;
247 	u32			id;
248 };
249 
250 struct amdgpu_audio {
251 	bool enabled;
252 	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
253 	int num_pins;
254 };
255 
256 struct amdgpu_mode_mc_save {
257 	u32 vga_render_control;
258 	u32 vga_hdp_control;
259 	bool crtc_enabled[AMDGPU_MAX_CRTCS];
260 };
261 
262 struct amdgpu_display_funcs {
263 	/* vga render */
264 	void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
265 	/* display watermarks */
266 	void (*bandwidth_update)(struct amdgpu_device *adev);
267 	/* get frame count */
268 	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
269 	/* wait for vblank */
270 	void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
271 	/* is dce hung */
272 	bool (*is_display_hung)(struct amdgpu_device *adev);
273 	/* set backlight level */
274 	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
275 				    u8 level);
276 	/* get backlight level */
277 	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
278 	/* hotplug detect */
279 	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
280 	void (*hpd_set_polarity)(struct amdgpu_device *adev,
281 				 enum amdgpu_hpd_id hpd);
282 	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
283 	/* pageflipping */
284 	void (*page_flip)(struct amdgpu_device *adev,
285 			 int crtc_id, u64 crtc_base);
286 	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
287 					u32 *vbl, u32 *position);
288 	/* display topology setup */
289 	void (*add_encoder)(struct amdgpu_device *adev,
290 			    uint32_t encoder_enum,
291 			    uint32_t supported_device,
292 			    u16 caps);
293 	void (*add_connector)(struct amdgpu_device *adev,
294 			      uint32_t connector_id,
295 			      uint32_t supported_device,
296 			      int connector_type,
297 			      struct amdgpu_i2c_bus_rec *i2c_bus,
298 			      uint16_t connector_object_id,
299 			      struct amdgpu_hpd *hpd,
300 			      struct amdgpu_router *router);
301 	void (*stop_mc_access)(struct amdgpu_device *adev,
302 			       struct amdgpu_mode_mc_save *save);
303 	void (*resume_mc_access)(struct amdgpu_device *adev,
304 				 struct amdgpu_mode_mc_save *save);
305 };
306 
307 struct amdgpu_mode_info {
308 	struct atom_context *atom_context;
309 	struct card_info *atom_card_info;
310 	bool mode_config_initialized;
311 	struct amdgpu_crtc *crtcs[6];
312 	struct amdgpu_afmt *afmt[7];
313 	/* DVI-I properties */
314 	struct drm_property *coherent_mode_property;
315 	/* DAC enable load detect */
316 	struct drm_property *load_detect_property;
317 	/* underscan */
318 	struct drm_property *underscan_property;
319 	struct drm_property *underscan_hborder_property;
320 	struct drm_property *underscan_vborder_property;
321 	/* audio */
322 	struct drm_property *audio_property;
323 	/* FMT dithering */
324 	struct drm_property *dither_property;
325 	/* hardcoded DFP edid from BIOS */
326 	struct edid *bios_hardcoded_edid;
327 	int bios_hardcoded_edid_size;
328 
329 	/* pointer to fbdev info structure */
330 	struct amdgpu_fbdev *rfbdev;
331 	/* firmware flags */
332 	u16 firmware_flags;
333 	/* pointer to backlight encoder */
334 	struct amdgpu_encoder *bl_encoder;
335 	struct amdgpu_audio	audio; /* audio stuff */
336 	int			num_crtc; /* number of crtcs */
337 	int			num_hpd; /* number of hpd pins */
338 	int			num_dig; /* number of dig blocks */
339 	int			disp_priority;
340 	const struct amdgpu_display_funcs *funcs;
341 };
342 
343 #define AMDGPU_MAX_BL_LEVEL 0xFF
344 
345 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
346 
347 struct amdgpu_backlight_privdata {
348 	struct amdgpu_encoder *encoder;
349 	uint8_t negative;
350 };
351 
352 #endif
353 
354 struct amdgpu_atom_ss {
355 	uint16_t percentage;
356 	uint16_t percentage_divider;
357 	uint8_t type;
358 	uint16_t step;
359 	uint8_t delay;
360 	uint8_t range;
361 	uint8_t refdiv;
362 	/* asic_ss */
363 	uint16_t rate;
364 	uint16_t amount;
365 };
366 
367 struct amdgpu_crtc {
368 	struct drm_crtc base;
369 	int crtc_id;
370 	u16 lut_r[256], lut_g[256], lut_b[256];
371 	bool enabled;
372 	bool can_tile;
373 	uint32_t crtc_offset;
374 	struct drm_gem_object *cursor_bo;
375 	uint64_t cursor_addr;
376 	int cursor_x;
377 	int cursor_y;
378 	int cursor_hot_x;
379 	int cursor_hot_y;
380 	int cursor_width;
381 	int cursor_height;
382 	int max_cursor_width;
383 	int max_cursor_height;
384 	enum amdgpu_rmx_type rmx_type;
385 	u8 h_border;
386 	u8 v_border;
387 	fixed20_12 vsc;
388 	fixed20_12 hsc;
389 	struct drm_display_mode native_mode;
390 	u32 pll_id;
391 	/* page flipping */
392 	struct workqueue_struct *pflip_queue;
393 	struct amdgpu_flip_work *pflip_works;
394 	enum amdgpu_flip_status pflip_status;
395 	int deferred_flip_completion;
396 	/* pll sharing */
397 	struct amdgpu_atom_ss ss;
398 	bool ss_enabled;
399 	u32 adjusted_clock;
400 	int bpc;
401 	u32 pll_reference_div;
402 	u32 pll_post_div;
403 	u32 pll_flags;
404 	struct drm_encoder *encoder;
405 	struct drm_connector *connector;
406 	/* for dpm */
407 	u32 line_time;
408 	u32 wm_low;
409 	u32 wm_high;
410 	u32 lb_vblank_lead_lines;
411 	struct drm_display_mode hw_mode;
412 };
413 
414 struct amdgpu_encoder_atom_dig {
415 	bool linkb;
416 	/* atom dig */
417 	bool coherent_mode;
418 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
419 	/* atom lvds/edp */
420 	uint32_t lcd_misc;
421 	uint16_t panel_pwr_delay;
422 	uint32_t lcd_ss_id;
423 	/* panel mode */
424 	struct drm_display_mode native_mode;
425 	struct backlight_device *bl_dev;
426 	int dpms_mode;
427 	uint8_t backlight_level;
428 	int panel_mode;
429 	struct amdgpu_afmt *afmt;
430 };
431 
432 struct amdgpu_encoder {
433 	struct drm_encoder base;
434 	uint32_t encoder_enum;
435 	uint32_t encoder_id;
436 	uint32_t devices;
437 	uint32_t active_device;
438 	uint32_t flags;
439 	uint32_t pixel_clock;
440 	enum amdgpu_rmx_type rmx_type;
441 	enum amdgpu_underscan_type underscan_type;
442 	uint32_t underscan_hborder;
443 	uint32_t underscan_vborder;
444 	struct drm_display_mode native_mode;
445 	void *enc_priv;
446 	int audio_polling_active;
447 	bool is_ext_encoder;
448 	u16 caps;
449 };
450 
451 struct amdgpu_connector_atom_dig {
452 	/* displayport */
453 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
454 	u8 dp_sink_type;
455 	int dp_clock;
456 	int dp_lane_count;
457 	bool edp_on;
458 };
459 
460 struct amdgpu_gpio_rec {
461 	bool valid;
462 	u8 id;
463 	u32 reg;
464 	u32 mask;
465 	u32 shift;
466 };
467 
468 struct amdgpu_hpd {
469 	enum amdgpu_hpd_id hpd;
470 	u8 plugged_state;
471 	struct amdgpu_gpio_rec gpio;
472 };
473 
474 struct amdgpu_router {
475 	u32 router_id;
476 	struct amdgpu_i2c_bus_rec i2c_info;
477 	u8 i2c_addr;
478 	/* i2c mux */
479 	bool ddc_valid;
480 	u8 ddc_mux_type;
481 	u8 ddc_mux_control_pin;
482 	u8 ddc_mux_state;
483 	/* clock/data mux */
484 	bool cd_valid;
485 	u8 cd_mux_type;
486 	u8 cd_mux_control_pin;
487 	u8 cd_mux_state;
488 };
489 
490 enum amdgpu_connector_audio {
491 	AMDGPU_AUDIO_DISABLE = 0,
492 	AMDGPU_AUDIO_ENABLE = 1,
493 	AMDGPU_AUDIO_AUTO = 2
494 };
495 
496 enum amdgpu_connector_dither {
497 	AMDGPU_FMT_DITHER_DISABLE = 0,
498 	AMDGPU_FMT_DITHER_ENABLE = 1,
499 };
500 
501 struct amdgpu_connector {
502 	struct drm_connector base;
503 	uint32_t connector_id;
504 	uint32_t devices;
505 	struct amdgpu_i2c_chan *ddc_bus;
506 	/* some systems have an hdmi and vga port with a shared ddc line */
507 	bool shared_ddc;
508 	bool use_digital;
509 	/* we need to mind the EDID between detect
510 	   and get modes due to analog/digital/tvencoder */
511 	struct edid *edid;
512 	void *con_priv;
513 	bool dac_load_detect;
514 	bool detected_by_load; /* if the connection status was determined by load */
515 	uint16_t connector_object_id;
516 	struct amdgpu_hpd hpd;
517 	struct amdgpu_router router;
518 	struct amdgpu_i2c_chan *router_bus;
519 	enum amdgpu_connector_audio audio;
520 	enum amdgpu_connector_dither dither;
521 	unsigned pixelclock_for_modeset;
522 };
523 
524 struct amdgpu_framebuffer {
525 	struct drm_framebuffer base;
526 	struct drm_gem_object *obj;
527 };
528 
529 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
530 				((em) == ATOM_ENCODER_MODE_DP_MST))
531 
532 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
533 #define USE_REAL_VBLANKSTART 		(1 << 30)
534 #define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
535 
536 void amdgpu_link_encoder_connector(struct drm_device *dev);
537 
538 struct drm_connector *
539 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
540 struct drm_connector *
541 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
542 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
543 				    u32 pixel_clock);
544 
545 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
546 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
547 
548 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
549 
550 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
551 
552 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
553 			       unsigned int flags, int *vpos, int *hpos,
554 			       ktime_t *stime, ktime_t *etime,
555 			       const struct drm_display_mode *mode);
556 
557 int amdgpu_framebuffer_init(struct drm_device *dev,
558 			     struct amdgpu_framebuffer *rfb,
559 			     struct drm_mode_fb_cmd2 *mode_cmd,
560 			     struct drm_gem_object *obj);
561 
562 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
563 
564 void amdgpu_enc_destroy(struct drm_encoder *encoder);
565 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
566 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
567 					const struct drm_display_mode *mode,
568 					struct drm_display_mode *adjusted_mode);
569 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
570 			     struct drm_display_mode *adjusted_mode);
571 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
572 
573 /* fbdev layer */
574 int amdgpu_fbdev_init(struct amdgpu_device *adev);
575 void amdgpu_fbdev_fini(struct amdgpu_device *adev);
576 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
577 int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
578 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
579 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
580 
581 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
582 
583 
584 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
585 
586 /* amdgpu_display.c */
587 void amdgpu_print_display_setup(struct drm_device *dev);
588 int amdgpu_modeset_create_props(struct amdgpu_device *adev);
589 int amdgpu_crtc_set_config(struct drm_mode_set *set);
590 int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
591 			  struct drm_framebuffer *fb,
592 			  struct drm_pending_vblank_event *event,
593 			  uint32_t page_flip_flags);
594 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
595 
596 #endif
597