1 /*
2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3  *                VA Linux Systems Inc., Fremont, California.
4  * Copyright 2008 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Original Authors:
25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26  *
27  * Kernel port Author: Dave Airlie
28  */
29 
30 #ifndef AMDGPU_MODE_H
31 #define AMDGPU_MODE_H
32 
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_plane_helper.h>
41 #include <drm/drm_probe_helper.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <linux/hrtimer.h>
45 #include "amdgpu_irq.h"
46 
47 #include <drm/drm_dp_mst_helper.h>
48 #include "modules/inc/mod_freesync.h"
49 #include "amdgpu_dm_irq_params.h"
50 
51 struct amdgpu_bo;
52 struct amdgpu_device;
53 struct amdgpu_encoder;
54 struct amdgpu_router;
55 struct amdgpu_hpd;
56 
57 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
58 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
59 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
60 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
61 
62 #define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base)
63 
64 #define AMDGPU_MAX_HPD_PINS 6
65 #define AMDGPU_MAX_CRTCS 6
66 #define AMDGPU_MAX_PLANES 6
67 #define AMDGPU_MAX_AFMT_BLOCKS 9
68 
69 enum amdgpu_rmx_type {
70 	RMX_OFF,
71 	RMX_FULL,
72 	RMX_CENTER,
73 	RMX_ASPECT
74 };
75 
76 enum amdgpu_underscan_type {
77 	UNDERSCAN_OFF,
78 	UNDERSCAN_ON,
79 	UNDERSCAN_AUTO,
80 };
81 
82 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
83 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
84 
85 enum amdgpu_hpd_id {
86 	AMDGPU_HPD_1 = 0,
87 	AMDGPU_HPD_2,
88 	AMDGPU_HPD_3,
89 	AMDGPU_HPD_4,
90 	AMDGPU_HPD_5,
91 	AMDGPU_HPD_6,
92 	AMDGPU_HPD_NONE = 0xff,
93 };
94 
95 enum amdgpu_crtc_irq {
96 	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
97 	AMDGPU_CRTC_IRQ_VBLANK2,
98 	AMDGPU_CRTC_IRQ_VBLANK3,
99 	AMDGPU_CRTC_IRQ_VBLANK4,
100 	AMDGPU_CRTC_IRQ_VBLANK5,
101 	AMDGPU_CRTC_IRQ_VBLANK6,
102 	AMDGPU_CRTC_IRQ_VLINE1,
103 	AMDGPU_CRTC_IRQ_VLINE2,
104 	AMDGPU_CRTC_IRQ_VLINE3,
105 	AMDGPU_CRTC_IRQ_VLINE4,
106 	AMDGPU_CRTC_IRQ_VLINE5,
107 	AMDGPU_CRTC_IRQ_VLINE6,
108 	AMDGPU_CRTC_IRQ_NONE = 0xff
109 };
110 
111 enum amdgpu_pageflip_irq {
112 	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
113 	AMDGPU_PAGEFLIP_IRQ_D2,
114 	AMDGPU_PAGEFLIP_IRQ_D3,
115 	AMDGPU_PAGEFLIP_IRQ_D4,
116 	AMDGPU_PAGEFLIP_IRQ_D5,
117 	AMDGPU_PAGEFLIP_IRQ_D6,
118 	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
119 };
120 
121 enum amdgpu_flip_status {
122 	AMDGPU_FLIP_NONE,
123 	AMDGPU_FLIP_PENDING,
124 	AMDGPU_FLIP_SUBMITTED
125 };
126 
127 #define AMDGPU_MAX_I2C_BUS 16
128 
129 /* amdgpu gpio-based i2c
130  * 1. "mask" reg and bits
131  *    grabs the gpio pins for software use
132  *    0=not held  1=held
133  * 2. "a" reg and bits
134  *    output pin value
135  *    0=low 1=high
136  * 3. "en" reg and bits
137  *    sets the pin direction
138  *    0=input 1=output
139  * 4. "y" reg and bits
140  *    input pin value
141  *    0=low 1=high
142  */
143 struct amdgpu_i2c_bus_rec {
144 	bool valid;
145 	/* id used by atom */
146 	uint8_t i2c_id;
147 	/* id used by atom */
148 	enum amdgpu_hpd_id hpd;
149 	/* can be used with hw i2c engine */
150 	bool hw_capable;
151 	/* uses multi-media i2c engine */
152 	bool mm_i2c;
153 	/* regs and bits */
154 	uint32_t mask_clk_reg;
155 	uint32_t mask_data_reg;
156 	uint32_t a_clk_reg;
157 	uint32_t a_data_reg;
158 	uint32_t en_clk_reg;
159 	uint32_t en_data_reg;
160 	uint32_t y_clk_reg;
161 	uint32_t y_data_reg;
162 	uint32_t mask_clk_mask;
163 	uint32_t mask_data_mask;
164 	uint32_t a_clk_mask;
165 	uint32_t a_data_mask;
166 	uint32_t en_clk_mask;
167 	uint32_t en_data_mask;
168 	uint32_t y_clk_mask;
169 	uint32_t y_data_mask;
170 };
171 
172 #define AMDGPU_MAX_BIOS_CONNECTOR 16
173 
174 /* pll flags */
175 #define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
176 #define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
177 #define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
178 #define AMDGPU_PLL_LEGACY               (1 << 3)
179 #define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
180 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
181 #define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
182 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
183 #define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
184 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
185 #define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
186 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
187 #define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
188 #define AMDGPU_PLL_IS_LCD               (1 << 13)
189 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
190 
191 struct amdgpu_pll {
192 	/* reference frequency */
193 	uint32_t reference_freq;
194 
195 	/* fixed dividers */
196 	uint32_t reference_div;
197 	uint32_t post_div;
198 
199 	/* pll in/out limits */
200 	uint32_t pll_in_min;
201 	uint32_t pll_in_max;
202 	uint32_t pll_out_min;
203 	uint32_t pll_out_max;
204 	uint32_t lcd_pll_out_min;
205 	uint32_t lcd_pll_out_max;
206 	uint32_t best_vco;
207 
208 	/* divider limits */
209 	uint32_t min_ref_div;
210 	uint32_t max_ref_div;
211 	uint32_t min_post_div;
212 	uint32_t max_post_div;
213 	uint32_t min_feedback_div;
214 	uint32_t max_feedback_div;
215 	uint32_t min_frac_feedback_div;
216 	uint32_t max_frac_feedback_div;
217 
218 	/* flags for the current clock */
219 	uint32_t flags;
220 
221 	/* pll id */
222 	uint32_t id;
223 };
224 
225 struct amdgpu_i2c_chan {
226 	struct i2c_adapter adapter;
227 	struct drm_device *dev;
228 	struct i2c_algo_bit_data bit;
229 	struct amdgpu_i2c_bus_rec rec;
230 	struct drm_dp_aux aux;
231 	bool has_aux;
232 	struct mutex mutex;
233 };
234 
235 struct amdgpu_fbdev;
236 
237 struct amdgpu_afmt {
238 	bool enabled;
239 	int offset;
240 	bool last_buffer_filled_status;
241 	int id;
242 	struct amdgpu_audio_pin *pin;
243 };
244 
245 /*
246  * Audio
247  */
248 struct amdgpu_audio_pin {
249 	int			channels;
250 	int			rate;
251 	int			bits_per_sample;
252 	u8			status_bits;
253 	u8			category_code;
254 	u32			offset;
255 	bool			connected;
256 	u32			id;
257 };
258 
259 struct amdgpu_audio {
260 	bool enabled;
261 	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
262 	int num_pins;
263 };
264 
265 struct amdgpu_display_funcs {
266 	/* display watermarks */
267 	void (*bandwidth_update)(struct amdgpu_device *adev);
268 	/* get frame count */
269 	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
270 	/* set backlight level */
271 	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
272 				    u8 level);
273 	/* get backlight level */
274 	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
275 	/* hotplug detect */
276 	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
277 	void (*hpd_set_polarity)(struct amdgpu_device *adev,
278 				 enum amdgpu_hpd_id hpd);
279 	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
280 	/* pageflipping */
281 	void (*page_flip)(struct amdgpu_device *adev,
282 			  int crtc_id, u64 crtc_base, bool async);
283 	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
284 					u32 *vbl, u32 *position);
285 	/* display topology setup */
286 	void (*add_encoder)(struct amdgpu_device *adev,
287 			    uint32_t encoder_enum,
288 			    uint32_t supported_device,
289 			    u16 caps);
290 	void (*add_connector)(struct amdgpu_device *adev,
291 			      uint32_t connector_id,
292 			      uint32_t supported_device,
293 			      int connector_type,
294 			      struct amdgpu_i2c_bus_rec *i2c_bus,
295 			      uint16_t connector_object_id,
296 			      struct amdgpu_hpd *hpd,
297 			      struct amdgpu_router *router);
298 
299 
300 };
301 
302 struct amdgpu_framebuffer {
303 	struct drm_framebuffer base;
304 
305 	uint64_t tiling_flags;
306 	bool tmz_surface;
307 
308 	/* caching for later use */
309 	uint64_t address;
310 };
311 
312 struct amdgpu_fbdev {
313 	struct drm_fb_helper helper;
314 	struct amdgpu_framebuffer rfb;
315 	struct list_head fbdev_list;
316 	struct amdgpu_device *adev;
317 };
318 
319 struct amdgpu_mode_info {
320 	struct atom_context *atom_context;
321 	struct card_info *atom_card_info;
322 	bool mode_config_initialized;
323 	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
324 	struct drm_plane *planes[AMDGPU_MAX_PLANES];
325 	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
326 	/* DVI-I properties */
327 	struct drm_property *coherent_mode_property;
328 	/* DAC enable load detect */
329 	struct drm_property *load_detect_property;
330 	/* underscan */
331 	struct drm_property *underscan_property;
332 	struct drm_property *underscan_hborder_property;
333 	struct drm_property *underscan_vborder_property;
334 	/* audio */
335 	struct drm_property *audio_property;
336 	/* FMT dithering */
337 	struct drm_property *dither_property;
338 	/* Adaptive Backlight Modulation (power feature) */
339 	struct drm_property *abm_level_property;
340 	/* hardcoded DFP edid from BIOS */
341 	struct edid *bios_hardcoded_edid;
342 	int bios_hardcoded_edid_size;
343 
344 	/* pointer to fbdev info structure */
345 	struct amdgpu_fbdev *rfbdev;
346 	/* firmware flags */
347 	u32 firmware_flags;
348 	/* pointer to backlight encoder */
349 	struct amdgpu_encoder *bl_encoder;
350 	u8 bl_level; /* saved backlight level */
351 	struct amdgpu_audio	audio; /* audio stuff */
352 	int			num_crtc; /* number of crtcs */
353 	int			num_hpd; /* number of hpd pins */
354 	int			num_dig; /* number of dig blocks */
355 	int			disp_priority;
356 	const struct amdgpu_display_funcs *funcs;
357 	const enum drm_plane_type *plane_type;
358 };
359 
360 #define AMDGPU_MAX_BL_LEVEL 0xFF
361 
362 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
363 
364 struct amdgpu_backlight_privdata {
365 	struct amdgpu_encoder *encoder;
366 	uint8_t negative;
367 };
368 
369 #endif
370 
371 struct amdgpu_atom_ss {
372 	uint16_t percentage;
373 	uint16_t percentage_divider;
374 	uint8_t type;
375 	uint16_t step;
376 	uint8_t delay;
377 	uint8_t range;
378 	uint8_t refdiv;
379 	/* asic_ss */
380 	uint16_t rate;
381 	uint16_t amount;
382 };
383 
384 struct amdgpu_crtc {
385 	struct drm_crtc base;
386 	int crtc_id;
387 	bool enabled;
388 	bool can_tile;
389 	uint32_t crtc_offset;
390 	struct drm_gem_object *cursor_bo;
391 	uint64_t cursor_addr;
392 	int cursor_x;
393 	int cursor_y;
394 	int cursor_hot_x;
395 	int cursor_hot_y;
396 	int cursor_width;
397 	int cursor_height;
398 	int max_cursor_width;
399 	int max_cursor_height;
400 	enum amdgpu_rmx_type rmx_type;
401 	u8 h_border;
402 	u8 v_border;
403 	fixed20_12 vsc;
404 	fixed20_12 hsc;
405 	struct drm_display_mode native_mode;
406 	u32 pll_id;
407 	/* page flipping */
408 	struct amdgpu_flip_work *pflip_works;
409 	enum amdgpu_flip_status pflip_status;
410 	int deferred_flip_completion;
411 	/* parameters access from DM IRQ handler */
412 	struct dm_irq_params dm_irq_params;
413 	/* pll sharing */
414 	struct amdgpu_atom_ss ss;
415 	bool ss_enabled;
416 	u32 adjusted_clock;
417 	int bpc;
418 	u32 pll_reference_div;
419 	u32 pll_post_div;
420 	u32 pll_flags;
421 	struct drm_encoder *encoder;
422 	struct drm_connector *connector;
423 	/* for dpm */
424 	u32 line_time;
425 	u32 wm_low;
426 	u32 wm_high;
427 	u32 lb_vblank_lead_lines;
428 	struct drm_display_mode hw_mode;
429 	/* for virtual dce */
430 	struct hrtimer vblank_timer;
431 	enum amdgpu_interrupt_state vsync_timer_enabled;
432 
433 	int otg_inst;
434 	struct drm_pending_vblank_event *event;
435 };
436 
437 struct amdgpu_encoder_atom_dig {
438 	bool linkb;
439 	/* atom dig */
440 	bool coherent_mode;
441 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
442 	/* atom lvds/edp */
443 	uint32_t lcd_misc;
444 	uint16_t panel_pwr_delay;
445 	uint32_t lcd_ss_id;
446 	/* panel mode */
447 	struct drm_display_mode native_mode;
448 	struct backlight_device *bl_dev;
449 	int dpms_mode;
450 	uint8_t backlight_level;
451 	int panel_mode;
452 	struct amdgpu_afmt *afmt;
453 };
454 
455 struct amdgpu_encoder {
456 	struct drm_encoder base;
457 	uint32_t encoder_enum;
458 	uint32_t encoder_id;
459 	uint32_t devices;
460 	uint32_t active_device;
461 	uint32_t flags;
462 	uint32_t pixel_clock;
463 	enum amdgpu_rmx_type rmx_type;
464 	enum amdgpu_underscan_type underscan_type;
465 	uint32_t underscan_hborder;
466 	uint32_t underscan_vborder;
467 	struct drm_display_mode native_mode;
468 	void *enc_priv;
469 	int audio_polling_active;
470 	bool is_ext_encoder;
471 	u16 caps;
472 };
473 
474 struct amdgpu_connector_atom_dig {
475 	/* displayport */
476 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
477 	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
478 	u8 dp_sink_type;
479 	int dp_clock;
480 	int dp_lane_count;
481 	bool edp_on;
482 };
483 
484 struct amdgpu_gpio_rec {
485 	bool valid;
486 	u8 id;
487 	u32 reg;
488 	u32 mask;
489 	u32 shift;
490 };
491 
492 struct amdgpu_hpd {
493 	enum amdgpu_hpd_id hpd;
494 	u8 plugged_state;
495 	struct amdgpu_gpio_rec gpio;
496 };
497 
498 struct amdgpu_router {
499 	u32 router_id;
500 	struct amdgpu_i2c_bus_rec i2c_info;
501 	u8 i2c_addr;
502 	/* i2c mux */
503 	bool ddc_valid;
504 	u8 ddc_mux_type;
505 	u8 ddc_mux_control_pin;
506 	u8 ddc_mux_state;
507 	/* clock/data mux */
508 	bool cd_valid;
509 	u8 cd_mux_type;
510 	u8 cd_mux_control_pin;
511 	u8 cd_mux_state;
512 };
513 
514 enum amdgpu_connector_audio {
515 	AMDGPU_AUDIO_DISABLE = 0,
516 	AMDGPU_AUDIO_ENABLE = 1,
517 	AMDGPU_AUDIO_AUTO = 2
518 };
519 
520 enum amdgpu_connector_dither {
521 	AMDGPU_FMT_DITHER_DISABLE = 0,
522 	AMDGPU_FMT_DITHER_ENABLE = 1,
523 };
524 
525 struct amdgpu_dm_dp_aux {
526 	struct drm_dp_aux aux;
527 	struct ddc_service *ddc_service;
528 };
529 
530 struct amdgpu_i2c_adapter {
531 	struct i2c_adapter base;
532 
533 	struct ddc_service *ddc_service;
534 };
535 
536 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
537 
538 struct amdgpu_connector {
539 	struct drm_connector base;
540 	uint32_t connector_id;
541 	uint32_t devices;
542 	struct amdgpu_i2c_chan *ddc_bus;
543 	/* some systems have an hdmi and vga port with a shared ddc line */
544 	bool shared_ddc;
545 	bool use_digital;
546 	/* we need to mind the EDID between detect
547 	   and get modes due to analog/digital/tvencoder */
548 	struct edid *edid;
549 	void *con_priv;
550 	bool dac_load_detect;
551 	bool detected_by_load; /* if the connection status was determined by load */
552 	uint16_t connector_object_id;
553 	struct amdgpu_hpd hpd;
554 	struct amdgpu_router router;
555 	struct amdgpu_i2c_chan *router_bus;
556 	enum amdgpu_connector_audio audio;
557 	enum amdgpu_connector_dither dither;
558 	unsigned pixelclock_for_modeset;
559 };
560 
561 /* TODO: start to use this struct and remove same field from base one */
562 struct amdgpu_mst_connector {
563 	struct amdgpu_connector base;
564 
565 	struct drm_dp_mst_topology_mgr mst_mgr;
566 	struct amdgpu_dm_dp_aux dm_dp_aux;
567 	struct drm_dp_mst_port *port;
568 	struct amdgpu_connector *mst_port;
569 	bool is_mst_connector;
570 	struct amdgpu_encoder *mst_encoder;
571 };
572 
573 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
574 				((em) == ATOM_ENCODER_MODE_DP_MST))
575 
576 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
577 #define DRM_SCANOUTPOS_VALID        (1 << 0)
578 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
579 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
580 #define USE_REAL_VBLANKSTART		(1 << 30)
581 #define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
582 
583 void amdgpu_link_encoder_connector(struct drm_device *dev);
584 
585 struct drm_connector *
586 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
587 struct drm_connector *
588 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
589 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
590 				    u32 pixel_clock);
591 
592 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
593 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
594 
595 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
596 			      bool use_aux);
597 
598 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
599 
600 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
601 			unsigned int pipe, unsigned int flags, int *vpos,
602 			int *hpos, ktime_t *stime, ktime_t *etime,
603 			const struct drm_display_mode *mode);
604 
605 int amdgpu_display_gem_fb_init(struct drm_device *dev,
606 			       struct amdgpu_framebuffer *rfb,
607 			       const struct drm_mode_fb_cmd2 *mode_cmd,
608 			       struct drm_gem_object *obj);
609 int amdgpu_display_gem_fb_verify_and_init(
610 	struct drm_device *dev, struct amdgpu_framebuffer *rfb,
611 	struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
612 	struct drm_gem_object *obj);
613 int amdgpu_display_framebuffer_init(struct drm_device *dev,
614 				    struct amdgpu_framebuffer *rfb,
615 				    const struct drm_mode_fb_cmd2 *mode_cmd,
616 				    struct drm_gem_object *obj);
617 
618 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
619 
620 void amdgpu_enc_destroy(struct drm_encoder *encoder);
621 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
622 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
623 				const struct drm_display_mode *mode,
624 				struct drm_display_mode *adjusted_mode);
625 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
626 			     struct drm_display_mode *adjusted_mode);
627 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
628 
629 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
630 			bool in_vblank_irq, int *vpos,
631 			int *hpos, ktime_t *stime, ktime_t *etime,
632 			const struct drm_display_mode *mode);
633 
634 /* fbdev layer */
635 int amdgpu_fbdev_init(struct amdgpu_device *adev);
636 void amdgpu_fbdev_fini(struct amdgpu_device *adev);
637 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
638 int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
639 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
640 
641 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
642 
643 /* amdgpu_display.c */
644 void amdgpu_display_print_display_setup(struct drm_device *dev);
645 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
646 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
647 				   struct drm_modeset_acquire_ctx *ctx);
648 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
649 				struct drm_framebuffer *fb,
650 				struct drm_pending_vblank_event *event,
651 				uint32_t page_flip_flags, uint32_t target,
652 				struct drm_modeset_acquire_ctx *ctx);
653 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
654 
655 #endif
656