1 /*
2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3  *                VA Linux Systems Inc., Fremont, California.
4  * Copyright 2008 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Original Authors:
25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26  *
27  * Kernel port Author: Dave Airlie
28  */
29 
30 #ifndef AMDGPU_MODE_H
31 #define AMDGPU_MODE_H
32 
33 #include <drm/display/drm_dp_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_framebuffer.h>
41 #include <drm/drm_probe_helper.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <linux/hrtimer.h>
45 #include "amdgpu_irq.h"
46 
47 #include <drm/display/drm_dp_mst_helper.h>
48 #include "modules/inc/mod_freesync.h"
49 #include "amdgpu_dm_irq_params.h"
50 
51 struct amdgpu_bo;
52 struct amdgpu_device;
53 struct amdgpu_encoder;
54 struct amdgpu_router;
55 struct amdgpu_hpd;
56 
57 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
58 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
59 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
60 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
61 
62 #define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base)
63 
64 #define AMDGPU_MAX_HPD_PINS 6
65 #define AMDGPU_MAX_CRTCS 6
66 #define AMDGPU_MAX_PLANES 6
67 #define AMDGPU_MAX_AFMT_BLOCKS 9
68 
69 enum amdgpu_rmx_type {
70 	RMX_OFF,
71 	RMX_FULL,
72 	RMX_CENTER,
73 	RMX_ASPECT
74 };
75 
76 enum amdgpu_underscan_type {
77 	UNDERSCAN_OFF,
78 	UNDERSCAN_ON,
79 	UNDERSCAN_AUTO,
80 };
81 
82 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
83 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
84 
85 enum amdgpu_hpd_id {
86 	AMDGPU_HPD_1 = 0,
87 	AMDGPU_HPD_2,
88 	AMDGPU_HPD_3,
89 	AMDGPU_HPD_4,
90 	AMDGPU_HPD_5,
91 	AMDGPU_HPD_6,
92 	AMDGPU_HPD_NONE = 0xff,
93 };
94 
95 enum amdgpu_crtc_irq {
96 	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
97 	AMDGPU_CRTC_IRQ_VBLANK2,
98 	AMDGPU_CRTC_IRQ_VBLANK3,
99 	AMDGPU_CRTC_IRQ_VBLANK4,
100 	AMDGPU_CRTC_IRQ_VBLANK5,
101 	AMDGPU_CRTC_IRQ_VBLANK6,
102 	AMDGPU_CRTC_IRQ_VLINE1,
103 	AMDGPU_CRTC_IRQ_VLINE2,
104 	AMDGPU_CRTC_IRQ_VLINE3,
105 	AMDGPU_CRTC_IRQ_VLINE4,
106 	AMDGPU_CRTC_IRQ_VLINE5,
107 	AMDGPU_CRTC_IRQ_VLINE6,
108 	AMDGPU_CRTC_IRQ_NONE = 0xff
109 };
110 
111 enum amdgpu_pageflip_irq {
112 	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
113 	AMDGPU_PAGEFLIP_IRQ_D2,
114 	AMDGPU_PAGEFLIP_IRQ_D3,
115 	AMDGPU_PAGEFLIP_IRQ_D4,
116 	AMDGPU_PAGEFLIP_IRQ_D5,
117 	AMDGPU_PAGEFLIP_IRQ_D6,
118 	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
119 };
120 
121 enum amdgpu_flip_status {
122 	AMDGPU_FLIP_NONE,
123 	AMDGPU_FLIP_PENDING,
124 	AMDGPU_FLIP_SUBMITTED
125 };
126 
127 #define AMDGPU_MAX_I2C_BUS 16
128 
129 /* amdgpu gpio-based i2c
130  * 1. "mask" reg and bits
131  *    grabs the gpio pins for software use
132  *    0=not held  1=held
133  * 2. "a" reg and bits
134  *    output pin value
135  *    0=low 1=high
136  * 3. "en" reg and bits
137  *    sets the pin direction
138  *    0=input 1=output
139  * 4. "y" reg and bits
140  *    input pin value
141  *    0=low 1=high
142  */
143 struct amdgpu_i2c_bus_rec {
144 	bool valid;
145 	/* id used by atom */
146 	uint8_t i2c_id;
147 	/* id used by atom */
148 	enum amdgpu_hpd_id hpd;
149 	/* can be used with hw i2c engine */
150 	bool hw_capable;
151 	/* uses multi-media i2c engine */
152 	bool mm_i2c;
153 	/* regs and bits */
154 	uint32_t mask_clk_reg;
155 	uint32_t mask_data_reg;
156 	uint32_t a_clk_reg;
157 	uint32_t a_data_reg;
158 	uint32_t en_clk_reg;
159 	uint32_t en_data_reg;
160 	uint32_t y_clk_reg;
161 	uint32_t y_data_reg;
162 	uint32_t mask_clk_mask;
163 	uint32_t mask_data_mask;
164 	uint32_t a_clk_mask;
165 	uint32_t a_data_mask;
166 	uint32_t en_clk_mask;
167 	uint32_t en_data_mask;
168 	uint32_t y_clk_mask;
169 	uint32_t y_data_mask;
170 };
171 
172 #define AMDGPU_MAX_BIOS_CONNECTOR 16
173 
174 /* pll flags */
175 #define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
176 #define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
177 #define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
178 #define AMDGPU_PLL_LEGACY               (1 << 3)
179 #define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
180 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
181 #define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
182 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
183 #define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
184 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
185 #define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
186 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
187 #define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
188 #define AMDGPU_PLL_IS_LCD               (1 << 13)
189 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
190 
191 struct amdgpu_pll {
192 	/* reference frequency */
193 	uint32_t reference_freq;
194 
195 	/* fixed dividers */
196 	uint32_t reference_div;
197 	uint32_t post_div;
198 
199 	/* pll in/out limits */
200 	uint32_t pll_in_min;
201 	uint32_t pll_in_max;
202 	uint32_t pll_out_min;
203 	uint32_t pll_out_max;
204 	uint32_t lcd_pll_out_min;
205 	uint32_t lcd_pll_out_max;
206 	uint32_t best_vco;
207 
208 	/* divider limits */
209 	uint32_t min_ref_div;
210 	uint32_t max_ref_div;
211 	uint32_t min_post_div;
212 	uint32_t max_post_div;
213 	uint32_t min_feedback_div;
214 	uint32_t max_feedback_div;
215 	uint32_t min_frac_feedback_div;
216 	uint32_t max_frac_feedback_div;
217 
218 	/* flags for the current clock */
219 	uint32_t flags;
220 
221 	/* pll id */
222 	uint32_t id;
223 };
224 
225 struct amdgpu_i2c_chan {
226 	struct i2c_adapter adapter;
227 	struct drm_device *dev;
228 	struct i2c_algo_bit_data bit;
229 	struct amdgpu_i2c_bus_rec rec;
230 	struct drm_dp_aux aux;
231 	bool has_aux;
232 	struct mutex mutex;
233 };
234 
235 struct amdgpu_afmt {
236 	bool enabled;
237 	int offset;
238 	bool last_buffer_filled_status;
239 	int id;
240 	struct amdgpu_audio_pin *pin;
241 };
242 
243 /*
244  * Audio
245  */
246 struct amdgpu_audio_pin {
247 	int			channels;
248 	int			rate;
249 	int			bits_per_sample;
250 	u8			status_bits;
251 	u8			category_code;
252 	u32			offset;
253 	bool			connected;
254 	u32			id;
255 };
256 
257 struct amdgpu_audio {
258 	bool enabled;
259 	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
260 	int num_pins;
261 };
262 
263 struct amdgpu_display_funcs {
264 	/* display watermarks */
265 	void (*bandwidth_update)(struct amdgpu_device *adev);
266 	/* get frame count */
267 	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
268 	/* set backlight level */
269 	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
270 				    u8 level);
271 	/* get backlight level */
272 	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
273 	/* hotplug detect */
274 	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
275 	void (*hpd_set_polarity)(struct amdgpu_device *adev,
276 				 enum amdgpu_hpd_id hpd);
277 	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
278 	/* pageflipping */
279 	void (*page_flip)(struct amdgpu_device *adev,
280 			  int crtc_id, u64 crtc_base, bool async);
281 	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
282 					u32 *vbl, u32 *position);
283 	/* display topology setup */
284 	void (*add_encoder)(struct amdgpu_device *adev,
285 			    uint32_t encoder_enum,
286 			    uint32_t supported_device,
287 			    u16 caps);
288 	void (*add_connector)(struct amdgpu_device *adev,
289 			      uint32_t connector_id,
290 			      uint32_t supported_device,
291 			      int connector_type,
292 			      struct amdgpu_i2c_bus_rec *i2c_bus,
293 			      uint16_t connector_object_id,
294 			      struct amdgpu_hpd *hpd,
295 			      struct amdgpu_router *router);
296 
297 
298 };
299 
300 struct amdgpu_framebuffer {
301 	struct drm_framebuffer base;
302 
303 	uint64_t tiling_flags;
304 	bool tmz_surface;
305 
306 	/* caching for later use */
307 	uint64_t address;
308 };
309 
310 struct amdgpu_mode_info {
311 	struct atom_context *atom_context;
312 	struct card_info *atom_card_info;
313 	bool mode_config_initialized;
314 	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
315 	struct drm_plane *planes[AMDGPU_MAX_PLANES];
316 	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
317 	/* DVI-I properties */
318 	struct drm_property *coherent_mode_property;
319 	/* DAC enable load detect */
320 	struct drm_property *load_detect_property;
321 	/* underscan */
322 	struct drm_property *underscan_property;
323 	struct drm_property *underscan_hborder_property;
324 	struct drm_property *underscan_vborder_property;
325 	/* audio */
326 	struct drm_property *audio_property;
327 	/* FMT dithering */
328 	struct drm_property *dither_property;
329 	/* Adaptive Backlight Modulation (power feature) */
330 	struct drm_property *abm_level_property;
331 	/* hardcoded DFP edid from BIOS */
332 	struct edid *bios_hardcoded_edid;
333 	int bios_hardcoded_edid_size;
334 
335 	/* firmware flags */
336 	u32 firmware_flags;
337 	/* pointer to backlight encoder */
338 	struct amdgpu_encoder *bl_encoder;
339 	u8 bl_level; /* saved backlight level */
340 	struct amdgpu_audio	audio; /* audio stuff */
341 	int			num_crtc; /* number of crtcs */
342 	int			num_hpd; /* number of hpd pins */
343 	int			num_dig; /* number of dig blocks */
344 	bool			gpu_vm_support; /* supports display from GTT */
345 	int			disp_priority;
346 	const struct amdgpu_display_funcs *funcs;
347 	const enum drm_plane_type *plane_type;
348 };
349 
350 #define AMDGPU_MAX_BL_LEVEL 0xFF
351 
352 struct amdgpu_backlight_privdata {
353 	struct amdgpu_encoder *encoder;
354 	uint8_t negative;
355 };
356 
357 struct amdgpu_atom_ss {
358 	uint16_t percentage;
359 	uint16_t percentage_divider;
360 	uint8_t type;
361 	uint16_t step;
362 	uint8_t delay;
363 	uint8_t range;
364 	uint8_t refdiv;
365 	/* asic_ss */
366 	uint16_t rate;
367 	uint16_t amount;
368 };
369 
370 struct amdgpu_crtc {
371 	struct drm_crtc base;
372 	int crtc_id;
373 	bool enabled;
374 	bool can_tile;
375 	uint32_t crtc_offset;
376 	struct drm_gem_object *cursor_bo;
377 	uint64_t cursor_addr;
378 	int cursor_x;
379 	int cursor_y;
380 	int cursor_hot_x;
381 	int cursor_hot_y;
382 	int cursor_width;
383 	int cursor_height;
384 	int max_cursor_width;
385 	int max_cursor_height;
386 	enum amdgpu_rmx_type rmx_type;
387 	u8 h_border;
388 	u8 v_border;
389 	fixed20_12 vsc;
390 	fixed20_12 hsc;
391 	struct drm_display_mode native_mode;
392 	u32 pll_id;
393 	/* page flipping */
394 	struct amdgpu_flip_work *pflip_works;
395 	enum amdgpu_flip_status pflip_status;
396 	int deferred_flip_completion;
397 	/* parameters access from DM IRQ handler */
398 	struct dm_irq_params dm_irq_params;
399 	/* pll sharing */
400 	struct amdgpu_atom_ss ss;
401 	bool ss_enabled;
402 	u32 adjusted_clock;
403 	int bpc;
404 	u32 pll_reference_div;
405 	u32 pll_post_div;
406 	u32 pll_flags;
407 	struct drm_encoder *encoder;
408 	struct drm_connector *connector;
409 	/* for dpm */
410 	u32 line_time;
411 	u32 wm_low;
412 	u32 wm_high;
413 	u32 lb_vblank_lead_lines;
414 	struct drm_display_mode hw_mode;
415 	/* for virtual dce */
416 	struct hrtimer vblank_timer;
417 	enum amdgpu_interrupt_state vsync_timer_enabled;
418 
419 	int otg_inst;
420 	struct drm_pending_vblank_event *event;
421 };
422 
423 struct amdgpu_encoder_atom_dig {
424 	bool linkb;
425 	/* atom dig */
426 	bool coherent_mode;
427 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
428 	/* atom lvds/edp */
429 	uint32_t lcd_misc;
430 	uint16_t panel_pwr_delay;
431 	uint32_t lcd_ss_id;
432 	/* panel mode */
433 	struct drm_display_mode native_mode;
434 	struct backlight_device *bl_dev;
435 	int dpms_mode;
436 	uint8_t backlight_level;
437 	int panel_mode;
438 	struct amdgpu_afmt *afmt;
439 };
440 
441 struct amdgpu_encoder {
442 	struct drm_encoder base;
443 	uint32_t encoder_enum;
444 	uint32_t encoder_id;
445 	uint32_t devices;
446 	uint32_t active_device;
447 	uint32_t flags;
448 	uint32_t pixel_clock;
449 	enum amdgpu_rmx_type rmx_type;
450 	enum amdgpu_underscan_type underscan_type;
451 	uint32_t underscan_hborder;
452 	uint32_t underscan_vborder;
453 	struct drm_display_mode native_mode;
454 	void *enc_priv;
455 	int audio_polling_active;
456 	bool is_ext_encoder;
457 	u16 caps;
458 };
459 
460 struct amdgpu_connector_atom_dig {
461 	/* displayport */
462 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
463 	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
464 	u8 dp_sink_type;
465 	int dp_clock;
466 	int dp_lane_count;
467 	bool edp_on;
468 };
469 
470 struct amdgpu_gpio_rec {
471 	bool valid;
472 	u8 id;
473 	u32 reg;
474 	u32 mask;
475 	u32 shift;
476 };
477 
478 struct amdgpu_hpd {
479 	enum amdgpu_hpd_id hpd;
480 	u8 plugged_state;
481 	struct amdgpu_gpio_rec gpio;
482 };
483 
484 struct amdgpu_router {
485 	u32 router_id;
486 	struct amdgpu_i2c_bus_rec i2c_info;
487 	u8 i2c_addr;
488 	/* i2c mux */
489 	bool ddc_valid;
490 	u8 ddc_mux_type;
491 	u8 ddc_mux_control_pin;
492 	u8 ddc_mux_state;
493 	/* clock/data mux */
494 	bool cd_valid;
495 	u8 cd_mux_type;
496 	u8 cd_mux_control_pin;
497 	u8 cd_mux_state;
498 };
499 
500 enum amdgpu_connector_audio {
501 	AMDGPU_AUDIO_DISABLE = 0,
502 	AMDGPU_AUDIO_ENABLE = 1,
503 	AMDGPU_AUDIO_AUTO = 2
504 };
505 
506 enum amdgpu_connector_dither {
507 	AMDGPU_FMT_DITHER_DISABLE = 0,
508 	AMDGPU_FMT_DITHER_ENABLE = 1,
509 };
510 
511 struct amdgpu_dm_dp_aux {
512 	struct drm_dp_aux aux;
513 	struct ddc_service *ddc_service;
514 };
515 
516 struct amdgpu_i2c_adapter {
517 	struct i2c_adapter base;
518 
519 	struct ddc_service *ddc_service;
520 };
521 
522 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
523 
524 struct amdgpu_connector {
525 	struct drm_connector base;
526 	uint32_t connector_id;
527 	uint32_t devices;
528 	struct amdgpu_i2c_chan *ddc_bus;
529 	/* some systems have an hdmi and vga port with a shared ddc line */
530 	bool shared_ddc;
531 	bool use_digital;
532 	/* we need to mind the EDID between detect
533 	   and get modes due to analog/digital/tvencoder */
534 	struct edid *edid;
535 	void *con_priv;
536 	bool dac_load_detect;
537 	bool detected_by_load; /* if the connection status was determined by load */
538 	uint16_t connector_object_id;
539 	struct amdgpu_hpd hpd;
540 	struct amdgpu_router router;
541 	struct amdgpu_i2c_chan *router_bus;
542 	enum amdgpu_connector_audio audio;
543 	enum amdgpu_connector_dither dither;
544 	unsigned pixelclock_for_modeset;
545 };
546 
547 /* TODO: start to use this struct and remove same field from base one */
548 struct amdgpu_mst_connector {
549 	struct amdgpu_connector base;
550 
551 	struct drm_dp_mst_topology_mgr mst_mgr;
552 	struct amdgpu_dm_dp_aux dm_dp_aux;
553 	struct drm_dp_mst_port *port;
554 	struct amdgpu_connector *mst_port;
555 	bool is_mst_connector;
556 	struct amdgpu_encoder *mst_encoder;
557 };
558 
559 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
560 				((em) == ATOM_ENCODER_MODE_DP_MST))
561 
562 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
563 #define DRM_SCANOUTPOS_VALID        (1 << 0)
564 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
565 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
566 #define USE_REAL_VBLANKSTART		(1 << 30)
567 #define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
568 
569 void amdgpu_link_encoder_connector(struct drm_device *dev);
570 
571 struct drm_connector *
572 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
573 struct drm_connector *
574 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
575 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
576 				    u32 pixel_clock);
577 
578 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
579 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
580 
581 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
582 			      bool use_aux);
583 
584 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
585 
586 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
587 			unsigned int pipe, unsigned int flags, int *vpos,
588 			int *hpos, ktime_t *stime, ktime_t *etime,
589 			const struct drm_display_mode *mode);
590 
591 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
592 
593 void amdgpu_enc_destroy(struct drm_encoder *encoder);
594 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
595 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
596 				const struct drm_display_mode *mode,
597 				struct drm_display_mode *adjusted_mode);
598 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
599 			     struct drm_display_mode *adjusted_mode);
600 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
601 
602 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
603 			bool in_vblank_irq, int *vpos,
604 			int *hpos, ktime_t *stime, ktime_t *etime,
605 			const struct drm_display_mode *mode);
606 
607 /* amdgpu_display.c */
608 void amdgpu_display_print_display_setup(struct drm_device *dev);
609 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
610 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
611 				   struct drm_modeset_acquire_ctx *ctx);
612 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
613 				struct drm_framebuffer *fb,
614 				struct drm_pending_vblank_event *event,
615 				uint32_t page_flip_flags, uint32_t target,
616 				struct drm_modeset_acquire_ctx *ctx);
617 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
618 
619 #endif
620