1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_encoder.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_fixed.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fb_helper.h> 40 #include <drm/drm_plane_helper.h> 41 #include <drm/drm_fb_helper.h> 42 #include <linux/i2c.h> 43 #include <linux/i2c-algo-bit.h> 44 #include <linux/hrtimer.h> 45 #include "amdgpu_irq.h" 46 47 #include <drm/drm_dp_mst_helper.h> 48 #include "modules/inc/mod_freesync.h" 49 50 struct amdgpu_bo; 51 struct amdgpu_device; 52 struct amdgpu_encoder; 53 struct amdgpu_router; 54 struct amdgpu_hpd; 55 56 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 57 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 58 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 59 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 60 #define to_amdgpu_plane(x) container_of(x, struct amdgpu_plane, base) 61 62 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base); 63 64 #define AMDGPU_MAX_HPD_PINS 6 65 #define AMDGPU_MAX_CRTCS 6 66 #define AMDGPU_MAX_PLANES 6 67 #define AMDGPU_MAX_AFMT_BLOCKS 9 68 69 enum amdgpu_rmx_type { 70 RMX_OFF, 71 RMX_FULL, 72 RMX_CENTER, 73 RMX_ASPECT 74 }; 75 76 enum amdgpu_underscan_type { 77 UNDERSCAN_OFF, 78 UNDERSCAN_ON, 79 UNDERSCAN_AUTO, 80 }; 81 82 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 83 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 84 85 enum amdgpu_hpd_id { 86 AMDGPU_HPD_1 = 0, 87 AMDGPU_HPD_2, 88 AMDGPU_HPD_3, 89 AMDGPU_HPD_4, 90 AMDGPU_HPD_5, 91 AMDGPU_HPD_6, 92 AMDGPU_HPD_LAST, 93 AMDGPU_HPD_NONE = 0xff, 94 }; 95 96 enum amdgpu_crtc_irq { 97 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 98 AMDGPU_CRTC_IRQ_VBLANK2, 99 AMDGPU_CRTC_IRQ_VBLANK3, 100 AMDGPU_CRTC_IRQ_VBLANK4, 101 AMDGPU_CRTC_IRQ_VBLANK5, 102 AMDGPU_CRTC_IRQ_VBLANK6, 103 AMDGPU_CRTC_IRQ_VLINE1, 104 AMDGPU_CRTC_IRQ_VLINE2, 105 AMDGPU_CRTC_IRQ_VLINE3, 106 AMDGPU_CRTC_IRQ_VLINE4, 107 AMDGPU_CRTC_IRQ_VLINE5, 108 AMDGPU_CRTC_IRQ_VLINE6, 109 AMDGPU_CRTC_IRQ_LAST, 110 AMDGPU_CRTC_IRQ_NONE = 0xff 111 }; 112 113 enum amdgpu_pageflip_irq { 114 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 115 AMDGPU_PAGEFLIP_IRQ_D2, 116 AMDGPU_PAGEFLIP_IRQ_D3, 117 AMDGPU_PAGEFLIP_IRQ_D4, 118 AMDGPU_PAGEFLIP_IRQ_D5, 119 AMDGPU_PAGEFLIP_IRQ_D6, 120 AMDGPU_PAGEFLIP_IRQ_LAST, 121 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 122 }; 123 124 enum amdgpu_flip_status { 125 AMDGPU_FLIP_NONE, 126 AMDGPU_FLIP_PENDING, 127 AMDGPU_FLIP_SUBMITTED 128 }; 129 130 #define AMDGPU_MAX_I2C_BUS 16 131 132 /* amdgpu gpio-based i2c 133 * 1. "mask" reg and bits 134 * grabs the gpio pins for software use 135 * 0=not held 1=held 136 * 2. "a" reg and bits 137 * output pin value 138 * 0=low 1=high 139 * 3. "en" reg and bits 140 * sets the pin direction 141 * 0=input 1=output 142 * 4. "y" reg and bits 143 * input pin value 144 * 0=low 1=high 145 */ 146 struct amdgpu_i2c_bus_rec { 147 bool valid; 148 /* id used by atom */ 149 uint8_t i2c_id; 150 /* id used by atom */ 151 enum amdgpu_hpd_id hpd; 152 /* can be used with hw i2c engine */ 153 bool hw_capable; 154 /* uses multi-media i2c engine */ 155 bool mm_i2c; 156 /* regs and bits */ 157 uint32_t mask_clk_reg; 158 uint32_t mask_data_reg; 159 uint32_t a_clk_reg; 160 uint32_t a_data_reg; 161 uint32_t en_clk_reg; 162 uint32_t en_data_reg; 163 uint32_t y_clk_reg; 164 uint32_t y_data_reg; 165 uint32_t mask_clk_mask; 166 uint32_t mask_data_mask; 167 uint32_t a_clk_mask; 168 uint32_t a_data_mask; 169 uint32_t en_clk_mask; 170 uint32_t en_data_mask; 171 uint32_t y_clk_mask; 172 uint32_t y_data_mask; 173 }; 174 175 #define AMDGPU_MAX_BIOS_CONNECTOR 16 176 177 /* pll flags */ 178 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 179 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 180 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 181 #define AMDGPU_PLL_LEGACY (1 << 3) 182 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 183 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 184 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 185 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 186 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 187 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 188 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 189 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 190 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 191 #define AMDGPU_PLL_IS_LCD (1 << 13) 192 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 193 194 struct amdgpu_pll { 195 /* reference frequency */ 196 uint32_t reference_freq; 197 198 /* fixed dividers */ 199 uint32_t reference_div; 200 uint32_t post_div; 201 202 /* pll in/out limits */ 203 uint32_t pll_in_min; 204 uint32_t pll_in_max; 205 uint32_t pll_out_min; 206 uint32_t pll_out_max; 207 uint32_t lcd_pll_out_min; 208 uint32_t lcd_pll_out_max; 209 uint32_t best_vco; 210 211 /* divider limits */ 212 uint32_t min_ref_div; 213 uint32_t max_ref_div; 214 uint32_t min_post_div; 215 uint32_t max_post_div; 216 uint32_t min_feedback_div; 217 uint32_t max_feedback_div; 218 uint32_t min_frac_feedback_div; 219 uint32_t max_frac_feedback_div; 220 221 /* flags for the current clock */ 222 uint32_t flags; 223 224 /* pll id */ 225 uint32_t id; 226 }; 227 228 struct amdgpu_i2c_chan { 229 struct i2c_adapter adapter; 230 struct drm_device *dev; 231 struct i2c_algo_bit_data bit; 232 struct amdgpu_i2c_bus_rec rec; 233 struct drm_dp_aux aux; 234 bool has_aux; 235 struct mutex mutex; 236 }; 237 238 struct amdgpu_fbdev; 239 240 struct amdgpu_afmt { 241 bool enabled; 242 int offset; 243 bool last_buffer_filled_status; 244 int id; 245 struct amdgpu_audio_pin *pin; 246 }; 247 248 /* 249 * Audio 250 */ 251 struct amdgpu_audio_pin { 252 int channels; 253 int rate; 254 int bits_per_sample; 255 u8 status_bits; 256 u8 category_code; 257 u32 offset; 258 bool connected; 259 u32 id; 260 }; 261 262 struct amdgpu_audio { 263 bool enabled; 264 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 265 int num_pins; 266 }; 267 268 struct amdgpu_display_funcs { 269 /* display watermarks */ 270 void (*bandwidth_update)(struct amdgpu_device *adev); 271 /* get frame count */ 272 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 273 /* wait for vblank */ 274 void (*vblank_wait)(struct amdgpu_device *adev, int crtc); 275 /* set backlight level */ 276 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 277 u8 level); 278 /* get backlight level */ 279 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 280 /* hotplug detect */ 281 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 282 void (*hpd_set_polarity)(struct amdgpu_device *adev, 283 enum amdgpu_hpd_id hpd); 284 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 285 /* pageflipping */ 286 void (*page_flip)(struct amdgpu_device *adev, 287 int crtc_id, u64 crtc_base, bool async); 288 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 289 u32 *vbl, u32 *position); 290 /* display topology setup */ 291 void (*add_encoder)(struct amdgpu_device *adev, 292 uint32_t encoder_enum, 293 uint32_t supported_device, 294 u16 caps); 295 void (*add_connector)(struct amdgpu_device *adev, 296 uint32_t connector_id, 297 uint32_t supported_device, 298 int connector_type, 299 struct amdgpu_i2c_bus_rec *i2c_bus, 300 uint16_t connector_object_id, 301 struct amdgpu_hpd *hpd, 302 struct amdgpu_router *router); 303 /* it is used to enter or exit into free sync mode */ 304 int (*notify_freesync)(struct drm_device *dev, void *data, 305 struct drm_file *filp); 306 /* it is used to allow enablement of freesync mode */ 307 int (*set_freesync_property)(struct drm_connector *connector, 308 struct drm_property *property, 309 uint64_t val); 310 311 312 }; 313 314 struct amdgpu_framebuffer { 315 struct drm_framebuffer base; 316 struct drm_gem_object *obj; 317 318 /* caching for later use */ 319 uint64_t address; 320 }; 321 322 struct amdgpu_fbdev { 323 struct drm_fb_helper helper; 324 struct amdgpu_framebuffer rfb; 325 struct list_head fbdev_list; 326 struct amdgpu_device *adev; 327 }; 328 329 struct amdgpu_mode_info { 330 struct atom_context *atom_context; 331 struct card_info *atom_card_info; 332 bool mode_config_initialized; 333 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 334 struct amdgpu_plane *planes[AMDGPU_MAX_PLANES]; 335 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 336 /* DVI-I properties */ 337 struct drm_property *coherent_mode_property; 338 /* DAC enable load detect */ 339 struct drm_property *load_detect_property; 340 /* underscan */ 341 struct drm_property *underscan_property; 342 struct drm_property *underscan_hborder_property; 343 struct drm_property *underscan_vborder_property; 344 /* audio */ 345 struct drm_property *audio_property; 346 /* FMT dithering */ 347 struct drm_property *dither_property; 348 /* hardcoded DFP edid from BIOS */ 349 struct edid *bios_hardcoded_edid; 350 int bios_hardcoded_edid_size; 351 352 /* pointer to fbdev info structure */ 353 struct amdgpu_fbdev *rfbdev; 354 /* firmware flags */ 355 u16 firmware_flags; 356 /* pointer to backlight encoder */ 357 struct amdgpu_encoder *bl_encoder; 358 struct amdgpu_audio audio; /* audio stuff */ 359 int num_crtc; /* number of crtcs */ 360 int num_hpd; /* number of hpd pins */ 361 int num_dig; /* number of dig blocks */ 362 int disp_priority; 363 const struct amdgpu_display_funcs *funcs; 364 const enum drm_plane_type *plane_type; 365 }; 366 367 #define AMDGPU_MAX_BL_LEVEL 0xFF 368 369 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 370 371 struct amdgpu_backlight_privdata { 372 struct amdgpu_encoder *encoder; 373 uint8_t negative; 374 }; 375 376 #endif 377 378 struct amdgpu_atom_ss { 379 uint16_t percentage; 380 uint16_t percentage_divider; 381 uint8_t type; 382 uint16_t step; 383 uint8_t delay; 384 uint8_t range; 385 uint8_t refdiv; 386 /* asic_ss */ 387 uint16_t rate; 388 uint16_t amount; 389 }; 390 391 struct amdgpu_crtc { 392 struct drm_crtc base; 393 int crtc_id; 394 bool enabled; 395 bool can_tile; 396 uint32_t crtc_offset; 397 struct drm_gem_object *cursor_bo; 398 uint64_t cursor_addr; 399 int cursor_x; 400 int cursor_y; 401 int cursor_hot_x; 402 int cursor_hot_y; 403 int cursor_width; 404 int cursor_height; 405 int max_cursor_width; 406 int max_cursor_height; 407 enum amdgpu_rmx_type rmx_type; 408 u8 h_border; 409 u8 v_border; 410 fixed20_12 vsc; 411 fixed20_12 hsc; 412 struct drm_display_mode native_mode; 413 u32 pll_id; 414 /* page flipping */ 415 struct amdgpu_flip_work *pflip_works; 416 enum amdgpu_flip_status pflip_status; 417 int deferred_flip_completion; 418 /* pll sharing */ 419 struct amdgpu_atom_ss ss; 420 bool ss_enabled; 421 u32 adjusted_clock; 422 int bpc; 423 u32 pll_reference_div; 424 u32 pll_post_div; 425 u32 pll_flags; 426 struct drm_encoder *encoder; 427 struct drm_connector *connector; 428 /* for dpm */ 429 u32 line_time; 430 u32 wm_low; 431 u32 wm_high; 432 u32 lb_vblank_lead_lines; 433 struct drm_display_mode hw_mode; 434 /* for virtual dce */ 435 struct hrtimer vblank_timer; 436 enum amdgpu_interrupt_state vsync_timer_enabled; 437 438 int otg_inst; 439 /* After Set Mode stream will be non-NULL */ 440 const struct dc_stream *stream; 441 struct drm_pending_vblank_event *event; 442 }; 443 444 struct amdgpu_plane { 445 struct drm_plane base; 446 enum drm_plane_type plane_type; 447 }; 448 449 struct amdgpu_encoder_atom_dig { 450 bool linkb; 451 /* atom dig */ 452 bool coherent_mode; 453 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 454 /* atom lvds/edp */ 455 uint32_t lcd_misc; 456 uint16_t panel_pwr_delay; 457 uint32_t lcd_ss_id; 458 /* panel mode */ 459 struct drm_display_mode native_mode; 460 struct backlight_device *bl_dev; 461 int dpms_mode; 462 uint8_t backlight_level; 463 int panel_mode; 464 struct amdgpu_afmt *afmt; 465 }; 466 467 struct amdgpu_encoder { 468 struct drm_encoder base; 469 uint32_t encoder_enum; 470 uint32_t encoder_id; 471 uint32_t devices; 472 uint32_t active_device; 473 uint32_t flags; 474 uint32_t pixel_clock; 475 enum amdgpu_rmx_type rmx_type; 476 enum amdgpu_underscan_type underscan_type; 477 uint32_t underscan_hborder; 478 uint32_t underscan_vborder; 479 struct drm_display_mode native_mode; 480 void *enc_priv; 481 int audio_polling_active; 482 bool is_ext_encoder; 483 u16 caps; 484 }; 485 486 struct amdgpu_connector_atom_dig { 487 /* displayport */ 488 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 489 u8 dp_sink_type; 490 int dp_clock; 491 int dp_lane_count; 492 bool edp_on; 493 }; 494 495 struct amdgpu_gpio_rec { 496 bool valid; 497 u8 id; 498 u32 reg; 499 u32 mask; 500 u32 shift; 501 }; 502 503 struct amdgpu_hpd { 504 enum amdgpu_hpd_id hpd; 505 u8 plugged_state; 506 struct amdgpu_gpio_rec gpio; 507 }; 508 509 struct amdgpu_router { 510 u32 router_id; 511 struct amdgpu_i2c_bus_rec i2c_info; 512 u8 i2c_addr; 513 /* i2c mux */ 514 bool ddc_valid; 515 u8 ddc_mux_type; 516 u8 ddc_mux_control_pin; 517 u8 ddc_mux_state; 518 /* clock/data mux */ 519 bool cd_valid; 520 u8 cd_mux_type; 521 u8 cd_mux_control_pin; 522 u8 cd_mux_state; 523 }; 524 525 enum amdgpu_connector_audio { 526 AMDGPU_AUDIO_DISABLE = 0, 527 AMDGPU_AUDIO_ENABLE = 1, 528 AMDGPU_AUDIO_AUTO = 2 529 }; 530 531 enum amdgpu_connector_dither { 532 AMDGPU_FMT_DITHER_DISABLE = 0, 533 AMDGPU_FMT_DITHER_ENABLE = 1, 534 }; 535 536 struct amdgpu_dm_dp_aux { 537 struct drm_dp_aux aux; 538 struct ddc_service *ddc_service; 539 }; 540 541 struct amdgpu_i2c_adapter { 542 struct i2c_adapter base; 543 544 struct ddc_service *ddc_service; 545 }; 546 547 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 548 549 struct amdgpu_connector { 550 struct drm_connector base; 551 uint32_t connector_id; 552 uint32_t devices; 553 struct amdgpu_i2c_chan *ddc_bus; 554 /* some systems have an hdmi and vga port with a shared ddc line */ 555 bool shared_ddc; 556 bool use_digital; 557 /* we need to mind the EDID between detect 558 and get modes due to analog/digital/tvencoder */ 559 struct edid *edid; 560 /* number of modes generated from EDID at 'dc_sink' */ 561 int num_modes; 562 /* The 'old' sink - before an HPD. 563 * The 'current' sink is in dc_link->sink. */ 564 struct dc_sink *dc_sink; 565 struct dc_link *dc_link; 566 struct dc_sink *dc_em_sink; 567 const struct dc_stream *stream; 568 void *con_priv; 569 bool dac_load_detect; 570 bool detected_by_load; /* if the connection status was determined by load */ 571 uint16_t connector_object_id; 572 struct amdgpu_hpd hpd; 573 struct amdgpu_router router; 574 struct amdgpu_i2c_chan *router_bus; 575 enum amdgpu_connector_audio audio; 576 enum amdgpu_connector_dither dither; 577 unsigned pixelclock_for_modeset; 578 579 struct drm_dp_mst_topology_mgr mst_mgr; 580 struct amdgpu_dm_dp_aux dm_dp_aux; 581 struct drm_dp_mst_port *port; 582 struct amdgpu_connector *mst_port; 583 struct amdgpu_encoder *mst_encoder; 584 struct semaphore mst_sem; 585 586 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 587 struct amdgpu_i2c_adapter *i2c; 588 589 /* Monitor range limits */ 590 int min_vfreq ; 591 int max_vfreq ; 592 int pixel_clock_mhz; 593 594 /*freesync caps*/ 595 struct mod_freesync_caps caps; 596 597 struct mutex hpd_lock; 598 599 }; 600 601 /* TODO: start to use this struct and remove same field from base one */ 602 struct amdgpu_mst_connector { 603 struct amdgpu_connector base; 604 605 struct drm_dp_mst_topology_mgr mst_mgr; 606 struct amdgpu_dm_dp_aux dm_dp_aux; 607 struct drm_dp_mst_port *port; 608 struct amdgpu_connector *mst_port; 609 bool is_mst_connector; 610 struct amdgpu_encoder *mst_encoder; 611 }; 612 613 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 614 ((em) == ATOM_ENCODER_MODE_DP_MST)) 615 616 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ 617 #define DRM_SCANOUTPOS_VALID (1 << 0) 618 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 619 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 620 #define USE_REAL_VBLANKSTART (1 << 30) 621 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 622 623 void amdgpu_link_encoder_connector(struct drm_device *dev); 624 625 struct drm_connector * 626 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 627 struct drm_connector * 628 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 629 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 630 u32 pixel_clock); 631 632 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 633 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 634 635 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux); 636 637 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 638 639 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 640 unsigned int flags, int *vpos, int *hpos, 641 ktime_t *stime, ktime_t *etime, 642 const struct drm_display_mode *mode); 643 644 int amdgpu_framebuffer_init(struct drm_device *dev, 645 struct amdgpu_framebuffer *rfb, 646 const struct drm_mode_fb_cmd2 *mode_cmd, 647 struct drm_gem_object *obj); 648 649 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 650 651 void amdgpu_enc_destroy(struct drm_encoder *encoder); 652 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 653 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 654 const struct drm_display_mode *mode, 655 struct drm_display_mode *adjusted_mode); 656 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 657 struct drm_display_mode *adjusted_mode); 658 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 659 660 /* fbdev layer */ 661 int amdgpu_fbdev_init(struct amdgpu_device *adev); 662 void amdgpu_fbdev_fini(struct amdgpu_device *adev); 663 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 664 int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 665 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 666 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); 667 668 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); 669 670 671 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 672 673 /* amdgpu_display.c */ 674 void amdgpu_print_display_setup(struct drm_device *dev); 675 int amdgpu_modeset_create_props(struct amdgpu_device *adev); 676 int amdgpu_crtc_set_config(struct drm_mode_set *set, 677 struct drm_modeset_acquire_ctx *ctx); 678 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc, 679 struct drm_framebuffer *fb, 680 struct drm_pending_vblank_event *event, 681 uint32_t page_flip_flags, uint32_t target, 682 struct drm_modeset_acquire_ctx *ctx); 683 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 684 685 #endif 686