1 /*
2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3  *                VA Linux Systems Inc., Fremont, California.
4  * Copyright 2008 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Original Authors:
25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26  *
27  * Kernel port Author: Dave Airlie
28  */
29 
30 #ifndef AMDGPU_MODE_H
31 #define AMDGPU_MODE_H
32 
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_plane_helper.h>
41 #include <linux/i2c.h>
42 #include <linux/i2c-algo-bit.h>
43 #include <linux/hrtimer.h>
44 #include "amdgpu_irq.h"
45 
46 struct amdgpu_bo;
47 struct amdgpu_device;
48 struct amdgpu_encoder;
49 struct amdgpu_router;
50 struct amdgpu_hpd;
51 
52 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
53 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
54 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
55 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
56 
57 #define AMDGPU_MAX_HPD_PINS 6
58 #define AMDGPU_MAX_CRTCS 6
59 #define AMDGPU_MAX_AFMT_BLOCKS 9
60 
61 enum amdgpu_rmx_type {
62 	RMX_OFF,
63 	RMX_FULL,
64 	RMX_CENTER,
65 	RMX_ASPECT
66 };
67 
68 enum amdgpu_underscan_type {
69 	UNDERSCAN_OFF,
70 	UNDERSCAN_ON,
71 	UNDERSCAN_AUTO,
72 };
73 
74 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
75 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
76 
77 enum amdgpu_hpd_id {
78 	AMDGPU_HPD_1 = 0,
79 	AMDGPU_HPD_2,
80 	AMDGPU_HPD_3,
81 	AMDGPU_HPD_4,
82 	AMDGPU_HPD_5,
83 	AMDGPU_HPD_6,
84 	AMDGPU_HPD_LAST,
85 	AMDGPU_HPD_NONE = 0xff,
86 };
87 
88 enum amdgpu_crtc_irq {
89 	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
90 	AMDGPU_CRTC_IRQ_VBLANK2,
91 	AMDGPU_CRTC_IRQ_VBLANK3,
92 	AMDGPU_CRTC_IRQ_VBLANK4,
93 	AMDGPU_CRTC_IRQ_VBLANK5,
94 	AMDGPU_CRTC_IRQ_VBLANK6,
95 	AMDGPU_CRTC_IRQ_VLINE1,
96 	AMDGPU_CRTC_IRQ_VLINE2,
97 	AMDGPU_CRTC_IRQ_VLINE3,
98 	AMDGPU_CRTC_IRQ_VLINE4,
99 	AMDGPU_CRTC_IRQ_VLINE5,
100 	AMDGPU_CRTC_IRQ_VLINE6,
101 	AMDGPU_CRTC_IRQ_LAST,
102 	AMDGPU_CRTC_IRQ_NONE = 0xff
103 };
104 
105 enum amdgpu_pageflip_irq {
106 	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
107 	AMDGPU_PAGEFLIP_IRQ_D2,
108 	AMDGPU_PAGEFLIP_IRQ_D3,
109 	AMDGPU_PAGEFLIP_IRQ_D4,
110 	AMDGPU_PAGEFLIP_IRQ_D5,
111 	AMDGPU_PAGEFLIP_IRQ_D6,
112 	AMDGPU_PAGEFLIP_IRQ_LAST,
113 	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
114 };
115 
116 enum amdgpu_flip_status {
117 	AMDGPU_FLIP_NONE,
118 	AMDGPU_FLIP_PENDING,
119 	AMDGPU_FLIP_SUBMITTED
120 };
121 
122 #define AMDGPU_MAX_I2C_BUS 16
123 
124 /* amdgpu gpio-based i2c
125  * 1. "mask" reg and bits
126  *    grabs the gpio pins for software use
127  *    0=not held  1=held
128  * 2. "a" reg and bits
129  *    output pin value
130  *    0=low 1=high
131  * 3. "en" reg and bits
132  *    sets the pin direction
133  *    0=input 1=output
134  * 4. "y" reg and bits
135  *    input pin value
136  *    0=low 1=high
137  */
138 struct amdgpu_i2c_bus_rec {
139 	bool valid;
140 	/* id used by atom */
141 	uint8_t i2c_id;
142 	/* id used by atom */
143 	enum amdgpu_hpd_id hpd;
144 	/* can be used with hw i2c engine */
145 	bool hw_capable;
146 	/* uses multi-media i2c engine */
147 	bool mm_i2c;
148 	/* regs and bits */
149 	uint32_t mask_clk_reg;
150 	uint32_t mask_data_reg;
151 	uint32_t a_clk_reg;
152 	uint32_t a_data_reg;
153 	uint32_t en_clk_reg;
154 	uint32_t en_data_reg;
155 	uint32_t y_clk_reg;
156 	uint32_t y_data_reg;
157 	uint32_t mask_clk_mask;
158 	uint32_t mask_data_mask;
159 	uint32_t a_clk_mask;
160 	uint32_t a_data_mask;
161 	uint32_t en_clk_mask;
162 	uint32_t en_data_mask;
163 	uint32_t y_clk_mask;
164 	uint32_t y_data_mask;
165 };
166 
167 #define AMDGPU_MAX_BIOS_CONNECTOR 16
168 
169 /* pll flags */
170 #define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
171 #define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
172 #define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
173 #define AMDGPU_PLL_LEGACY               (1 << 3)
174 #define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
175 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
176 #define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
177 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
178 #define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
179 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
180 #define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
181 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
182 #define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
183 #define AMDGPU_PLL_IS_LCD               (1 << 13)
184 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
185 
186 struct amdgpu_pll {
187 	/* reference frequency */
188 	uint32_t reference_freq;
189 
190 	/* fixed dividers */
191 	uint32_t reference_div;
192 	uint32_t post_div;
193 
194 	/* pll in/out limits */
195 	uint32_t pll_in_min;
196 	uint32_t pll_in_max;
197 	uint32_t pll_out_min;
198 	uint32_t pll_out_max;
199 	uint32_t lcd_pll_out_min;
200 	uint32_t lcd_pll_out_max;
201 	uint32_t best_vco;
202 
203 	/* divider limits */
204 	uint32_t min_ref_div;
205 	uint32_t max_ref_div;
206 	uint32_t min_post_div;
207 	uint32_t max_post_div;
208 	uint32_t min_feedback_div;
209 	uint32_t max_feedback_div;
210 	uint32_t min_frac_feedback_div;
211 	uint32_t max_frac_feedback_div;
212 
213 	/* flags for the current clock */
214 	uint32_t flags;
215 
216 	/* pll id */
217 	uint32_t id;
218 };
219 
220 struct amdgpu_i2c_chan {
221 	struct i2c_adapter adapter;
222 	struct drm_device *dev;
223 	struct i2c_algo_bit_data bit;
224 	struct amdgpu_i2c_bus_rec rec;
225 	struct drm_dp_aux aux;
226 	bool has_aux;
227 	struct mutex mutex;
228 };
229 
230 struct amdgpu_fbdev;
231 
232 struct amdgpu_afmt {
233 	bool enabled;
234 	int offset;
235 	bool last_buffer_filled_status;
236 	int id;
237 	struct amdgpu_audio_pin *pin;
238 };
239 
240 /*
241  * Audio
242  */
243 struct amdgpu_audio_pin {
244 	int			channels;
245 	int			rate;
246 	int			bits_per_sample;
247 	u8			status_bits;
248 	u8			category_code;
249 	u32			offset;
250 	bool			connected;
251 	u32			id;
252 };
253 
254 struct amdgpu_audio {
255 	bool enabled;
256 	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
257 	int num_pins;
258 };
259 
260 struct amdgpu_display_funcs {
261 	/* display watermarks */
262 	void (*bandwidth_update)(struct amdgpu_device *adev);
263 	/* get frame count */
264 	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
265 	/* wait for vblank */
266 	void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
267 	/* set backlight level */
268 	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
269 				    u8 level);
270 	/* get backlight level */
271 	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
272 	/* hotplug detect */
273 	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
274 	void (*hpd_set_polarity)(struct amdgpu_device *adev,
275 				 enum amdgpu_hpd_id hpd);
276 	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
277 	/* pageflipping */
278 	void (*page_flip)(struct amdgpu_device *adev,
279 			  int crtc_id, u64 crtc_base, bool async);
280 	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
281 					u32 *vbl, u32 *position);
282 	/* display topology setup */
283 	void (*add_encoder)(struct amdgpu_device *adev,
284 			    uint32_t encoder_enum,
285 			    uint32_t supported_device,
286 			    u16 caps);
287 	void (*add_connector)(struct amdgpu_device *adev,
288 			      uint32_t connector_id,
289 			      uint32_t supported_device,
290 			      int connector_type,
291 			      struct amdgpu_i2c_bus_rec *i2c_bus,
292 			      uint16_t connector_object_id,
293 			      struct amdgpu_hpd *hpd,
294 			      struct amdgpu_router *router);
295 };
296 
297 struct amdgpu_mode_info {
298 	struct atom_context *atom_context;
299 	struct card_info *atom_card_info;
300 	bool mode_config_initialized;
301 	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
302 	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
303 	/* DVI-I properties */
304 	struct drm_property *coherent_mode_property;
305 	/* DAC enable load detect */
306 	struct drm_property *load_detect_property;
307 	/* underscan */
308 	struct drm_property *underscan_property;
309 	struct drm_property *underscan_hborder_property;
310 	struct drm_property *underscan_vborder_property;
311 	/* audio */
312 	struct drm_property *audio_property;
313 	/* FMT dithering */
314 	struct drm_property *dither_property;
315 	/* hardcoded DFP edid from BIOS */
316 	struct edid *bios_hardcoded_edid;
317 	int bios_hardcoded_edid_size;
318 
319 	/* pointer to fbdev info structure */
320 	struct amdgpu_fbdev *rfbdev;
321 	/* firmware flags */
322 	u16 firmware_flags;
323 	/* pointer to backlight encoder */
324 	struct amdgpu_encoder *bl_encoder;
325 	struct amdgpu_audio	audio; /* audio stuff */
326 	int			num_crtc; /* number of crtcs */
327 	int			num_hpd; /* number of hpd pins */
328 	int			num_dig; /* number of dig blocks */
329 	int			disp_priority;
330 	const struct amdgpu_display_funcs *funcs;
331 };
332 
333 #define AMDGPU_MAX_BL_LEVEL 0xFF
334 
335 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
336 
337 struct amdgpu_backlight_privdata {
338 	struct amdgpu_encoder *encoder;
339 	uint8_t negative;
340 };
341 
342 #endif
343 
344 struct amdgpu_atom_ss {
345 	uint16_t percentage;
346 	uint16_t percentage_divider;
347 	uint8_t type;
348 	uint16_t step;
349 	uint8_t delay;
350 	uint8_t range;
351 	uint8_t refdiv;
352 	/* asic_ss */
353 	uint16_t rate;
354 	uint16_t amount;
355 };
356 
357 struct amdgpu_crtc {
358 	struct drm_crtc base;
359 	int crtc_id;
360 	bool enabled;
361 	bool can_tile;
362 	uint32_t crtc_offset;
363 	struct drm_gem_object *cursor_bo;
364 	uint64_t cursor_addr;
365 	int cursor_x;
366 	int cursor_y;
367 	int cursor_hot_x;
368 	int cursor_hot_y;
369 	int cursor_width;
370 	int cursor_height;
371 	int max_cursor_width;
372 	int max_cursor_height;
373 	enum amdgpu_rmx_type rmx_type;
374 	u8 h_border;
375 	u8 v_border;
376 	fixed20_12 vsc;
377 	fixed20_12 hsc;
378 	struct drm_display_mode native_mode;
379 	u32 pll_id;
380 	/* page flipping */
381 	struct amdgpu_flip_work *pflip_works;
382 	enum amdgpu_flip_status pflip_status;
383 	int deferred_flip_completion;
384 	/* pll sharing */
385 	struct amdgpu_atom_ss ss;
386 	bool ss_enabled;
387 	u32 adjusted_clock;
388 	int bpc;
389 	u32 pll_reference_div;
390 	u32 pll_post_div;
391 	u32 pll_flags;
392 	struct drm_encoder *encoder;
393 	struct drm_connector *connector;
394 	/* for dpm */
395 	u32 line_time;
396 	u32 wm_low;
397 	u32 wm_high;
398 	u32 lb_vblank_lead_lines;
399 	struct drm_display_mode hw_mode;
400 	/* for virtual dce */
401 	struct hrtimer vblank_timer;
402 	enum amdgpu_interrupt_state vsync_timer_enabled;
403 };
404 
405 struct amdgpu_encoder_atom_dig {
406 	bool linkb;
407 	/* atom dig */
408 	bool coherent_mode;
409 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
410 	/* atom lvds/edp */
411 	uint32_t lcd_misc;
412 	uint16_t panel_pwr_delay;
413 	uint32_t lcd_ss_id;
414 	/* panel mode */
415 	struct drm_display_mode native_mode;
416 	struct backlight_device *bl_dev;
417 	int dpms_mode;
418 	uint8_t backlight_level;
419 	int panel_mode;
420 	struct amdgpu_afmt *afmt;
421 };
422 
423 struct amdgpu_encoder {
424 	struct drm_encoder base;
425 	uint32_t encoder_enum;
426 	uint32_t encoder_id;
427 	uint32_t devices;
428 	uint32_t active_device;
429 	uint32_t flags;
430 	uint32_t pixel_clock;
431 	enum amdgpu_rmx_type rmx_type;
432 	enum amdgpu_underscan_type underscan_type;
433 	uint32_t underscan_hborder;
434 	uint32_t underscan_vborder;
435 	struct drm_display_mode native_mode;
436 	void *enc_priv;
437 	int audio_polling_active;
438 	bool is_ext_encoder;
439 	u16 caps;
440 };
441 
442 struct amdgpu_connector_atom_dig {
443 	/* displayport */
444 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
445 	u8 dp_sink_type;
446 	int dp_clock;
447 	int dp_lane_count;
448 	bool edp_on;
449 };
450 
451 struct amdgpu_gpio_rec {
452 	bool valid;
453 	u8 id;
454 	u32 reg;
455 	u32 mask;
456 	u32 shift;
457 };
458 
459 struct amdgpu_hpd {
460 	enum amdgpu_hpd_id hpd;
461 	u8 plugged_state;
462 	struct amdgpu_gpio_rec gpio;
463 };
464 
465 struct amdgpu_router {
466 	u32 router_id;
467 	struct amdgpu_i2c_bus_rec i2c_info;
468 	u8 i2c_addr;
469 	/* i2c mux */
470 	bool ddc_valid;
471 	u8 ddc_mux_type;
472 	u8 ddc_mux_control_pin;
473 	u8 ddc_mux_state;
474 	/* clock/data mux */
475 	bool cd_valid;
476 	u8 cd_mux_type;
477 	u8 cd_mux_control_pin;
478 	u8 cd_mux_state;
479 };
480 
481 enum amdgpu_connector_audio {
482 	AMDGPU_AUDIO_DISABLE = 0,
483 	AMDGPU_AUDIO_ENABLE = 1,
484 	AMDGPU_AUDIO_AUTO = 2
485 };
486 
487 enum amdgpu_connector_dither {
488 	AMDGPU_FMT_DITHER_DISABLE = 0,
489 	AMDGPU_FMT_DITHER_ENABLE = 1,
490 };
491 
492 struct amdgpu_connector {
493 	struct drm_connector base;
494 	uint32_t connector_id;
495 	uint32_t devices;
496 	struct amdgpu_i2c_chan *ddc_bus;
497 	/* some systems have an hdmi and vga port with a shared ddc line */
498 	bool shared_ddc;
499 	bool use_digital;
500 	/* we need to mind the EDID between detect
501 	   and get modes due to analog/digital/tvencoder */
502 	struct edid *edid;
503 	void *con_priv;
504 	bool dac_load_detect;
505 	bool detected_by_load; /* if the connection status was determined by load */
506 	uint16_t connector_object_id;
507 	struct amdgpu_hpd hpd;
508 	struct amdgpu_router router;
509 	struct amdgpu_i2c_chan *router_bus;
510 	enum amdgpu_connector_audio audio;
511 	enum amdgpu_connector_dither dither;
512 	unsigned pixelclock_for_modeset;
513 };
514 
515 struct amdgpu_framebuffer {
516 	struct drm_framebuffer base;
517 	struct drm_gem_object *obj;
518 };
519 
520 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
521 				((em) == ATOM_ENCODER_MODE_DP_MST))
522 
523 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
524 #define DRM_SCANOUTPOS_VALID        (1 << 0)
525 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
526 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
527 #define USE_REAL_VBLANKSTART		(1 << 30)
528 #define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
529 
530 void amdgpu_link_encoder_connector(struct drm_device *dev);
531 
532 struct drm_connector *
533 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
534 struct drm_connector *
535 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
536 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
537 				    u32 pixel_clock);
538 
539 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
540 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
541 
542 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
543 
544 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
545 
546 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
547 			       unsigned int flags, int *vpos, int *hpos,
548 			       ktime_t *stime, ktime_t *etime,
549 			       const struct drm_display_mode *mode);
550 
551 int amdgpu_framebuffer_init(struct drm_device *dev,
552 			     struct amdgpu_framebuffer *rfb,
553 			     const struct drm_mode_fb_cmd2 *mode_cmd,
554 			     struct drm_gem_object *obj);
555 
556 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
557 
558 void amdgpu_enc_destroy(struct drm_encoder *encoder);
559 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
560 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
561 					const struct drm_display_mode *mode,
562 					struct drm_display_mode *adjusted_mode);
563 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
564 			     struct drm_display_mode *adjusted_mode);
565 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
566 
567 /* fbdev layer */
568 int amdgpu_fbdev_init(struct amdgpu_device *adev);
569 void amdgpu_fbdev_fini(struct amdgpu_device *adev);
570 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
571 int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
572 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
573 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
574 
575 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
576 
577 
578 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
579 
580 /* amdgpu_display.c */
581 void amdgpu_print_display_setup(struct drm_device *dev);
582 int amdgpu_modeset_create_props(struct amdgpu_device *adev);
583 int amdgpu_crtc_set_config(struct drm_mode_set *set,
584 			   struct drm_modeset_acquire_ctx *ctx);
585 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
586 				 struct drm_framebuffer *fb,
587 				 struct drm_pending_vblank_event *event,
588 				 uint32_t page_flip_flags, uint32_t target,
589 				 struct drm_modeset_acquire_ctx *ctx);
590 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
591 
592 #endif
593