1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3d38ceaf9SAlex Deucher * VA Linux Systems Inc., Fremont, California. 4d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Original Authors: 25d38ceaf9SAlex Deucher * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26d38ceaf9SAlex Deucher * 27d38ceaf9SAlex Deucher * Kernel port Author: Dave Airlie 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher 30d38ceaf9SAlex Deucher #ifndef AMDGPU_MODE_H 31d38ceaf9SAlex Deucher #define AMDGPU_MODE_H 32d38ceaf9SAlex Deucher 33*da68386dSThomas Zimmermann #include <drm/display/drm_dp_helper.h> 34d38ceaf9SAlex Deucher #include <drm/drm_crtc.h> 35d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 369338203cSLaurent Pinchart #include <drm/drm_encoder.h> 37d38ceaf9SAlex Deucher #include <drm/drm_fixed.h> 38d38ceaf9SAlex Deucher #include <drm/drm_crtc_helper.h> 39b516a9efSDaniel Vetter #include <drm/drm_fb_helper.h> 40d38ceaf9SAlex Deucher #include <drm/drm_plane_helper.h> 41fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 42d38ceaf9SAlex Deucher #include <linux/i2c.h> 43d38ceaf9SAlex Deucher #include <linux/i2c-algo-bit.h> 4446ac3622SEmily Deng #include <linux/hrtimer.h> 4546ac3622SEmily Deng #include "amdgpu_irq.h" 46d38ceaf9SAlex Deucher 47*da68386dSThomas Zimmermann #include <drm/display/drm_dp_mst_helper.h> 484562236bSHarry Wentland #include "modules/inc/mod_freesync.h" 495d1c59c4SAurabindo Pillai #include "amdgpu_dm_irq_params.h" 504562236bSHarry Wentland 51d38ceaf9SAlex Deucher struct amdgpu_bo; 52d38ceaf9SAlex Deucher struct amdgpu_device; 53d38ceaf9SAlex Deucher struct amdgpu_encoder; 54d38ceaf9SAlex Deucher struct amdgpu_router; 55d38ceaf9SAlex Deucher struct amdgpu_hpd; 56d38ceaf9SAlex Deucher 57d38ceaf9SAlex Deucher #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 58d38ceaf9SAlex Deucher #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 59d38ceaf9SAlex Deucher #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 60d38ceaf9SAlex Deucher #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 61d38ceaf9SAlex Deucher 623d12beb3SNicholas Kazlauskas #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 630604b36cSAndrey Grodzovsky 64d38ceaf9SAlex Deucher #define AMDGPU_MAX_HPD_PINS 6 65d38ceaf9SAlex Deucher #define AMDGPU_MAX_CRTCS 6 66d4e13b0dSAlex Deucher #define AMDGPU_MAX_PLANES 6 6722384459SAlex Deucher #define AMDGPU_MAX_AFMT_BLOCKS 9 68d38ceaf9SAlex Deucher 69d38ceaf9SAlex Deucher enum amdgpu_rmx_type { 70d38ceaf9SAlex Deucher RMX_OFF, 71d38ceaf9SAlex Deucher RMX_FULL, 72d38ceaf9SAlex Deucher RMX_CENTER, 73d38ceaf9SAlex Deucher RMX_ASPECT 74d38ceaf9SAlex Deucher }; 75d38ceaf9SAlex Deucher 76d38ceaf9SAlex Deucher enum amdgpu_underscan_type { 77d38ceaf9SAlex Deucher UNDERSCAN_OFF, 78d38ceaf9SAlex Deucher UNDERSCAN_ON, 79d38ceaf9SAlex Deucher UNDERSCAN_AUTO, 80d38ceaf9SAlex Deucher }; 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 83d38ceaf9SAlex Deucher #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 84d38ceaf9SAlex Deucher 85d38ceaf9SAlex Deucher enum amdgpu_hpd_id { 86d38ceaf9SAlex Deucher AMDGPU_HPD_1 = 0, 87d38ceaf9SAlex Deucher AMDGPU_HPD_2, 88d38ceaf9SAlex Deucher AMDGPU_HPD_3, 89d38ceaf9SAlex Deucher AMDGPU_HPD_4, 90d38ceaf9SAlex Deucher AMDGPU_HPD_5, 91d38ceaf9SAlex Deucher AMDGPU_HPD_6, 92d38ceaf9SAlex Deucher AMDGPU_HPD_NONE = 0xff, 93d38ceaf9SAlex Deucher }; 94d38ceaf9SAlex Deucher 95d38ceaf9SAlex Deucher enum amdgpu_crtc_irq { 96d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK1 = 0, 97d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK2, 98d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK3, 99d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK4, 100d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK5, 101d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK6, 102d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE1, 103d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE2, 104d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE3, 105d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE4, 106d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE5, 107d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE6, 108d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_NONE = 0xff 109d38ceaf9SAlex Deucher }; 110d38ceaf9SAlex Deucher 111d38ceaf9SAlex Deucher enum amdgpu_pageflip_irq { 112d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D1 = 0, 113d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D2, 114d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D3, 115d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D4, 116d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D5, 117d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D6, 118d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 119d38ceaf9SAlex Deucher }; 120d38ceaf9SAlex Deucher 121d38ceaf9SAlex Deucher enum amdgpu_flip_status { 122d38ceaf9SAlex Deucher AMDGPU_FLIP_NONE, 123d38ceaf9SAlex Deucher AMDGPU_FLIP_PENDING, 124d38ceaf9SAlex Deucher AMDGPU_FLIP_SUBMITTED 125d38ceaf9SAlex Deucher }; 126d38ceaf9SAlex Deucher 127d38ceaf9SAlex Deucher #define AMDGPU_MAX_I2C_BUS 16 128d38ceaf9SAlex Deucher 129d38ceaf9SAlex Deucher /* amdgpu gpio-based i2c 130d38ceaf9SAlex Deucher * 1. "mask" reg and bits 131d38ceaf9SAlex Deucher * grabs the gpio pins for software use 132d38ceaf9SAlex Deucher * 0=not held 1=held 133d38ceaf9SAlex Deucher * 2. "a" reg and bits 134d38ceaf9SAlex Deucher * output pin value 135d38ceaf9SAlex Deucher * 0=low 1=high 136d38ceaf9SAlex Deucher * 3. "en" reg and bits 137d38ceaf9SAlex Deucher * sets the pin direction 138d38ceaf9SAlex Deucher * 0=input 1=output 139d38ceaf9SAlex Deucher * 4. "y" reg and bits 140d38ceaf9SAlex Deucher * input pin value 141d38ceaf9SAlex Deucher * 0=low 1=high 142d38ceaf9SAlex Deucher */ 143d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec { 144d38ceaf9SAlex Deucher bool valid; 145d38ceaf9SAlex Deucher /* id used by atom */ 146d38ceaf9SAlex Deucher uint8_t i2c_id; 147d38ceaf9SAlex Deucher /* id used by atom */ 148d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd; 149d38ceaf9SAlex Deucher /* can be used with hw i2c engine */ 150d38ceaf9SAlex Deucher bool hw_capable; 151d38ceaf9SAlex Deucher /* uses multi-media i2c engine */ 152d38ceaf9SAlex Deucher bool mm_i2c; 153d38ceaf9SAlex Deucher /* regs and bits */ 154d38ceaf9SAlex Deucher uint32_t mask_clk_reg; 155d38ceaf9SAlex Deucher uint32_t mask_data_reg; 156d38ceaf9SAlex Deucher uint32_t a_clk_reg; 157d38ceaf9SAlex Deucher uint32_t a_data_reg; 158d38ceaf9SAlex Deucher uint32_t en_clk_reg; 159d38ceaf9SAlex Deucher uint32_t en_data_reg; 160d38ceaf9SAlex Deucher uint32_t y_clk_reg; 161d38ceaf9SAlex Deucher uint32_t y_data_reg; 162d38ceaf9SAlex Deucher uint32_t mask_clk_mask; 163d38ceaf9SAlex Deucher uint32_t mask_data_mask; 164d38ceaf9SAlex Deucher uint32_t a_clk_mask; 165d38ceaf9SAlex Deucher uint32_t a_data_mask; 166d38ceaf9SAlex Deucher uint32_t en_clk_mask; 167d38ceaf9SAlex Deucher uint32_t en_data_mask; 168d38ceaf9SAlex Deucher uint32_t y_clk_mask; 169d38ceaf9SAlex Deucher uint32_t y_data_mask; 170d38ceaf9SAlex Deucher }; 171d38ceaf9SAlex Deucher 172d38ceaf9SAlex Deucher #define AMDGPU_MAX_BIOS_CONNECTOR 16 173d38ceaf9SAlex Deucher 174d38ceaf9SAlex Deucher /* pll flags */ 175d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 176d38ceaf9SAlex Deucher #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 177d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 178d38ceaf9SAlex Deucher #define AMDGPU_PLL_LEGACY (1 << 3) 179d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 180d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 181d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 182d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 183d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 184d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 185d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 186d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 187d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 188d38ceaf9SAlex Deucher #define AMDGPU_PLL_IS_LCD (1 << 13) 189d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 190d38ceaf9SAlex Deucher 191d38ceaf9SAlex Deucher struct amdgpu_pll { 192d38ceaf9SAlex Deucher /* reference frequency */ 193d38ceaf9SAlex Deucher uint32_t reference_freq; 194d38ceaf9SAlex Deucher 195d38ceaf9SAlex Deucher /* fixed dividers */ 196d38ceaf9SAlex Deucher uint32_t reference_div; 197d38ceaf9SAlex Deucher uint32_t post_div; 198d38ceaf9SAlex Deucher 199d38ceaf9SAlex Deucher /* pll in/out limits */ 200d38ceaf9SAlex Deucher uint32_t pll_in_min; 201d38ceaf9SAlex Deucher uint32_t pll_in_max; 202d38ceaf9SAlex Deucher uint32_t pll_out_min; 203d38ceaf9SAlex Deucher uint32_t pll_out_max; 204d38ceaf9SAlex Deucher uint32_t lcd_pll_out_min; 205d38ceaf9SAlex Deucher uint32_t lcd_pll_out_max; 206d38ceaf9SAlex Deucher uint32_t best_vco; 207d38ceaf9SAlex Deucher 208d38ceaf9SAlex Deucher /* divider limits */ 209d38ceaf9SAlex Deucher uint32_t min_ref_div; 210d38ceaf9SAlex Deucher uint32_t max_ref_div; 211d38ceaf9SAlex Deucher uint32_t min_post_div; 212d38ceaf9SAlex Deucher uint32_t max_post_div; 213d38ceaf9SAlex Deucher uint32_t min_feedback_div; 214d38ceaf9SAlex Deucher uint32_t max_feedback_div; 215d38ceaf9SAlex Deucher uint32_t min_frac_feedback_div; 216d38ceaf9SAlex Deucher uint32_t max_frac_feedback_div; 217d38ceaf9SAlex Deucher 218d38ceaf9SAlex Deucher /* flags for the current clock */ 219d38ceaf9SAlex Deucher uint32_t flags; 220d38ceaf9SAlex Deucher 221d38ceaf9SAlex Deucher /* pll id */ 222d38ceaf9SAlex Deucher uint32_t id; 223d38ceaf9SAlex Deucher }; 224d38ceaf9SAlex Deucher 225d38ceaf9SAlex Deucher struct amdgpu_i2c_chan { 226d38ceaf9SAlex Deucher struct i2c_adapter adapter; 227d38ceaf9SAlex Deucher struct drm_device *dev; 228d38ceaf9SAlex Deucher struct i2c_algo_bit_data bit; 229d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec rec; 230d38ceaf9SAlex Deucher struct drm_dp_aux aux; 231d38ceaf9SAlex Deucher bool has_aux; 232d38ceaf9SAlex Deucher struct mutex mutex; 233d38ceaf9SAlex Deucher }; 234d38ceaf9SAlex Deucher 235d38ceaf9SAlex Deucher struct amdgpu_afmt { 236d38ceaf9SAlex Deucher bool enabled; 237d38ceaf9SAlex Deucher int offset; 238d38ceaf9SAlex Deucher bool last_buffer_filled_status; 239d38ceaf9SAlex Deucher int id; 240d38ceaf9SAlex Deucher struct amdgpu_audio_pin *pin; 241d38ceaf9SAlex Deucher }; 242d38ceaf9SAlex Deucher 243d38ceaf9SAlex Deucher /* 244d38ceaf9SAlex Deucher * Audio 245d38ceaf9SAlex Deucher */ 246d38ceaf9SAlex Deucher struct amdgpu_audio_pin { 247d38ceaf9SAlex Deucher int channels; 248d38ceaf9SAlex Deucher int rate; 249d38ceaf9SAlex Deucher int bits_per_sample; 250d38ceaf9SAlex Deucher u8 status_bits; 251d38ceaf9SAlex Deucher u8 category_code; 252d38ceaf9SAlex Deucher u32 offset; 253d38ceaf9SAlex Deucher bool connected; 254d38ceaf9SAlex Deucher u32 id; 255d38ceaf9SAlex Deucher }; 256d38ceaf9SAlex Deucher 257d38ceaf9SAlex Deucher struct amdgpu_audio { 258d38ceaf9SAlex Deucher bool enabled; 259d38ceaf9SAlex Deucher struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 260d38ceaf9SAlex Deucher int num_pins; 261d38ceaf9SAlex Deucher }; 262d38ceaf9SAlex Deucher 263d38ceaf9SAlex Deucher struct amdgpu_display_funcs { 264d38ceaf9SAlex Deucher /* display watermarks */ 265d38ceaf9SAlex Deucher void (*bandwidth_update)(struct amdgpu_device *adev); 266d38ceaf9SAlex Deucher /* get frame count */ 267d38ceaf9SAlex Deucher u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 268d38ceaf9SAlex Deucher /* set backlight level */ 269d38ceaf9SAlex Deucher void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 270d38ceaf9SAlex Deucher u8 level); 271d38ceaf9SAlex Deucher /* get backlight level */ 272d38ceaf9SAlex Deucher u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 273d38ceaf9SAlex Deucher /* hotplug detect */ 274d38ceaf9SAlex Deucher bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 275d38ceaf9SAlex Deucher void (*hpd_set_polarity)(struct amdgpu_device *adev, 276d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd); 277d38ceaf9SAlex Deucher u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 278d38ceaf9SAlex Deucher /* pageflipping */ 279d38ceaf9SAlex Deucher void (*page_flip)(struct amdgpu_device *adev, 280cb9e59d7SAlex Deucher int crtc_id, u64 crtc_base, bool async); 281d38ceaf9SAlex Deucher int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 282d38ceaf9SAlex Deucher u32 *vbl, u32 *position); 283d38ceaf9SAlex Deucher /* display topology setup */ 284d38ceaf9SAlex Deucher void (*add_encoder)(struct amdgpu_device *adev, 285d38ceaf9SAlex Deucher uint32_t encoder_enum, 286d38ceaf9SAlex Deucher uint32_t supported_device, 287d38ceaf9SAlex Deucher u16 caps); 288d38ceaf9SAlex Deucher void (*add_connector)(struct amdgpu_device *adev, 289d38ceaf9SAlex Deucher uint32_t connector_id, 290d38ceaf9SAlex Deucher uint32_t supported_device, 291d38ceaf9SAlex Deucher int connector_type, 292d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 293d38ceaf9SAlex Deucher uint16_t connector_object_id, 294d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 295d38ceaf9SAlex Deucher struct amdgpu_router *router); 2964562236bSHarry Wentland 2974562236bSHarry Wentland 2984562236bSHarry Wentland }; 2994562236bSHarry Wentland 3004562236bSHarry Wentland struct amdgpu_framebuffer { 3014562236bSHarry Wentland struct drm_framebuffer base; 302dd55d12cSAndrey Grodzovsky 3036eed95b0SBas Nieuwenhuizen uint64_t tiling_flags; 3046eed95b0SBas Nieuwenhuizen bool tmz_surface; 3056eed95b0SBas Nieuwenhuizen 306dd55d12cSAndrey Grodzovsky /* caching for later use */ 307dd55d12cSAndrey Grodzovsky uint64_t address; 3084562236bSHarry Wentland }; 3094562236bSHarry Wentland 310d38ceaf9SAlex Deucher struct amdgpu_mode_info { 311d38ceaf9SAlex Deucher struct atom_context *atom_context; 312d38ceaf9SAlex Deucher struct card_info *atom_card_info; 313d38ceaf9SAlex Deucher bool mode_config_initialized; 314f195038cSAlex Deucher struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 315f180b4bcSHarry Wentland struct drm_plane *planes[AMDGPU_MAX_PLANES]; 316f195038cSAlex Deucher struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 317d38ceaf9SAlex Deucher /* DVI-I properties */ 318d38ceaf9SAlex Deucher struct drm_property *coherent_mode_property; 319d38ceaf9SAlex Deucher /* DAC enable load detect */ 320d38ceaf9SAlex Deucher struct drm_property *load_detect_property; 321d38ceaf9SAlex Deucher /* underscan */ 322d38ceaf9SAlex Deucher struct drm_property *underscan_property; 323d38ceaf9SAlex Deucher struct drm_property *underscan_hborder_property; 324d38ceaf9SAlex Deucher struct drm_property *underscan_vborder_property; 325d38ceaf9SAlex Deucher /* audio */ 326d38ceaf9SAlex Deucher struct drm_property *audio_property; 327d38ceaf9SAlex Deucher /* FMT dithering */ 328d38ceaf9SAlex Deucher struct drm_property *dither_property; 329c1ee92f9SDavid Francis /* Adaptive Backlight Modulation (power feature) */ 330c1ee92f9SDavid Francis struct drm_property *abm_level_property; 331d38ceaf9SAlex Deucher /* hardcoded DFP edid from BIOS */ 332d38ceaf9SAlex Deucher struct edid *bios_hardcoded_edid; 333d38ceaf9SAlex Deucher int bios_hardcoded_edid_size; 334d38ceaf9SAlex Deucher 335d38ceaf9SAlex Deucher /* firmware flags */ 3365968c6a2SHawking Zhang u32 firmware_flags; 337d38ceaf9SAlex Deucher /* pointer to backlight encoder */ 338d38ceaf9SAlex Deucher struct amdgpu_encoder *bl_encoder; 339a59b3c80SAlex Deucher u8 bl_level; /* saved backlight level */ 340d38ceaf9SAlex Deucher struct amdgpu_audio audio; /* audio stuff */ 341d38ceaf9SAlex Deucher int num_crtc; /* number of crtcs */ 342d38ceaf9SAlex Deucher int num_hpd; /* number of hpd pins */ 343d38ceaf9SAlex Deucher int num_dig; /* number of dig blocks */ 344a7f520bfSAlex Deucher bool gpu_vm_support; /* supports display from GTT */ 345d38ceaf9SAlex Deucher int disp_priority; 346d38ceaf9SAlex Deucher const struct amdgpu_display_funcs *funcs; 347e04a6123SDave Airlie const enum drm_plane_type *plane_type; 348d38ceaf9SAlex Deucher }; 349d38ceaf9SAlex Deucher 350d38ceaf9SAlex Deucher #define AMDGPU_MAX_BL_LEVEL 0xFF 351d38ceaf9SAlex Deucher 352d38ceaf9SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 353d38ceaf9SAlex Deucher 354d38ceaf9SAlex Deucher struct amdgpu_backlight_privdata { 355d38ceaf9SAlex Deucher struct amdgpu_encoder *encoder; 356d38ceaf9SAlex Deucher uint8_t negative; 357d38ceaf9SAlex Deucher }; 358d38ceaf9SAlex Deucher 359d38ceaf9SAlex Deucher #endif 360d38ceaf9SAlex Deucher 361d38ceaf9SAlex Deucher struct amdgpu_atom_ss { 362d38ceaf9SAlex Deucher uint16_t percentage; 363d38ceaf9SAlex Deucher uint16_t percentage_divider; 364d38ceaf9SAlex Deucher uint8_t type; 365d38ceaf9SAlex Deucher uint16_t step; 366d38ceaf9SAlex Deucher uint8_t delay; 367d38ceaf9SAlex Deucher uint8_t range; 368d38ceaf9SAlex Deucher uint8_t refdiv; 369d38ceaf9SAlex Deucher /* asic_ss */ 370d38ceaf9SAlex Deucher uint16_t rate; 371d38ceaf9SAlex Deucher uint16_t amount; 372d38ceaf9SAlex Deucher }; 373d38ceaf9SAlex Deucher 374d38ceaf9SAlex Deucher struct amdgpu_crtc { 375d38ceaf9SAlex Deucher struct drm_crtc base; 376d38ceaf9SAlex Deucher int crtc_id; 377d38ceaf9SAlex Deucher bool enabled; 378d38ceaf9SAlex Deucher bool can_tile; 379d38ceaf9SAlex Deucher uint32_t crtc_offset; 380d38ceaf9SAlex Deucher struct drm_gem_object *cursor_bo; 381d38ceaf9SAlex Deucher uint64_t cursor_addr; 38229275a9bSAlex Deucher int cursor_x; 38329275a9bSAlex Deucher int cursor_y; 38429275a9bSAlex Deucher int cursor_hot_x; 38529275a9bSAlex Deucher int cursor_hot_y; 386d38ceaf9SAlex Deucher int cursor_width; 387d38ceaf9SAlex Deucher int cursor_height; 388d38ceaf9SAlex Deucher int max_cursor_width; 389d38ceaf9SAlex Deucher int max_cursor_height; 390d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 391d38ceaf9SAlex Deucher u8 h_border; 392d38ceaf9SAlex Deucher u8 v_border; 393d38ceaf9SAlex Deucher fixed20_12 vsc; 394d38ceaf9SAlex Deucher fixed20_12 hsc; 395d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 396d38ceaf9SAlex Deucher u32 pll_id; 397d38ceaf9SAlex Deucher /* page flipping */ 398d38ceaf9SAlex Deucher struct amdgpu_flip_work *pflip_works; 399d38ceaf9SAlex Deucher enum amdgpu_flip_status pflip_status; 400d38ceaf9SAlex Deucher int deferred_flip_completion; 4015d1c59c4SAurabindo Pillai /* parameters access from DM IRQ handler */ 4025d1c59c4SAurabindo Pillai struct dm_irq_params dm_irq_params; 403d38ceaf9SAlex Deucher /* pll sharing */ 404d38ceaf9SAlex Deucher struct amdgpu_atom_ss ss; 405d38ceaf9SAlex Deucher bool ss_enabled; 406d38ceaf9SAlex Deucher u32 adjusted_clock; 407d38ceaf9SAlex Deucher int bpc; 408d38ceaf9SAlex Deucher u32 pll_reference_div; 409d38ceaf9SAlex Deucher u32 pll_post_div; 410d38ceaf9SAlex Deucher u32 pll_flags; 411d38ceaf9SAlex Deucher struct drm_encoder *encoder; 412d38ceaf9SAlex Deucher struct drm_connector *connector; 413d38ceaf9SAlex Deucher /* for dpm */ 414d38ceaf9SAlex Deucher u32 line_time; 415d38ceaf9SAlex Deucher u32 wm_low; 416d38ceaf9SAlex Deucher u32 wm_high; 4178e36f9d3SAlex Deucher u32 lb_vblank_lead_lines; 418d38ceaf9SAlex Deucher struct drm_display_mode hw_mode; 4190f66356dSEmily Deng /* for virtual dce */ 4200f66356dSEmily Deng struct hrtimer vblank_timer; 4210f66356dSEmily Deng enum amdgpu_interrupt_state vsync_timer_enabled; 4224562236bSHarry Wentland 4234562236bSHarry Wentland int otg_inst; 424dd55d12cSAndrey Grodzovsky struct drm_pending_vblank_event *event; 425d38ceaf9SAlex Deucher }; 426d38ceaf9SAlex Deucher 427d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig { 428d38ceaf9SAlex Deucher bool linkb; 429d38ceaf9SAlex Deucher /* atom dig */ 430d38ceaf9SAlex Deucher bool coherent_mode; 431d38ceaf9SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 432d38ceaf9SAlex Deucher /* atom lvds/edp */ 433d38ceaf9SAlex Deucher uint32_t lcd_misc; 434d38ceaf9SAlex Deucher uint16_t panel_pwr_delay; 435d38ceaf9SAlex Deucher uint32_t lcd_ss_id; 436d38ceaf9SAlex Deucher /* panel mode */ 437d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 438d38ceaf9SAlex Deucher struct backlight_device *bl_dev; 439d38ceaf9SAlex Deucher int dpms_mode; 440d38ceaf9SAlex Deucher uint8_t backlight_level; 441d38ceaf9SAlex Deucher int panel_mode; 442d38ceaf9SAlex Deucher struct amdgpu_afmt *afmt; 443d38ceaf9SAlex Deucher }; 444d38ceaf9SAlex Deucher 445d38ceaf9SAlex Deucher struct amdgpu_encoder { 446d38ceaf9SAlex Deucher struct drm_encoder base; 447d38ceaf9SAlex Deucher uint32_t encoder_enum; 448d38ceaf9SAlex Deucher uint32_t encoder_id; 449d38ceaf9SAlex Deucher uint32_t devices; 450d38ceaf9SAlex Deucher uint32_t active_device; 451d38ceaf9SAlex Deucher uint32_t flags; 452d38ceaf9SAlex Deucher uint32_t pixel_clock; 453d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 454d38ceaf9SAlex Deucher enum amdgpu_underscan_type underscan_type; 455d38ceaf9SAlex Deucher uint32_t underscan_hborder; 456d38ceaf9SAlex Deucher uint32_t underscan_vborder; 457d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 458d38ceaf9SAlex Deucher void *enc_priv; 459d38ceaf9SAlex Deucher int audio_polling_active; 460d38ceaf9SAlex Deucher bool is_ext_encoder; 461d38ceaf9SAlex Deucher u16 caps; 462d38ceaf9SAlex Deucher }; 463d38ceaf9SAlex Deucher 464d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig { 465d38ceaf9SAlex Deucher /* displayport */ 466d38ceaf9SAlex Deucher u8 dpcd[DP_RECEIVER_CAP_SIZE]; 46765bf2cf9SOleg Vasilev u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 468d38ceaf9SAlex Deucher u8 dp_sink_type; 469d38ceaf9SAlex Deucher int dp_clock; 470d38ceaf9SAlex Deucher int dp_lane_count; 471d38ceaf9SAlex Deucher bool edp_on; 472d38ceaf9SAlex Deucher }; 473d38ceaf9SAlex Deucher 474d38ceaf9SAlex Deucher struct amdgpu_gpio_rec { 475d38ceaf9SAlex Deucher bool valid; 476d38ceaf9SAlex Deucher u8 id; 477d38ceaf9SAlex Deucher u32 reg; 478d38ceaf9SAlex Deucher u32 mask; 479d38ceaf9SAlex Deucher u32 shift; 480d38ceaf9SAlex Deucher }; 481d38ceaf9SAlex Deucher 482d38ceaf9SAlex Deucher struct amdgpu_hpd { 483d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd; 484d38ceaf9SAlex Deucher u8 plugged_state; 485d38ceaf9SAlex Deucher struct amdgpu_gpio_rec gpio; 486d38ceaf9SAlex Deucher }; 487d38ceaf9SAlex Deucher 488d38ceaf9SAlex Deucher struct amdgpu_router { 489d38ceaf9SAlex Deucher u32 router_id; 490d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec i2c_info; 491d38ceaf9SAlex Deucher u8 i2c_addr; 492d38ceaf9SAlex Deucher /* i2c mux */ 493d38ceaf9SAlex Deucher bool ddc_valid; 494d38ceaf9SAlex Deucher u8 ddc_mux_type; 495d38ceaf9SAlex Deucher u8 ddc_mux_control_pin; 496d38ceaf9SAlex Deucher u8 ddc_mux_state; 497d38ceaf9SAlex Deucher /* clock/data mux */ 498d38ceaf9SAlex Deucher bool cd_valid; 499d38ceaf9SAlex Deucher u8 cd_mux_type; 500d38ceaf9SAlex Deucher u8 cd_mux_control_pin; 501d38ceaf9SAlex Deucher u8 cd_mux_state; 502d38ceaf9SAlex Deucher }; 503d38ceaf9SAlex Deucher 504d38ceaf9SAlex Deucher enum amdgpu_connector_audio { 505d38ceaf9SAlex Deucher AMDGPU_AUDIO_DISABLE = 0, 506d38ceaf9SAlex Deucher AMDGPU_AUDIO_ENABLE = 1, 507d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO = 2 508d38ceaf9SAlex Deucher }; 509d38ceaf9SAlex Deucher 510d38ceaf9SAlex Deucher enum amdgpu_connector_dither { 511d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE = 0, 512d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_ENABLE = 1, 513d38ceaf9SAlex Deucher }; 514d38ceaf9SAlex Deucher 5154562236bSHarry Wentland struct amdgpu_dm_dp_aux { 5164562236bSHarry Wentland struct drm_dp_aux aux; 51746df790cSAndrey Grodzovsky struct ddc_service *ddc_service; 5184562236bSHarry Wentland }; 5194562236bSHarry Wentland 5204562236bSHarry Wentland struct amdgpu_i2c_adapter { 5214562236bSHarry Wentland struct i2c_adapter base; 52246df790cSAndrey Grodzovsky 52346df790cSAndrey Grodzovsky struct ddc_service *ddc_service; 5244562236bSHarry Wentland }; 5254562236bSHarry Wentland 5264562236bSHarry Wentland #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 5274562236bSHarry Wentland 528d38ceaf9SAlex Deucher struct amdgpu_connector { 529d38ceaf9SAlex Deucher struct drm_connector base; 530d38ceaf9SAlex Deucher uint32_t connector_id; 531d38ceaf9SAlex Deucher uint32_t devices; 532d38ceaf9SAlex Deucher struct amdgpu_i2c_chan *ddc_bus; 533d38ceaf9SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 534d38ceaf9SAlex Deucher bool shared_ddc; 535d38ceaf9SAlex Deucher bool use_digital; 536d38ceaf9SAlex Deucher /* we need to mind the EDID between detect 537d38ceaf9SAlex Deucher and get modes due to analog/digital/tvencoder */ 538d38ceaf9SAlex Deucher struct edid *edid; 539d38ceaf9SAlex Deucher void *con_priv; 540d38ceaf9SAlex Deucher bool dac_load_detect; 541d38ceaf9SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 542d38ceaf9SAlex Deucher uint16_t connector_object_id; 543d38ceaf9SAlex Deucher struct amdgpu_hpd hpd; 544d38ceaf9SAlex Deucher struct amdgpu_router router; 545d38ceaf9SAlex Deucher struct amdgpu_i2c_chan *router_bus; 546d38ceaf9SAlex Deucher enum amdgpu_connector_audio audio; 547d38ceaf9SAlex Deucher enum amdgpu_connector_dither dither; 548d38ceaf9SAlex Deucher unsigned pixelclock_for_modeset; 549d38ceaf9SAlex Deucher }; 550d38ceaf9SAlex Deucher 5514562236bSHarry Wentland /* TODO: start to use this struct and remove same field from base one */ 5524562236bSHarry Wentland struct amdgpu_mst_connector { 5534562236bSHarry Wentland struct amdgpu_connector base; 5544562236bSHarry Wentland 5554562236bSHarry Wentland struct drm_dp_mst_topology_mgr mst_mgr; 5564562236bSHarry Wentland struct amdgpu_dm_dp_aux dm_dp_aux; 5574562236bSHarry Wentland struct drm_dp_mst_port *port; 5584562236bSHarry Wentland struct amdgpu_connector *mst_port; 5594562236bSHarry Wentland bool is_mst_connector; 5604562236bSHarry Wentland struct amdgpu_encoder *mst_encoder; 561d38ceaf9SAlex Deucher }; 562d38ceaf9SAlex Deucher 563d38ceaf9SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 564d38ceaf9SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 565d38ceaf9SAlex Deucher 566aa8e286aSSamuel Li /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 5671bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_VALID (1 << 0) 5681bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 5691bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 5708e36f9d3SAlex Deucher #define USE_REAL_VBLANKSTART (1 << 30) 5718e36f9d3SAlex Deucher #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 5728e36f9d3SAlex Deucher 573d38ceaf9SAlex Deucher void amdgpu_link_encoder_connector(struct drm_device *dev); 574d38ceaf9SAlex Deucher 575d38ceaf9SAlex Deucher struct drm_connector * 576d38ceaf9SAlex Deucher amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 577d38ceaf9SAlex Deucher struct drm_connector * 578d38ceaf9SAlex Deucher amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 579d38ceaf9SAlex Deucher bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 580d38ceaf9SAlex Deucher u32 pixel_clock); 581d38ceaf9SAlex Deucher 582d38ceaf9SAlex Deucher u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 583d38ceaf9SAlex Deucher struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 584d38ceaf9SAlex Deucher 585e0b5b5ecSSamuel Li bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 586e0b5b5ecSSamuel Li bool use_aux); 587d38ceaf9SAlex Deucher 588d38ceaf9SAlex Deucher void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 589d38ceaf9SAlex Deucher 590aa8e286aSSamuel Li int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 591aa8e286aSSamuel Li unsigned int pipe, unsigned int flags, int *vpos, 592aa8e286aSSamuel Li int *hpos, ktime_t *stime, ktime_t *etime, 5933bb403bfSVille Syrjälä const struct drm_display_mode *mode); 594d38ceaf9SAlex Deucher 595f258907fSMark Yacoub int amdgpu_display_gem_fb_init(struct drm_device *dev, 596f258907fSMark Yacoub struct amdgpu_framebuffer *rfb, 597f258907fSMark Yacoub const struct drm_mode_fb_cmd2 *mode_cmd, 598f258907fSMark Yacoub struct drm_gem_object *obj); 599f258907fSMark Yacoub int amdgpu_display_gem_fb_verify_and_init( 600f258907fSMark Yacoub struct drm_device *dev, struct amdgpu_framebuffer *rfb, 601f258907fSMark Yacoub struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd, 602f258907fSMark Yacoub struct drm_gem_object *obj); 6039da3f2d9SSamuel Li int amdgpu_display_framebuffer_init(struct drm_device *dev, 604d38ceaf9SAlex Deucher struct amdgpu_framebuffer *rfb, 6051eb83451SVille Syrjälä const struct drm_mode_fb_cmd2 *mode_cmd, 606d38ceaf9SAlex Deucher struct drm_gem_object *obj); 607d38ceaf9SAlex Deucher 608d38ceaf9SAlex Deucher int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 609d38ceaf9SAlex Deucher 610d38ceaf9SAlex Deucher void amdgpu_enc_destroy(struct drm_encoder *encoder); 611d38ceaf9SAlex Deucher void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 6120c16443aSSamuel Li bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 613d38ceaf9SAlex Deucher const struct drm_display_mode *mode, 614d38ceaf9SAlex Deucher struct drm_display_mode *adjusted_mode); 615d38ceaf9SAlex Deucher void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 616d38ceaf9SAlex Deucher struct drm_display_mode *adjusted_mode); 617734dd01dSSamuel Li int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 618d38ceaf9SAlex Deucher 619ea702333SThomas Zimmermann bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 620ea702333SThomas Zimmermann bool in_vblank_irq, int *vpos, 621ea702333SThomas Zimmermann int *hpos, ktime_t *stime, ktime_t *etime, 622ea702333SThomas Zimmermann const struct drm_display_mode *mode); 623ea702333SThomas Zimmermann 624d38ceaf9SAlex Deucher /* amdgpu_display.c */ 62550af9193SSamuel Li void amdgpu_display_print_display_setup(struct drm_device *dev); 6263dc9b1ceSSamuel Li int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 627775a8364SSamuel Li int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 628a4eff9aaSDaniel Vetter struct drm_modeset_acquire_ctx *ctx); 6290cd11932SSamuel Li int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 630d38ceaf9SAlex Deucher struct drm_framebuffer *fb, 631d38ceaf9SAlex Deucher struct drm_pending_vblank_event *event, 63241292b1fSDaniel Vetter uint32_t page_flip_flags, uint32_t target, 63341292b1fSDaniel Vetter struct drm_modeset_acquire_ctx *ctx); 634d38ceaf9SAlex Deucher extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 635d38ceaf9SAlex Deucher 636d38ceaf9SAlex Deucher #endif 637