1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3d38ceaf9SAlex Deucher * VA Linux Systems Inc., Fremont, California. 4d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Original Authors: 25d38ceaf9SAlex Deucher * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26d38ceaf9SAlex Deucher * 27d38ceaf9SAlex Deucher * Kernel port Author: Dave Airlie 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher 30d38ceaf9SAlex Deucher #ifndef AMDGPU_MODE_H 31d38ceaf9SAlex Deucher #define AMDGPU_MODE_H 32d38ceaf9SAlex Deucher 33d38ceaf9SAlex Deucher #include <drm/drm_crtc.h> 34d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 35d38ceaf9SAlex Deucher #include <drm/drm_dp_helper.h> 36d38ceaf9SAlex Deucher #include <drm/drm_fixed.h> 37d38ceaf9SAlex Deucher #include <drm/drm_crtc_helper.h> 38b516a9efSDaniel Vetter #include <drm/drm_fb_helper.h> 39d38ceaf9SAlex Deucher #include <drm/drm_plane_helper.h> 40d38ceaf9SAlex Deucher #include <linux/i2c.h> 41d38ceaf9SAlex Deucher #include <linux/i2c-algo-bit.h> 42d38ceaf9SAlex Deucher 43d38ceaf9SAlex Deucher struct amdgpu_bo; 44d38ceaf9SAlex Deucher struct amdgpu_device; 45d38ceaf9SAlex Deucher struct amdgpu_encoder; 46d38ceaf9SAlex Deucher struct amdgpu_router; 47d38ceaf9SAlex Deucher struct amdgpu_hpd; 48d38ceaf9SAlex Deucher 49d38ceaf9SAlex Deucher #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 50d38ceaf9SAlex Deucher #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 51d38ceaf9SAlex Deucher #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 52d38ceaf9SAlex Deucher #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 53d38ceaf9SAlex Deucher 54d38ceaf9SAlex Deucher #define AMDGPU_MAX_HPD_PINS 6 55d38ceaf9SAlex Deucher #define AMDGPU_MAX_CRTCS 6 5622384459SAlex Deucher #define AMDGPU_MAX_AFMT_BLOCKS 9 57d38ceaf9SAlex Deucher 58d38ceaf9SAlex Deucher enum amdgpu_rmx_type { 59d38ceaf9SAlex Deucher RMX_OFF, 60d38ceaf9SAlex Deucher RMX_FULL, 61d38ceaf9SAlex Deucher RMX_CENTER, 62d38ceaf9SAlex Deucher RMX_ASPECT 63d38ceaf9SAlex Deucher }; 64d38ceaf9SAlex Deucher 65d38ceaf9SAlex Deucher enum amdgpu_underscan_type { 66d38ceaf9SAlex Deucher UNDERSCAN_OFF, 67d38ceaf9SAlex Deucher UNDERSCAN_ON, 68d38ceaf9SAlex Deucher UNDERSCAN_AUTO, 69d38ceaf9SAlex Deucher }; 70d38ceaf9SAlex Deucher 71d38ceaf9SAlex Deucher #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 72d38ceaf9SAlex Deucher #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 73d38ceaf9SAlex Deucher 74d38ceaf9SAlex Deucher enum amdgpu_hpd_id { 75d38ceaf9SAlex Deucher AMDGPU_HPD_1 = 0, 76d38ceaf9SAlex Deucher AMDGPU_HPD_2, 77d38ceaf9SAlex Deucher AMDGPU_HPD_3, 78d38ceaf9SAlex Deucher AMDGPU_HPD_4, 79d38ceaf9SAlex Deucher AMDGPU_HPD_5, 80d38ceaf9SAlex Deucher AMDGPU_HPD_6, 81d38ceaf9SAlex Deucher AMDGPU_HPD_LAST, 82d38ceaf9SAlex Deucher AMDGPU_HPD_NONE = 0xff, 83d38ceaf9SAlex Deucher }; 84d38ceaf9SAlex Deucher 85d38ceaf9SAlex Deucher enum amdgpu_crtc_irq { 86d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK1 = 0, 87d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK2, 88d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK3, 89d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK4, 90d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK5, 91d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK6, 92d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE1, 93d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE2, 94d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE3, 95d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE4, 96d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE5, 97d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE6, 98d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_LAST, 99d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_NONE = 0xff 100d38ceaf9SAlex Deucher }; 101d38ceaf9SAlex Deucher 102d38ceaf9SAlex Deucher enum amdgpu_pageflip_irq { 103d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D1 = 0, 104d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D2, 105d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D3, 106d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D4, 107d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D5, 108d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D6, 109d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_LAST, 110d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 111d38ceaf9SAlex Deucher }; 112d38ceaf9SAlex Deucher 113d38ceaf9SAlex Deucher enum amdgpu_flip_status { 114d38ceaf9SAlex Deucher AMDGPU_FLIP_NONE, 115d38ceaf9SAlex Deucher AMDGPU_FLIP_PENDING, 116d38ceaf9SAlex Deucher AMDGPU_FLIP_SUBMITTED 117d38ceaf9SAlex Deucher }; 118d38ceaf9SAlex Deucher 119d38ceaf9SAlex Deucher #define AMDGPU_MAX_I2C_BUS 16 120d38ceaf9SAlex Deucher 121d38ceaf9SAlex Deucher /* amdgpu gpio-based i2c 122d38ceaf9SAlex Deucher * 1. "mask" reg and bits 123d38ceaf9SAlex Deucher * grabs the gpio pins for software use 124d38ceaf9SAlex Deucher * 0=not held 1=held 125d38ceaf9SAlex Deucher * 2. "a" reg and bits 126d38ceaf9SAlex Deucher * output pin value 127d38ceaf9SAlex Deucher * 0=low 1=high 128d38ceaf9SAlex Deucher * 3. "en" reg and bits 129d38ceaf9SAlex Deucher * sets the pin direction 130d38ceaf9SAlex Deucher * 0=input 1=output 131d38ceaf9SAlex Deucher * 4. "y" reg and bits 132d38ceaf9SAlex Deucher * input pin value 133d38ceaf9SAlex Deucher * 0=low 1=high 134d38ceaf9SAlex Deucher */ 135d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec { 136d38ceaf9SAlex Deucher bool valid; 137d38ceaf9SAlex Deucher /* id used by atom */ 138d38ceaf9SAlex Deucher uint8_t i2c_id; 139d38ceaf9SAlex Deucher /* id used by atom */ 140d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd; 141d38ceaf9SAlex Deucher /* can be used with hw i2c engine */ 142d38ceaf9SAlex Deucher bool hw_capable; 143d38ceaf9SAlex Deucher /* uses multi-media i2c engine */ 144d38ceaf9SAlex Deucher bool mm_i2c; 145d38ceaf9SAlex Deucher /* regs and bits */ 146d38ceaf9SAlex Deucher uint32_t mask_clk_reg; 147d38ceaf9SAlex Deucher uint32_t mask_data_reg; 148d38ceaf9SAlex Deucher uint32_t a_clk_reg; 149d38ceaf9SAlex Deucher uint32_t a_data_reg; 150d38ceaf9SAlex Deucher uint32_t en_clk_reg; 151d38ceaf9SAlex Deucher uint32_t en_data_reg; 152d38ceaf9SAlex Deucher uint32_t y_clk_reg; 153d38ceaf9SAlex Deucher uint32_t y_data_reg; 154d38ceaf9SAlex Deucher uint32_t mask_clk_mask; 155d38ceaf9SAlex Deucher uint32_t mask_data_mask; 156d38ceaf9SAlex Deucher uint32_t a_clk_mask; 157d38ceaf9SAlex Deucher uint32_t a_data_mask; 158d38ceaf9SAlex Deucher uint32_t en_clk_mask; 159d38ceaf9SAlex Deucher uint32_t en_data_mask; 160d38ceaf9SAlex Deucher uint32_t y_clk_mask; 161d38ceaf9SAlex Deucher uint32_t y_data_mask; 162d38ceaf9SAlex Deucher }; 163d38ceaf9SAlex Deucher 164d38ceaf9SAlex Deucher #define AMDGPU_MAX_BIOS_CONNECTOR 16 165d38ceaf9SAlex Deucher 166d38ceaf9SAlex Deucher /* pll flags */ 167d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 168d38ceaf9SAlex Deucher #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 169d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 170d38ceaf9SAlex Deucher #define AMDGPU_PLL_LEGACY (1 << 3) 171d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 172d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 173d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 174d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 175d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 176d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 177d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 178d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 179d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 180d38ceaf9SAlex Deucher #define AMDGPU_PLL_IS_LCD (1 << 13) 181d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 182d38ceaf9SAlex Deucher 183d38ceaf9SAlex Deucher struct amdgpu_pll { 184d38ceaf9SAlex Deucher /* reference frequency */ 185d38ceaf9SAlex Deucher uint32_t reference_freq; 186d38ceaf9SAlex Deucher 187d38ceaf9SAlex Deucher /* fixed dividers */ 188d38ceaf9SAlex Deucher uint32_t reference_div; 189d38ceaf9SAlex Deucher uint32_t post_div; 190d38ceaf9SAlex Deucher 191d38ceaf9SAlex Deucher /* pll in/out limits */ 192d38ceaf9SAlex Deucher uint32_t pll_in_min; 193d38ceaf9SAlex Deucher uint32_t pll_in_max; 194d38ceaf9SAlex Deucher uint32_t pll_out_min; 195d38ceaf9SAlex Deucher uint32_t pll_out_max; 196d38ceaf9SAlex Deucher uint32_t lcd_pll_out_min; 197d38ceaf9SAlex Deucher uint32_t lcd_pll_out_max; 198d38ceaf9SAlex Deucher uint32_t best_vco; 199d38ceaf9SAlex Deucher 200d38ceaf9SAlex Deucher /* divider limits */ 201d38ceaf9SAlex Deucher uint32_t min_ref_div; 202d38ceaf9SAlex Deucher uint32_t max_ref_div; 203d38ceaf9SAlex Deucher uint32_t min_post_div; 204d38ceaf9SAlex Deucher uint32_t max_post_div; 205d38ceaf9SAlex Deucher uint32_t min_feedback_div; 206d38ceaf9SAlex Deucher uint32_t max_feedback_div; 207d38ceaf9SAlex Deucher uint32_t min_frac_feedback_div; 208d38ceaf9SAlex Deucher uint32_t max_frac_feedback_div; 209d38ceaf9SAlex Deucher 210d38ceaf9SAlex Deucher /* flags for the current clock */ 211d38ceaf9SAlex Deucher uint32_t flags; 212d38ceaf9SAlex Deucher 213d38ceaf9SAlex Deucher /* pll id */ 214d38ceaf9SAlex Deucher uint32_t id; 215d38ceaf9SAlex Deucher }; 216d38ceaf9SAlex Deucher 217d38ceaf9SAlex Deucher struct amdgpu_i2c_chan { 218d38ceaf9SAlex Deucher struct i2c_adapter adapter; 219d38ceaf9SAlex Deucher struct drm_device *dev; 220d38ceaf9SAlex Deucher struct i2c_algo_bit_data bit; 221d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec rec; 222d38ceaf9SAlex Deucher struct drm_dp_aux aux; 223d38ceaf9SAlex Deucher bool has_aux; 224d38ceaf9SAlex Deucher struct mutex mutex; 225d38ceaf9SAlex Deucher }; 226d38ceaf9SAlex Deucher 227d38ceaf9SAlex Deucher struct amdgpu_fbdev; 228d38ceaf9SAlex Deucher 229d38ceaf9SAlex Deucher struct amdgpu_afmt { 230d38ceaf9SAlex Deucher bool enabled; 231d38ceaf9SAlex Deucher int offset; 232d38ceaf9SAlex Deucher bool last_buffer_filled_status; 233d38ceaf9SAlex Deucher int id; 234d38ceaf9SAlex Deucher struct amdgpu_audio_pin *pin; 235d38ceaf9SAlex Deucher }; 236d38ceaf9SAlex Deucher 237d38ceaf9SAlex Deucher /* 238d38ceaf9SAlex Deucher * Audio 239d38ceaf9SAlex Deucher */ 240d38ceaf9SAlex Deucher struct amdgpu_audio_pin { 241d38ceaf9SAlex Deucher int channels; 242d38ceaf9SAlex Deucher int rate; 243d38ceaf9SAlex Deucher int bits_per_sample; 244d38ceaf9SAlex Deucher u8 status_bits; 245d38ceaf9SAlex Deucher u8 category_code; 246d38ceaf9SAlex Deucher u32 offset; 247d38ceaf9SAlex Deucher bool connected; 248d38ceaf9SAlex Deucher u32 id; 249d38ceaf9SAlex Deucher }; 250d38ceaf9SAlex Deucher 251d38ceaf9SAlex Deucher struct amdgpu_audio { 252d38ceaf9SAlex Deucher bool enabled; 253d38ceaf9SAlex Deucher struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 254d38ceaf9SAlex Deucher int num_pins; 255d38ceaf9SAlex Deucher }; 256d38ceaf9SAlex Deucher 257d38ceaf9SAlex Deucher struct amdgpu_mode_mc_save { 258d38ceaf9SAlex Deucher u32 vga_render_control; 259d38ceaf9SAlex Deucher u32 vga_hdp_control; 260d38ceaf9SAlex Deucher bool crtc_enabled[AMDGPU_MAX_CRTCS]; 261d38ceaf9SAlex Deucher }; 262d38ceaf9SAlex Deucher 263d38ceaf9SAlex Deucher struct amdgpu_display_funcs { 264d38ceaf9SAlex Deucher /* vga render */ 265d38ceaf9SAlex Deucher void (*set_vga_render_state)(struct amdgpu_device *adev, bool render); 266d38ceaf9SAlex Deucher /* display watermarks */ 267d38ceaf9SAlex Deucher void (*bandwidth_update)(struct amdgpu_device *adev); 268d38ceaf9SAlex Deucher /* get frame count */ 269d38ceaf9SAlex Deucher u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 270d38ceaf9SAlex Deucher /* wait for vblank */ 271d38ceaf9SAlex Deucher void (*vblank_wait)(struct amdgpu_device *adev, int crtc); 272d38ceaf9SAlex Deucher /* is dce hung */ 273d38ceaf9SAlex Deucher bool (*is_display_hung)(struct amdgpu_device *adev); 274d38ceaf9SAlex Deucher /* set backlight level */ 275d38ceaf9SAlex Deucher void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 276d38ceaf9SAlex Deucher u8 level); 277d38ceaf9SAlex Deucher /* get backlight level */ 278d38ceaf9SAlex Deucher u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 279d38ceaf9SAlex Deucher /* hotplug detect */ 280d38ceaf9SAlex Deucher bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 281d38ceaf9SAlex Deucher void (*hpd_set_polarity)(struct amdgpu_device *adev, 282d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd); 283d38ceaf9SAlex Deucher u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 284d38ceaf9SAlex Deucher /* pageflipping */ 285d38ceaf9SAlex Deucher void (*page_flip)(struct amdgpu_device *adev, 286cb9e59d7SAlex Deucher int crtc_id, u64 crtc_base, bool async); 287d38ceaf9SAlex Deucher int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 288d38ceaf9SAlex Deucher u32 *vbl, u32 *position); 289d38ceaf9SAlex Deucher /* display topology setup */ 290d38ceaf9SAlex Deucher void (*add_encoder)(struct amdgpu_device *adev, 291d38ceaf9SAlex Deucher uint32_t encoder_enum, 292d38ceaf9SAlex Deucher uint32_t supported_device, 293d38ceaf9SAlex Deucher u16 caps); 294d38ceaf9SAlex Deucher void (*add_connector)(struct amdgpu_device *adev, 295d38ceaf9SAlex Deucher uint32_t connector_id, 296d38ceaf9SAlex Deucher uint32_t supported_device, 297d38ceaf9SAlex Deucher int connector_type, 298d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 299d38ceaf9SAlex Deucher uint16_t connector_object_id, 300d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 301d38ceaf9SAlex Deucher struct amdgpu_router *router); 302d38ceaf9SAlex Deucher void (*stop_mc_access)(struct amdgpu_device *adev, 303d38ceaf9SAlex Deucher struct amdgpu_mode_mc_save *save); 304d38ceaf9SAlex Deucher void (*resume_mc_access)(struct amdgpu_device *adev, 305d38ceaf9SAlex Deucher struct amdgpu_mode_mc_save *save); 306d38ceaf9SAlex Deucher }; 307d38ceaf9SAlex Deucher 308d38ceaf9SAlex Deucher struct amdgpu_mode_info { 309d38ceaf9SAlex Deucher struct atom_context *atom_context; 310d38ceaf9SAlex Deucher struct card_info *atom_card_info; 311d38ceaf9SAlex Deucher bool mode_config_initialized; 312f195038cSAlex Deucher struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 313f195038cSAlex Deucher struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 314d38ceaf9SAlex Deucher /* DVI-I properties */ 315d38ceaf9SAlex Deucher struct drm_property *coherent_mode_property; 316d38ceaf9SAlex Deucher /* DAC enable load detect */ 317d38ceaf9SAlex Deucher struct drm_property *load_detect_property; 318d38ceaf9SAlex Deucher /* underscan */ 319d38ceaf9SAlex Deucher struct drm_property *underscan_property; 320d38ceaf9SAlex Deucher struct drm_property *underscan_hborder_property; 321d38ceaf9SAlex Deucher struct drm_property *underscan_vborder_property; 322d38ceaf9SAlex Deucher /* audio */ 323d38ceaf9SAlex Deucher struct drm_property *audio_property; 324d38ceaf9SAlex Deucher /* FMT dithering */ 325d38ceaf9SAlex Deucher struct drm_property *dither_property; 326d38ceaf9SAlex Deucher /* hardcoded DFP edid from BIOS */ 327d38ceaf9SAlex Deucher struct edid *bios_hardcoded_edid; 328d38ceaf9SAlex Deucher int bios_hardcoded_edid_size; 329d38ceaf9SAlex Deucher 330d38ceaf9SAlex Deucher /* pointer to fbdev info structure */ 331d38ceaf9SAlex Deucher struct amdgpu_fbdev *rfbdev; 332d38ceaf9SAlex Deucher /* firmware flags */ 333d38ceaf9SAlex Deucher u16 firmware_flags; 334d38ceaf9SAlex Deucher /* pointer to backlight encoder */ 335d38ceaf9SAlex Deucher struct amdgpu_encoder *bl_encoder; 336d38ceaf9SAlex Deucher struct amdgpu_audio audio; /* audio stuff */ 337d38ceaf9SAlex Deucher int num_crtc; /* number of crtcs */ 338d38ceaf9SAlex Deucher int num_hpd; /* number of hpd pins */ 339d38ceaf9SAlex Deucher int num_dig; /* number of dig blocks */ 340d38ceaf9SAlex Deucher int disp_priority; 341d38ceaf9SAlex Deucher const struct amdgpu_display_funcs *funcs; 342d38ceaf9SAlex Deucher }; 343d38ceaf9SAlex Deucher 344d38ceaf9SAlex Deucher #define AMDGPU_MAX_BL_LEVEL 0xFF 345d38ceaf9SAlex Deucher 346d38ceaf9SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 347d38ceaf9SAlex Deucher 348d38ceaf9SAlex Deucher struct amdgpu_backlight_privdata { 349d38ceaf9SAlex Deucher struct amdgpu_encoder *encoder; 350d38ceaf9SAlex Deucher uint8_t negative; 351d38ceaf9SAlex Deucher }; 352d38ceaf9SAlex Deucher 353d38ceaf9SAlex Deucher #endif 354d38ceaf9SAlex Deucher 355d38ceaf9SAlex Deucher struct amdgpu_atom_ss { 356d38ceaf9SAlex Deucher uint16_t percentage; 357d38ceaf9SAlex Deucher uint16_t percentage_divider; 358d38ceaf9SAlex Deucher uint8_t type; 359d38ceaf9SAlex Deucher uint16_t step; 360d38ceaf9SAlex Deucher uint8_t delay; 361d38ceaf9SAlex Deucher uint8_t range; 362d38ceaf9SAlex Deucher uint8_t refdiv; 363d38ceaf9SAlex Deucher /* asic_ss */ 364d38ceaf9SAlex Deucher uint16_t rate; 365d38ceaf9SAlex Deucher uint16_t amount; 366d38ceaf9SAlex Deucher }; 367d38ceaf9SAlex Deucher 368d38ceaf9SAlex Deucher struct amdgpu_crtc { 369d38ceaf9SAlex Deucher struct drm_crtc base; 370d38ceaf9SAlex Deucher int crtc_id; 371d38ceaf9SAlex Deucher u16 lut_r[256], lut_g[256], lut_b[256]; 372d38ceaf9SAlex Deucher bool enabled; 373d38ceaf9SAlex Deucher bool can_tile; 374d38ceaf9SAlex Deucher uint32_t crtc_offset; 375d38ceaf9SAlex Deucher struct drm_gem_object *cursor_bo; 376d38ceaf9SAlex Deucher uint64_t cursor_addr; 37729275a9bSAlex Deucher int cursor_x; 37829275a9bSAlex Deucher int cursor_y; 37929275a9bSAlex Deucher int cursor_hot_x; 38029275a9bSAlex Deucher int cursor_hot_y; 381d38ceaf9SAlex Deucher int cursor_width; 382d38ceaf9SAlex Deucher int cursor_height; 383d38ceaf9SAlex Deucher int max_cursor_width; 384d38ceaf9SAlex Deucher int max_cursor_height; 385d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 386d38ceaf9SAlex Deucher u8 h_border; 387d38ceaf9SAlex Deucher u8 v_border; 388d38ceaf9SAlex Deucher fixed20_12 vsc; 389d38ceaf9SAlex Deucher fixed20_12 hsc; 390d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 391d38ceaf9SAlex Deucher u32 pll_id; 392d38ceaf9SAlex Deucher /* page flipping */ 393d38ceaf9SAlex Deucher struct amdgpu_flip_work *pflip_works; 394d38ceaf9SAlex Deucher enum amdgpu_flip_status pflip_status; 395d38ceaf9SAlex Deucher int deferred_flip_completion; 396d38ceaf9SAlex Deucher /* pll sharing */ 397d38ceaf9SAlex Deucher struct amdgpu_atom_ss ss; 398d38ceaf9SAlex Deucher bool ss_enabled; 399d38ceaf9SAlex Deucher u32 adjusted_clock; 400d38ceaf9SAlex Deucher int bpc; 401d38ceaf9SAlex Deucher u32 pll_reference_div; 402d38ceaf9SAlex Deucher u32 pll_post_div; 403d38ceaf9SAlex Deucher u32 pll_flags; 404d38ceaf9SAlex Deucher struct drm_encoder *encoder; 405d38ceaf9SAlex Deucher struct drm_connector *connector; 406d38ceaf9SAlex Deucher /* for dpm */ 407d38ceaf9SAlex Deucher u32 line_time; 408d38ceaf9SAlex Deucher u32 wm_low; 409d38ceaf9SAlex Deucher u32 wm_high; 4108e36f9d3SAlex Deucher u32 lb_vblank_lead_lines; 411d38ceaf9SAlex Deucher struct drm_display_mode hw_mode; 412d38ceaf9SAlex Deucher }; 413d38ceaf9SAlex Deucher 414d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig { 415d38ceaf9SAlex Deucher bool linkb; 416d38ceaf9SAlex Deucher /* atom dig */ 417d38ceaf9SAlex Deucher bool coherent_mode; 418d38ceaf9SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 419d38ceaf9SAlex Deucher /* atom lvds/edp */ 420d38ceaf9SAlex Deucher uint32_t lcd_misc; 421d38ceaf9SAlex Deucher uint16_t panel_pwr_delay; 422d38ceaf9SAlex Deucher uint32_t lcd_ss_id; 423d38ceaf9SAlex Deucher /* panel mode */ 424d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 425d38ceaf9SAlex Deucher struct backlight_device *bl_dev; 426d38ceaf9SAlex Deucher int dpms_mode; 427d38ceaf9SAlex Deucher uint8_t backlight_level; 428d38ceaf9SAlex Deucher int panel_mode; 429d38ceaf9SAlex Deucher struct amdgpu_afmt *afmt; 430d38ceaf9SAlex Deucher }; 431d38ceaf9SAlex Deucher 432d38ceaf9SAlex Deucher struct amdgpu_encoder { 433d38ceaf9SAlex Deucher struct drm_encoder base; 434d38ceaf9SAlex Deucher uint32_t encoder_enum; 435d38ceaf9SAlex Deucher uint32_t encoder_id; 436d38ceaf9SAlex Deucher uint32_t devices; 437d38ceaf9SAlex Deucher uint32_t active_device; 438d38ceaf9SAlex Deucher uint32_t flags; 439d38ceaf9SAlex Deucher uint32_t pixel_clock; 440d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 441d38ceaf9SAlex Deucher enum amdgpu_underscan_type underscan_type; 442d38ceaf9SAlex Deucher uint32_t underscan_hborder; 443d38ceaf9SAlex Deucher uint32_t underscan_vborder; 444d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 445d38ceaf9SAlex Deucher void *enc_priv; 446d38ceaf9SAlex Deucher int audio_polling_active; 447d38ceaf9SAlex Deucher bool is_ext_encoder; 448d38ceaf9SAlex Deucher u16 caps; 449d38ceaf9SAlex Deucher }; 450d38ceaf9SAlex Deucher 451d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig { 452d38ceaf9SAlex Deucher /* displayport */ 453d38ceaf9SAlex Deucher u8 dpcd[DP_RECEIVER_CAP_SIZE]; 454d38ceaf9SAlex Deucher u8 dp_sink_type; 455d38ceaf9SAlex Deucher int dp_clock; 456d38ceaf9SAlex Deucher int dp_lane_count; 457d38ceaf9SAlex Deucher bool edp_on; 458d38ceaf9SAlex Deucher }; 459d38ceaf9SAlex Deucher 460d38ceaf9SAlex Deucher struct amdgpu_gpio_rec { 461d38ceaf9SAlex Deucher bool valid; 462d38ceaf9SAlex Deucher u8 id; 463d38ceaf9SAlex Deucher u32 reg; 464d38ceaf9SAlex Deucher u32 mask; 465d38ceaf9SAlex Deucher u32 shift; 466d38ceaf9SAlex Deucher }; 467d38ceaf9SAlex Deucher 468d38ceaf9SAlex Deucher struct amdgpu_hpd { 469d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd; 470d38ceaf9SAlex Deucher u8 plugged_state; 471d38ceaf9SAlex Deucher struct amdgpu_gpio_rec gpio; 472d38ceaf9SAlex Deucher }; 473d38ceaf9SAlex Deucher 474d38ceaf9SAlex Deucher struct amdgpu_router { 475d38ceaf9SAlex Deucher u32 router_id; 476d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec i2c_info; 477d38ceaf9SAlex Deucher u8 i2c_addr; 478d38ceaf9SAlex Deucher /* i2c mux */ 479d38ceaf9SAlex Deucher bool ddc_valid; 480d38ceaf9SAlex Deucher u8 ddc_mux_type; 481d38ceaf9SAlex Deucher u8 ddc_mux_control_pin; 482d38ceaf9SAlex Deucher u8 ddc_mux_state; 483d38ceaf9SAlex Deucher /* clock/data mux */ 484d38ceaf9SAlex Deucher bool cd_valid; 485d38ceaf9SAlex Deucher u8 cd_mux_type; 486d38ceaf9SAlex Deucher u8 cd_mux_control_pin; 487d38ceaf9SAlex Deucher u8 cd_mux_state; 488d38ceaf9SAlex Deucher }; 489d38ceaf9SAlex Deucher 490d38ceaf9SAlex Deucher enum amdgpu_connector_audio { 491d38ceaf9SAlex Deucher AMDGPU_AUDIO_DISABLE = 0, 492d38ceaf9SAlex Deucher AMDGPU_AUDIO_ENABLE = 1, 493d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO = 2 494d38ceaf9SAlex Deucher }; 495d38ceaf9SAlex Deucher 496d38ceaf9SAlex Deucher enum amdgpu_connector_dither { 497d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE = 0, 498d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_ENABLE = 1, 499d38ceaf9SAlex Deucher }; 500d38ceaf9SAlex Deucher 501d38ceaf9SAlex Deucher struct amdgpu_connector { 502d38ceaf9SAlex Deucher struct drm_connector base; 503d38ceaf9SAlex Deucher uint32_t connector_id; 504d38ceaf9SAlex Deucher uint32_t devices; 505d38ceaf9SAlex Deucher struct amdgpu_i2c_chan *ddc_bus; 506d38ceaf9SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 507d38ceaf9SAlex Deucher bool shared_ddc; 508d38ceaf9SAlex Deucher bool use_digital; 509d38ceaf9SAlex Deucher /* we need to mind the EDID between detect 510d38ceaf9SAlex Deucher and get modes due to analog/digital/tvencoder */ 511d38ceaf9SAlex Deucher struct edid *edid; 512d38ceaf9SAlex Deucher void *con_priv; 513d38ceaf9SAlex Deucher bool dac_load_detect; 514d38ceaf9SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 515d38ceaf9SAlex Deucher uint16_t connector_object_id; 516d38ceaf9SAlex Deucher struct amdgpu_hpd hpd; 517d38ceaf9SAlex Deucher struct amdgpu_router router; 518d38ceaf9SAlex Deucher struct amdgpu_i2c_chan *router_bus; 519d38ceaf9SAlex Deucher enum amdgpu_connector_audio audio; 520d38ceaf9SAlex Deucher enum amdgpu_connector_dither dither; 521d38ceaf9SAlex Deucher unsigned pixelclock_for_modeset; 522d38ceaf9SAlex Deucher }; 523d38ceaf9SAlex Deucher 524d38ceaf9SAlex Deucher struct amdgpu_framebuffer { 525d38ceaf9SAlex Deucher struct drm_framebuffer base; 526d38ceaf9SAlex Deucher struct drm_gem_object *obj; 527d38ceaf9SAlex Deucher }; 528d38ceaf9SAlex Deucher 529d38ceaf9SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 530d38ceaf9SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 531d38ceaf9SAlex Deucher 5328e36f9d3SAlex Deucher /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ 5338e36f9d3SAlex Deucher #define USE_REAL_VBLANKSTART (1 << 30) 5348e36f9d3SAlex Deucher #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 5358e36f9d3SAlex Deucher 536d38ceaf9SAlex Deucher void amdgpu_link_encoder_connector(struct drm_device *dev); 537d38ceaf9SAlex Deucher 538d38ceaf9SAlex Deucher struct drm_connector * 539d38ceaf9SAlex Deucher amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 540d38ceaf9SAlex Deucher struct drm_connector * 541d38ceaf9SAlex Deucher amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 542d38ceaf9SAlex Deucher bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 543d38ceaf9SAlex Deucher u32 pixel_clock); 544d38ceaf9SAlex Deucher 545d38ceaf9SAlex Deucher u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 546d38ceaf9SAlex Deucher struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 547d38ceaf9SAlex Deucher 548d38ceaf9SAlex Deucher bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux); 549d38ceaf9SAlex Deucher 550d38ceaf9SAlex Deucher void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 551d38ceaf9SAlex Deucher 55288e72717SThierry Reding int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 55388e72717SThierry Reding unsigned int flags, int *vpos, int *hpos, 55488e72717SThierry Reding ktime_t *stime, ktime_t *etime, 5553bb403bfSVille Syrjälä const struct drm_display_mode *mode); 556d38ceaf9SAlex Deucher 557d38ceaf9SAlex Deucher int amdgpu_framebuffer_init(struct drm_device *dev, 558d38ceaf9SAlex Deucher struct amdgpu_framebuffer *rfb, 5591eb83451SVille Syrjälä const struct drm_mode_fb_cmd2 *mode_cmd, 560d38ceaf9SAlex Deucher struct drm_gem_object *obj); 561d38ceaf9SAlex Deucher 562d38ceaf9SAlex Deucher int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 563d38ceaf9SAlex Deucher 564d38ceaf9SAlex Deucher void amdgpu_enc_destroy(struct drm_encoder *encoder); 565d38ceaf9SAlex Deucher void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 566d38ceaf9SAlex Deucher bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 567d38ceaf9SAlex Deucher const struct drm_display_mode *mode, 568d38ceaf9SAlex Deucher struct drm_display_mode *adjusted_mode); 569d38ceaf9SAlex Deucher void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 570d38ceaf9SAlex Deucher struct drm_display_mode *adjusted_mode); 571d38ceaf9SAlex Deucher int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 572d38ceaf9SAlex Deucher 573d38ceaf9SAlex Deucher /* fbdev layer */ 574d38ceaf9SAlex Deucher int amdgpu_fbdev_init(struct amdgpu_device *adev); 575d38ceaf9SAlex Deucher void amdgpu_fbdev_fini(struct amdgpu_device *adev); 576d38ceaf9SAlex Deucher void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 577d38ceaf9SAlex Deucher int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 578d38ceaf9SAlex Deucher bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 5798b7530b1SAlex Deucher void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); 580d38ceaf9SAlex Deucher 581d38ceaf9SAlex Deucher void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); 582d38ceaf9SAlex Deucher 583d38ceaf9SAlex Deucher 584d38ceaf9SAlex Deucher int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 585d38ceaf9SAlex Deucher 586d38ceaf9SAlex Deucher /* amdgpu_display.c */ 587d38ceaf9SAlex Deucher void amdgpu_print_display_setup(struct drm_device *dev); 588d38ceaf9SAlex Deucher int amdgpu_modeset_create_props(struct amdgpu_device *adev); 589d38ceaf9SAlex Deucher int amdgpu_crtc_set_config(struct drm_mode_set *set); 590d38ceaf9SAlex Deucher int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 591d38ceaf9SAlex Deucher struct drm_framebuffer *fb, 592d38ceaf9SAlex Deucher struct drm_pending_vblank_event *event, 593d38ceaf9SAlex Deucher uint32_t page_flip_flags); 594d38ceaf9SAlex Deucher extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 595d38ceaf9SAlex Deucher 596d38ceaf9SAlex Deucher #endif 597