1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3d38ceaf9SAlex Deucher * VA Linux Systems Inc., Fremont, California. 4d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Original Authors: 25d38ceaf9SAlex Deucher * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26d38ceaf9SAlex Deucher * 27d38ceaf9SAlex Deucher * Kernel port Author: Dave Airlie 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher 30d38ceaf9SAlex Deucher #ifndef AMDGPU_MODE_H 31d38ceaf9SAlex Deucher #define AMDGPU_MODE_H 32d38ceaf9SAlex Deucher 33d38ceaf9SAlex Deucher #include <drm/drm_crtc.h> 34d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 359338203cSLaurent Pinchart #include <drm/drm_encoder.h> 36d38ceaf9SAlex Deucher #include <drm/drm_dp_helper.h> 37d38ceaf9SAlex Deucher #include <drm/drm_fixed.h> 38d38ceaf9SAlex Deucher #include <drm/drm_crtc_helper.h> 39b516a9efSDaniel Vetter #include <drm/drm_fb_helper.h> 40d38ceaf9SAlex Deucher #include <drm/drm_plane_helper.h> 41fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 42d38ceaf9SAlex Deucher #include <linux/i2c.h> 43d38ceaf9SAlex Deucher #include <linux/i2c-algo-bit.h> 4446ac3622SEmily Deng #include <linux/hrtimer.h> 4546ac3622SEmily Deng #include "amdgpu_irq.h" 46d38ceaf9SAlex Deucher 474562236bSHarry Wentland #include <drm/drm_dp_mst_helper.h> 484562236bSHarry Wentland #include "modules/inc/mod_freesync.h" 495d1c59c4SAurabindo Pillai #include "amdgpu_dm_irq_params.h" 504562236bSHarry Wentland 51d38ceaf9SAlex Deucher struct amdgpu_bo; 52d38ceaf9SAlex Deucher struct amdgpu_device; 53d38ceaf9SAlex Deucher struct amdgpu_encoder; 54d38ceaf9SAlex Deucher struct amdgpu_router; 55d38ceaf9SAlex Deucher struct amdgpu_hpd; 56d38ceaf9SAlex Deucher 57d38ceaf9SAlex Deucher #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 58d38ceaf9SAlex Deucher #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 59d38ceaf9SAlex Deucher #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 60d38ceaf9SAlex Deucher #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 61d38ceaf9SAlex Deucher 623d12beb3SNicholas Kazlauskas #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 630604b36cSAndrey Grodzovsky 64d38ceaf9SAlex Deucher #define AMDGPU_MAX_HPD_PINS 6 65d38ceaf9SAlex Deucher #define AMDGPU_MAX_CRTCS 6 66d4e13b0dSAlex Deucher #define AMDGPU_MAX_PLANES 6 6722384459SAlex Deucher #define AMDGPU_MAX_AFMT_BLOCKS 9 68d38ceaf9SAlex Deucher 69d38ceaf9SAlex Deucher enum amdgpu_rmx_type { 70d38ceaf9SAlex Deucher RMX_OFF, 71d38ceaf9SAlex Deucher RMX_FULL, 72d38ceaf9SAlex Deucher RMX_CENTER, 73d38ceaf9SAlex Deucher RMX_ASPECT 74d38ceaf9SAlex Deucher }; 75d38ceaf9SAlex Deucher 76d38ceaf9SAlex Deucher enum amdgpu_underscan_type { 77d38ceaf9SAlex Deucher UNDERSCAN_OFF, 78d38ceaf9SAlex Deucher UNDERSCAN_ON, 79d38ceaf9SAlex Deucher UNDERSCAN_AUTO, 80d38ceaf9SAlex Deucher }; 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 83d38ceaf9SAlex Deucher #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 84d38ceaf9SAlex Deucher 85d38ceaf9SAlex Deucher enum amdgpu_hpd_id { 86d38ceaf9SAlex Deucher AMDGPU_HPD_1 = 0, 87d38ceaf9SAlex Deucher AMDGPU_HPD_2, 88d38ceaf9SAlex Deucher AMDGPU_HPD_3, 89d38ceaf9SAlex Deucher AMDGPU_HPD_4, 90d38ceaf9SAlex Deucher AMDGPU_HPD_5, 91d38ceaf9SAlex Deucher AMDGPU_HPD_6, 92d38ceaf9SAlex Deucher AMDGPU_HPD_NONE = 0xff, 93d38ceaf9SAlex Deucher }; 94d38ceaf9SAlex Deucher 95d38ceaf9SAlex Deucher enum amdgpu_crtc_irq { 96d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK1 = 0, 97d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK2, 98d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK3, 99d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK4, 100d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK5, 101d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VBLANK6, 102d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE1, 103d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE2, 104d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE3, 105d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE4, 106d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE5, 107d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_VLINE6, 108d38ceaf9SAlex Deucher AMDGPU_CRTC_IRQ_NONE = 0xff 109d38ceaf9SAlex Deucher }; 110d38ceaf9SAlex Deucher 111d38ceaf9SAlex Deucher enum amdgpu_pageflip_irq { 112d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D1 = 0, 113d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D2, 114d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D3, 115d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D4, 116d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D5, 117d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_D6, 118d38ceaf9SAlex Deucher AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 119d38ceaf9SAlex Deucher }; 120d38ceaf9SAlex Deucher 121d38ceaf9SAlex Deucher enum amdgpu_flip_status { 122d38ceaf9SAlex Deucher AMDGPU_FLIP_NONE, 123d38ceaf9SAlex Deucher AMDGPU_FLIP_PENDING, 124d38ceaf9SAlex Deucher AMDGPU_FLIP_SUBMITTED 125d38ceaf9SAlex Deucher }; 126d38ceaf9SAlex Deucher 127d38ceaf9SAlex Deucher #define AMDGPU_MAX_I2C_BUS 16 128d38ceaf9SAlex Deucher 129d38ceaf9SAlex Deucher /* amdgpu gpio-based i2c 130d38ceaf9SAlex Deucher * 1. "mask" reg and bits 131d38ceaf9SAlex Deucher * grabs the gpio pins for software use 132d38ceaf9SAlex Deucher * 0=not held 1=held 133d38ceaf9SAlex Deucher * 2. "a" reg and bits 134d38ceaf9SAlex Deucher * output pin value 135d38ceaf9SAlex Deucher * 0=low 1=high 136d38ceaf9SAlex Deucher * 3. "en" reg and bits 137d38ceaf9SAlex Deucher * sets the pin direction 138d38ceaf9SAlex Deucher * 0=input 1=output 139d38ceaf9SAlex Deucher * 4. "y" reg and bits 140d38ceaf9SAlex Deucher * input pin value 141d38ceaf9SAlex Deucher * 0=low 1=high 142d38ceaf9SAlex Deucher */ 143d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec { 144d38ceaf9SAlex Deucher bool valid; 145d38ceaf9SAlex Deucher /* id used by atom */ 146d38ceaf9SAlex Deucher uint8_t i2c_id; 147d38ceaf9SAlex Deucher /* id used by atom */ 148d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd; 149d38ceaf9SAlex Deucher /* can be used with hw i2c engine */ 150d38ceaf9SAlex Deucher bool hw_capable; 151d38ceaf9SAlex Deucher /* uses multi-media i2c engine */ 152d38ceaf9SAlex Deucher bool mm_i2c; 153d38ceaf9SAlex Deucher /* regs and bits */ 154d38ceaf9SAlex Deucher uint32_t mask_clk_reg; 155d38ceaf9SAlex Deucher uint32_t mask_data_reg; 156d38ceaf9SAlex Deucher uint32_t a_clk_reg; 157d38ceaf9SAlex Deucher uint32_t a_data_reg; 158d38ceaf9SAlex Deucher uint32_t en_clk_reg; 159d38ceaf9SAlex Deucher uint32_t en_data_reg; 160d38ceaf9SAlex Deucher uint32_t y_clk_reg; 161d38ceaf9SAlex Deucher uint32_t y_data_reg; 162d38ceaf9SAlex Deucher uint32_t mask_clk_mask; 163d38ceaf9SAlex Deucher uint32_t mask_data_mask; 164d38ceaf9SAlex Deucher uint32_t a_clk_mask; 165d38ceaf9SAlex Deucher uint32_t a_data_mask; 166d38ceaf9SAlex Deucher uint32_t en_clk_mask; 167d38ceaf9SAlex Deucher uint32_t en_data_mask; 168d38ceaf9SAlex Deucher uint32_t y_clk_mask; 169d38ceaf9SAlex Deucher uint32_t y_data_mask; 170d38ceaf9SAlex Deucher }; 171d38ceaf9SAlex Deucher 172d38ceaf9SAlex Deucher #define AMDGPU_MAX_BIOS_CONNECTOR 16 173d38ceaf9SAlex Deucher 174d38ceaf9SAlex Deucher /* pll flags */ 175d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 176d38ceaf9SAlex Deucher #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 177d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 178d38ceaf9SAlex Deucher #define AMDGPU_PLL_LEGACY (1 << 3) 179d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 180d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 181d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 182d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 183d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 184d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 185d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 186d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 187d38ceaf9SAlex Deucher #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 188d38ceaf9SAlex Deucher #define AMDGPU_PLL_IS_LCD (1 << 13) 189d38ceaf9SAlex Deucher #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 190d38ceaf9SAlex Deucher 191d38ceaf9SAlex Deucher struct amdgpu_pll { 192d38ceaf9SAlex Deucher /* reference frequency */ 193d38ceaf9SAlex Deucher uint32_t reference_freq; 194d38ceaf9SAlex Deucher 195d38ceaf9SAlex Deucher /* fixed dividers */ 196d38ceaf9SAlex Deucher uint32_t reference_div; 197d38ceaf9SAlex Deucher uint32_t post_div; 198d38ceaf9SAlex Deucher 199d38ceaf9SAlex Deucher /* pll in/out limits */ 200d38ceaf9SAlex Deucher uint32_t pll_in_min; 201d38ceaf9SAlex Deucher uint32_t pll_in_max; 202d38ceaf9SAlex Deucher uint32_t pll_out_min; 203d38ceaf9SAlex Deucher uint32_t pll_out_max; 204d38ceaf9SAlex Deucher uint32_t lcd_pll_out_min; 205d38ceaf9SAlex Deucher uint32_t lcd_pll_out_max; 206d38ceaf9SAlex Deucher uint32_t best_vco; 207d38ceaf9SAlex Deucher 208d38ceaf9SAlex Deucher /* divider limits */ 209d38ceaf9SAlex Deucher uint32_t min_ref_div; 210d38ceaf9SAlex Deucher uint32_t max_ref_div; 211d38ceaf9SAlex Deucher uint32_t min_post_div; 212d38ceaf9SAlex Deucher uint32_t max_post_div; 213d38ceaf9SAlex Deucher uint32_t min_feedback_div; 214d38ceaf9SAlex Deucher uint32_t max_feedback_div; 215d38ceaf9SAlex Deucher uint32_t min_frac_feedback_div; 216d38ceaf9SAlex Deucher uint32_t max_frac_feedback_div; 217d38ceaf9SAlex Deucher 218d38ceaf9SAlex Deucher /* flags for the current clock */ 219d38ceaf9SAlex Deucher uint32_t flags; 220d38ceaf9SAlex Deucher 221d38ceaf9SAlex Deucher /* pll id */ 222d38ceaf9SAlex Deucher uint32_t id; 223d38ceaf9SAlex Deucher }; 224d38ceaf9SAlex Deucher 225d38ceaf9SAlex Deucher struct amdgpu_i2c_chan { 226d38ceaf9SAlex Deucher struct i2c_adapter adapter; 227d38ceaf9SAlex Deucher struct drm_device *dev; 228d38ceaf9SAlex Deucher struct i2c_algo_bit_data bit; 229d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec rec; 230d38ceaf9SAlex Deucher struct drm_dp_aux aux; 231d38ceaf9SAlex Deucher bool has_aux; 232d38ceaf9SAlex Deucher struct mutex mutex; 233d38ceaf9SAlex Deucher }; 234d38ceaf9SAlex Deucher 235d38ceaf9SAlex Deucher struct amdgpu_fbdev; 236d38ceaf9SAlex Deucher 237d38ceaf9SAlex Deucher struct amdgpu_afmt { 238d38ceaf9SAlex Deucher bool enabled; 239d38ceaf9SAlex Deucher int offset; 240d38ceaf9SAlex Deucher bool last_buffer_filled_status; 241d38ceaf9SAlex Deucher int id; 242d38ceaf9SAlex Deucher struct amdgpu_audio_pin *pin; 243d38ceaf9SAlex Deucher }; 244d38ceaf9SAlex Deucher 245d38ceaf9SAlex Deucher /* 246d38ceaf9SAlex Deucher * Audio 247d38ceaf9SAlex Deucher */ 248d38ceaf9SAlex Deucher struct amdgpu_audio_pin { 249d38ceaf9SAlex Deucher int channels; 250d38ceaf9SAlex Deucher int rate; 251d38ceaf9SAlex Deucher int bits_per_sample; 252d38ceaf9SAlex Deucher u8 status_bits; 253d38ceaf9SAlex Deucher u8 category_code; 254d38ceaf9SAlex Deucher u32 offset; 255d38ceaf9SAlex Deucher bool connected; 256d38ceaf9SAlex Deucher u32 id; 257d38ceaf9SAlex Deucher }; 258d38ceaf9SAlex Deucher 259d38ceaf9SAlex Deucher struct amdgpu_audio { 260d38ceaf9SAlex Deucher bool enabled; 261d38ceaf9SAlex Deucher struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 262d38ceaf9SAlex Deucher int num_pins; 263d38ceaf9SAlex Deucher }; 264d38ceaf9SAlex Deucher 265d38ceaf9SAlex Deucher struct amdgpu_display_funcs { 266d38ceaf9SAlex Deucher /* display watermarks */ 267d38ceaf9SAlex Deucher void (*bandwidth_update)(struct amdgpu_device *adev); 268d38ceaf9SAlex Deucher /* get frame count */ 269d38ceaf9SAlex Deucher u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 270d38ceaf9SAlex Deucher /* set backlight level */ 271d38ceaf9SAlex Deucher void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 272d38ceaf9SAlex Deucher u8 level); 273d38ceaf9SAlex Deucher /* get backlight level */ 274d38ceaf9SAlex Deucher u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 275d38ceaf9SAlex Deucher /* hotplug detect */ 276d38ceaf9SAlex Deucher bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 277d38ceaf9SAlex Deucher void (*hpd_set_polarity)(struct amdgpu_device *adev, 278d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd); 279d38ceaf9SAlex Deucher u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 280d38ceaf9SAlex Deucher /* pageflipping */ 281d38ceaf9SAlex Deucher void (*page_flip)(struct amdgpu_device *adev, 282cb9e59d7SAlex Deucher int crtc_id, u64 crtc_base, bool async); 283d38ceaf9SAlex Deucher int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 284d38ceaf9SAlex Deucher u32 *vbl, u32 *position); 285d38ceaf9SAlex Deucher /* display topology setup */ 286d38ceaf9SAlex Deucher void (*add_encoder)(struct amdgpu_device *adev, 287d38ceaf9SAlex Deucher uint32_t encoder_enum, 288d38ceaf9SAlex Deucher uint32_t supported_device, 289d38ceaf9SAlex Deucher u16 caps); 290d38ceaf9SAlex Deucher void (*add_connector)(struct amdgpu_device *adev, 291d38ceaf9SAlex Deucher uint32_t connector_id, 292d38ceaf9SAlex Deucher uint32_t supported_device, 293d38ceaf9SAlex Deucher int connector_type, 294d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 295d38ceaf9SAlex Deucher uint16_t connector_object_id, 296d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 297d38ceaf9SAlex Deucher struct amdgpu_router *router); 2984562236bSHarry Wentland 2994562236bSHarry Wentland 3004562236bSHarry Wentland }; 3014562236bSHarry Wentland 3024562236bSHarry Wentland struct amdgpu_framebuffer { 3034562236bSHarry Wentland struct drm_framebuffer base; 304dd55d12cSAndrey Grodzovsky 3056eed95b0SBas Nieuwenhuizen uint64_t tiling_flags; 3066eed95b0SBas Nieuwenhuizen bool tmz_surface; 3076eed95b0SBas Nieuwenhuizen 308dd55d12cSAndrey Grodzovsky /* caching for later use */ 309dd55d12cSAndrey Grodzovsky uint64_t address; 3104562236bSHarry Wentland }; 3114562236bSHarry Wentland 3124562236bSHarry Wentland struct amdgpu_fbdev { 3134562236bSHarry Wentland struct drm_fb_helper helper; 3144562236bSHarry Wentland struct amdgpu_framebuffer rfb; 3154562236bSHarry Wentland struct list_head fbdev_list; 3164562236bSHarry Wentland struct amdgpu_device *adev; 317d38ceaf9SAlex Deucher }; 318d38ceaf9SAlex Deucher 319d38ceaf9SAlex Deucher struct amdgpu_mode_info { 320d38ceaf9SAlex Deucher struct atom_context *atom_context; 321d38ceaf9SAlex Deucher struct card_info *atom_card_info; 322d38ceaf9SAlex Deucher bool mode_config_initialized; 323f195038cSAlex Deucher struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 324f180b4bcSHarry Wentland struct drm_plane *planes[AMDGPU_MAX_PLANES]; 325f195038cSAlex Deucher struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 326d38ceaf9SAlex Deucher /* DVI-I properties */ 327d38ceaf9SAlex Deucher struct drm_property *coherent_mode_property; 328d38ceaf9SAlex Deucher /* DAC enable load detect */ 329d38ceaf9SAlex Deucher struct drm_property *load_detect_property; 330d38ceaf9SAlex Deucher /* underscan */ 331d38ceaf9SAlex Deucher struct drm_property *underscan_property; 332d38ceaf9SAlex Deucher struct drm_property *underscan_hborder_property; 333d38ceaf9SAlex Deucher struct drm_property *underscan_vborder_property; 334d38ceaf9SAlex Deucher /* audio */ 335d38ceaf9SAlex Deucher struct drm_property *audio_property; 336d38ceaf9SAlex Deucher /* FMT dithering */ 337d38ceaf9SAlex Deucher struct drm_property *dither_property; 338c1ee92f9SDavid Francis /* Adaptive Backlight Modulation (power feature) */ 339c1ee92f9SDavid Francis struct drm_property *abm_level_property; 340d38ceaf9SAlex Deucher /* hardcoded DFP edid from BIOS */ 341d38ceaf9SAlex Deucher struct edid *bios_hardcoded_edid; 342d38ceaf9SAlex Deucher int bios_hardcoded_edid_size; 343d38ceaf9SAlex Deucher 344d38ceaf9SAlex Deucher /* pointer to fbdev info structure */ 345d38ceaf9SAlex Deucher struct amdgpu_fbdev *rfbdev; 346d38ceaf9SAlex Deucher /* firmware flags */ 347*5968c6a2SHawking Zhang u32 firmware_flags; 348d38ceaf9SAlex Deucher /* pointer to backlight encoder */ 349d38ceaf9SAlex Deucher struct amdgpu_encoder *bl_encoder; 350a59b3c80SAlex Deucher u8 bl_level; /* saved backlight level */ 351d38ceaf9SAlex Deucher struct amdgpu_audio audio; /* audio stuff */ 352d38ceaf9SAlex Deucher int num_crtc; /* number of crtcs */ 353d38ceaf9SAlex Deucher int num_hpd; /* number of hpd pins */ 354d38ceaf9SAlex Deucher int num_dig; /* number of dig blocks */ 355d38ceaf9SAlex Deucher int disp_priority; 356d38ceaf9SAlex Deucher const struct amdgpu_display_funcs *funcs; 357e04a6123SDave Airlie const enum drm_plane_type *plane_type; 358d38ceaf9SAlex Deucher }; 359d38ceaf9SAlex Deucher 360d38ceaf9SAlex Deucher #define AMDGPU_MAX_BL_LEVEL 0xFF 361d38ceaf9SAlex Deucher 362d38ceaf9SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 363d38ceaf9SAlex Deucher 364d38ceaf9SAlex Deucher struct amdgpu_backlight_privdata { 365d38ceaf9SAlex Deucher struct amdgpu_encoder *encoder; 366d38ceaf9SAlex Deucher uint8_t negative; 367d38ceaf9SAlex Deucher }; 368d38ceaf9SAlex Deucher 369d38ceaf9SAlex Deucher #endif 370d38ceaf9SAlex Deucher 371d38ceaf9SAlex Deucher struct amdgpu_atom_ss { 372d38ceaf9SAlex Deucher uint16_t percentage; 373d38ceaf9SAlex Deucher uint16_t percentage_divider; 374d38ceaf9SAlex Deucher uint8_t type; 375d38ceaf9SAlex Deucher uint16_t step; 376d38ceaf9SAlex Deucher uint8_t delay; 377d38ceaf9SAlex Deucher uint8_t range; 378d38ceaf9SAlex Deucher uint8_t refdiv; 379d38ceaf9SAlex Deucher /* asic_ss */ 380d38ceaf9SAlex Deucher uint16_t rate; 381d38ceaf9SAlex Deucher uint16_t amount; 382d38ceaf9SAlex Deucher }; 383d38ceaf9SAlex Deucher 384d38ceaf9SAlex Deucher struct amdgpu_crtc { 385d38ceaf9SAlex Deucher struct drm_crtc base; 386d38ceaf9SAlex Deucher int crtc_id; 387d38ceaf9SAlex Deucher bool enabled; 388d38ceaf9SAlex Deucher bool can_tile; 389d38ceaf9SAlex Deucher uint32_t crtc_offset; 390d38ceaf9SAlex Deucher struct drm_gem_object *cursor_bo; 391d38ceaf9SAlex Deucher uint64_t cursor_addr; 39229275a9bSAlex Deucher int cursor_x; 39329275a9bSAlex Deucher int cursor_y; 39429275a9bSAlex Deucher int cursor_hot_x; 39529275a9bSAlex Deucher int cursor_hot_y; 396d38ceaf9SAlex Deucher int cursor_width; 397d38ceaf9SAlex Deucher int cursor_height; 398d38ceaf9SAlex Deucher int max_cursor_width; 399d38ceaf9SAlex Deucher int max_cursor_height; 400d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 401d38ceaf9SAlex Deucher u8 h_border; 402d38ceaf9SAlex Deucher u8 v_border; 403d38ceaf9SAlex Deucher fixed20_12 vsc; 404d38ceaf9SAlex Deucher fixed20_12 hsc; 405d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 406d38ceaf9SAlex Deucher u32 pll_id; 407d38ceaf9SAlex Deucher /* page flipping */ 408d38ceaf9SAlex Deucher struct amdgpu_flip_work *pflip_works; 409d38ceaf9SAlex Deucher enum amdgpu_flip_status pflip_status; 410d38ceaf9SAlex Deucher int deferred_flip_completion; 4115d1c59c4SAurabindo Pillai /* parameters access from DM IRQ handler */ 4125d1c59c4SAurabindo Pillai struct dm_irq_params dm_irq_params; 413d38ceaf9SAlex Deucher /* pll sharing */ 414d38ceaf9SAlex Deucher struct amdgpu_atom_ss ss; 415d38ceaf9SAlex Deucher bool ss_enabled; 416d38ceaf9SAlex Deucher u32 adjusted_clock; 417d38ceaf9SAlex Deucher int bpc; 418d38ceaf9SAlex Deucher u32 pll_reference_div; 419d38ceaf9SAlex Deucher u32 pll_post_div; 420d38ceaf9SAlex Deucher u32 pll_flags; 421d38ceaf9SAlex Deucher struct drm_encoder *encoder; 422d38ceaf9SAlex Deucher struct drm_connector *connector; 423d38ceaf9SAlex Deucher /* for dpm */ 424d38ceaf9SAlex Deucher u32 line_time; 425d38ceaf9SAlex Deucher u32 wm_low; 426d38ceaf9SAlex Deucher u32 wm_high; 4278e36f9d3SAlex Deucher u32 lb_vblank_lead_lines; 428d38ceaf9SAlex Deucher struct drm_display_mode hw_mode; 4290f66356dSEmily Deng /* for virtual dce */ 4300f66356dSEmily Deng struct hrtimer vblank_timer; 4310f66356dSEmily Deng enum amdgpu_interrupt_state vsync_timer_enabled; 4324562236bSHarry Wentland 4334562236bSHarry Wentland int otg_inst; 434dd55d12cSAndrey Grodzovsky struct drm_pending_vblank_event *event; 435d38ceaf9SAlex Deucher }; 436d38ceaf9SAlex Deucher 437d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig { 438d38ceaf9SAlex Deucher bool linkb; 439d38ceaf9SAlex Deucher /* atom dig */ 440d38ceaf9SAlex Deucher bool coherent_mode; 441d38ceaf9SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 442d38ceaf9SAlex Deucher /* atom lvds/edp */ 443d38ceaf9SAlex Deucher uint32_t lcd_misc; 444d38ceaf9SAlex Deucher uint16_t panel_pwr_delay; 445d38ceaf9SAlex Deucher uint32_t lcd_ss_id; 446d38ceaf9SAlex Deucher /* panel mode */ 447d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 448d38ceaf9SAlex Deucher struct backlight_device *bl_dev; 449d38ceaf9SAlex Deucher int dpms_mode; 450d38ceaf9SAlex Deucher uint8_t backlight_level; 451d38ceaf9SAlex Deucher int panel_mode; 452d38ceaf9SAlex Deucher struct amdgpu_afmt *afmt; 453d38ceaf9SAlex Deucher }; 454d38ceaf9SAlex Deucher 455d38ceaf9SAlex Deucher struct amdgpu_encoder { 456d38ceaf9SAlex Deucher struct drm_encoder base; 457d38ceaf9SAlex Deucher uint32_t encoder_enum; 458d38ceaf9SAlex Deucher uint32_t encoder_id; 459d38ceaf9SAlex Deucher uint32_t devices; 460d38ceaf9SAlex Deucher uint32_t active_device; 461d38ceaf9SAlex Deucher uint32_t flags; 462d38ceaf9SAlex Deucher uint32_t pixel_clock; 463d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 464d38ceaf9SAlex Deucher enum amdgpu_underscan_type underscan_type; 465d38ceaf9SAlex Deucher uint32_t underscan_hborder; 466d38ceaf9SAlex Deucher uint32_t underscan_vborder; 467d38ceaf9SAlex Deucher struct drm_display_mode native_mode; 468d38ceaf9SAlex Deucher void *enc_priv; 469d38ceaf9SAlex Deucher int audio_polling_active; 470d38ceaf9SAlex Deucher bool is_ext_encoder; 471d38ceaf9SAlex Deucher u16 caps; 472d38ceaf9SAlex Deucher }; 473d38ceaf9SAlex Deucher 474d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig { 475d38ceaf9SAlex Deucher /* displayport */ 476d38ceaf9SAlex Deucher u8 dpcd[DP_RECEIVER_CAP_SIZE]; 47765bf2cf9SOleg Vasilev u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 478d38ceaf9SAlex Deucher u8 dp_sink_type; 479d38ceaf9SAlex Deucher int dp_clock; 480d38ceaf9SAlex Deucher int dp_lane_count; 481d38ceaf9SAlex Deucher bool edp_on; 482d38ceaf9SAlex Deucher }; 483d38ceaf9SAlex Deucher 484d38ceaf9SAlex Deucher struct amdgpu_gpio_rec { 485d38ceaf9SAlex Deucher bool valid; 486d38ceaf9SAlex Deucher u8 id; 487d38ceaf9SAlex Deucher u32 reg; 488d38ceaf9SAlex Deucher u32 mask; 489d38ceaf9SAlex Deucher u32 shift; 490d38ceaf9SAlex Deucher }; 491d38ceaf9SAlex Deucher 492d38ceaf9SAlex Deucher struct amdgpu_hpd { 493d38ceaf9SAlex Deucher enum amdgpu_hpd_id hpd; 494d38ceaf9SAlex Deucher u8 plugged_state; 495d38ceaf9SAlex Deucher struct amdgpu_gpio_rec gpio; 496d38ceaf9SAlex Deucher }; 497d38ceaf9SAlex Deucher 498d38ceaf9SAlex Deucher struct amdgpu_router { 499d38ceaf9SAlex Deucher u32 router_id; 500d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec i2c_info; 501d38ceaf9SAlex Deucher u8 i2c_addr; 502d38ceaf9SAlex Deucher /* i2c mux */ 503d38ceaf9SAlex Deucher bool ddc_valid; 504d38ceaf9SAlex Deucher u8 ddc_mux_type; 505d38ceaf9SAlex Deucher u8 ddc_mux_control_pin; 506d38ceaf9SAlex Deucher u8 ddc_mux_state; 507d38ceaf9SAlex Deucher /* clock/data mux */ 508d38ceaf9SAlex Deucher bool cd_valid; 509d38ceaf9SAlex Deucher u8 cd_mux_type; 510d38ceaf9SAlex Deucher u8 cd_mux_control_pin; 511d38ceaf9SAlex Deucher u8 cd_mux_state; 512d38ceaf9SAlex Deucher }; 513d38ceaf9SAlex Deucher 514d38ceaf9SAlex Deucher enum amdgpu_connector_audio { 515d38ceaf9SAlex Deucher AMDGPU_AUDIO_DISABLE = 0, 516d38ceaf9SAlex Deucher AMDGPU_AUDIO_ENABLE = 1, 517d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO = 2 518d38ceaf9SAlex Deucher }; 519d38ceaf9SAlex Deucher 520d38ceaf9SAlex Deucher enum amdgpu_connector_dither { 521d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE = 0, 522d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_ENABLE = 1, 523d38ceaf9SAlex Deucher }; 524d38ceaf9SAlex Deucher 5254562236bSHarry Wentland struct amdgpu_dm_dp_aux { 5264562236bSHarry Wentland struct drm_dp_aux aux; 52746df790cSAndrey Grodzovsky struct ddc_service *ddc_service; 5284562236bSHarry Wentland }; 5294562236bSHarry Wentland 5304562236bSHarry Wentland struct amdgpu_i2c_adapter { 5314562236bSHarry Wentland struct i2c_adapter base; 53246df790cSAndrey Grodzovsky 53346df790cSAndrey Grodzovsky struct ddc_service *ddc_service; 5344562236bSHarry Wentland }; 5354562236bSHarry Wentland 5364562236bSHarry Wentland #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 5374562236bSHarry Wentland 538d38ceaf9SAlex Deucher struct amdgpu_connector { 539d38ceaf9SAlex Deucher struct drm_connector base; 540d38ceaf9SAlex Deucher uint32_t connector_id; 541d38ceaf9SAlex Deucher uint32_t devices; 542d38ceaf9SAlex Deucher struct amdgpu_i2c_chan *ddc_bus; 543d38ceaf9SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 544d38ceaf9SAlex Deucher bool shared_ddc; 545d38ceaf9SAlex Deucher bool use_digital; 546d38ceaf9SAlex Deucher /* we need to mind the EDID between detect 547d38ceaf9SAlex Deucher and get modes due to analog/digital/tvencoder */ 548d38ceaf9SAlex Deucher struct edid *edid; 549d38ceaf9SAlex Deucher void *con_priv; 550d38ceaf9SAlex Deucher bool dac_load_detect; 551d38ceaf9SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 552d38ceaf9SAlex Deucher uint16_t connector_object_id; 553d38ceaf9SAlex Deucher struct amdgpu_hpd hpd; 554d38ceaf9SAlex Deucher struct amdgpu_router router; 555d38ceaf9SAlex Deucher struct amdgpu_i2c_chan *router_bus; 556d38ceaf9SAlex Deucher enum amdgpu_connector_audio audio; 557d38ceaf9SAlex Deucher enum amdgpu_connector_dither dither; 558d38ceaf9SAlex Deucher unsigned pixelclock_for_modeset; 559d38ceaf9SAlex Deucher }; 560d38ceaf9SAlex Deucher 5614562236bSHarry Wentland /* TODO: start to use this struct and remove same field from base one */ 5624562236bSHarry Wentland struct amdgpu_mst_connector { 5634562236bSHarry Wentland struct amdgpu_connector base; 5644562236bSHarry Wentland 5654562236bSHarry Wentland struct drm_dp_mst_topology_mgr mst_mgr; 5664562236bSHarry Wentland struct amdgpu_dm_dp_aux dm_dp_aux; 5674562236bSHarry Wentland struct drm_dp_mst_port *port; 5684562236bSHarry Wentland struct amdgpu_connector *mst_port; 5694562236bSHarry Wentland bool is_mst_connector; 5704562236bSHarry Wentland struct amdgpu_encoder *mst_encoder; 571d38ceaf9SAlex Deucher }; 572d38ceaf9SAlex Deucher 573d38ceaf9SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 574d38ceaf9SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 575d38ceaf9SAlex Deucher 576aa8e286aSSamuel Li /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 5771bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_VALID (1 << 0) 5781bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 5791bf6ad62SDaniel Vetter #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 5808e36f9d3SAlex Deucher #define USE_REAL_VBLANKSTART (1 << 30) 5818e36f9d3SAlex Deucher #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 5828e36f9d3SAlex Deucher 583d38ceaf9SAlex Deucher void amdgpu_link_encoder_connector(struct drm_device *dev); 584d38ceaf9SAlex Deucher 585d38ceaf9SAlex Deucher struct drm_connector * 586d38ceaf9SAlex Deucher amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 587d38ceaf9SAlex Deucher struct drm_connector * 588d38ceaf9SAlex Deucher amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 589d38ceaf9SAlex Deucher bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 590d38ceaf9SAlex Deucher u32 pixel_clock); 591d38ceaf9SAlex Deucher 592d38ceaf9SAlex Deucher u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 593d38ceaf9SAlex Deucher struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 594d38ceaf9SAlex Deucher 595e0b5b5ecSSamuel Li bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 596e0b5b5ecSSamuel Li bool use_aux); 597d38ceaf9SAlex Deucher 598d38ceaf9SAlex Deucher void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 599d38ceaf9SAlex Deucher 600aa8e286aSSamuel Li int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 601aa8e286aSSamuel Li unsigned int pipe, unsigned int flags, int *vpos, 602aa8e286aSSamuel Li int *hpos, ktime_t *stime, ktime_t *etime, 6033bb403bfSVille Syrjälä const struct drm_display_mode *mode); 604d38ceaf9SAlex Deucher 605f258907fSMark Yacoub int amdgpu_display_gem_fb_init(struct drm_device *dev, 606f258907fSMark Yacoub struct amdgpu_framebuffer *rfb, 607f258907fSMark Yacoub const struct drm_mode_fb_cmd2 *mode_cmd, 608f258907fSMark Yacoub struct drm_gem_object *obj); 609f258907fSMark Yacoub int amdgpu_display_gem_fb_verify_and_init( 610f258907fSMark Yacoub struct drm_device *dev, struct amdgpu_framebuffer *rfb, 611f258907fSMark Yacoub struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd, 612f258907fSMark Yacoub struct drm_gem_object *obj); 6139da3f2d9SSamuel Li int amdgpu_display_framebuffer_init(struct drm_device *dev, 614d38ceaf9SAlex Deucher struct amdgpu_framebuffer *rfb, 6151eb83451SVille Syrjälä const struct drm_mode_fb_cmd2 *mode_cmd, 616d38ceaf9SAlex Deucher struct drm_gem_object *obj); 617d38ceaf9SAlex Deucher 618d38ceaf9SAlex Deucher int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 619d38ceaf9SAlex Deucher 620d38ceaf9SAlex Deucher void amdgpu_enc_destroy(struct drm_encoder *encoder); 621d38ceaf9SAlex Deucher void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 6220c16443aSSamuel Li bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 623d38ceaf9SAlex Deucher const struct drm_display_mode *mode, 624d38ceaf9SAlex Deucher struct drm_display_mode *adjusted_mode); 625d38ceaf9SAlex Deucher void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 626d38ceaf9SAlex Deucher struct drm_display_mode *adjusted_mode); 627734dd01dSSamuel Li int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 628d38ceaf9SAlex Deucher 629ea702333SThomas Zimmermann bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 630ea702333SThomas Zimmermann bool in_vblank_irq, int *vpos, 631ea702333SThomas Zimmermann int *hpos, ktime_t *stime, ktime_t *etime, 632ea702333SThomas Zimmermann const struct drm_display_mode *mode); 633ea702333SThomas Zimmermann 634d38ceaf9SAlex Deucher /* fbdev layer */ 635d38ceaf9SAlex Deucher int amdgpu_fbdev_init(struct amdgpu_device *adev); 636d38ceaf9SAlex Deucher void amdgpu_fbdev_fini(struct amdgpu_device *adev); 637d38ceaf9SAlex Deucher void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 638d38ceaf9SAlex Deucher int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 639d38ceaf9SAlex Deucher bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 640d38ceaf9SAlex Deucher 641d38ceaf9SAlex Deucher int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 642d38ceaf9SAlex Deucher 643d38ceaf9SAlex Deucher /* amdgpu_display.c */ 64450af9193SSamuel Li void amdgpu_display_print_display_setup(struct drm_device *dev); 6453dc9b1ceSSamuel Li int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 646775a8364SSamuel Li int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 647a4eff9aaSDaniel Vetter struct drm_modeset_acquire_ctx *ctx); 6480cd11932SSamuel Li int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 649d38ceaf9SAlex Deucher struct drm_framebuffer *fb, 650d38ceaf9SAlex Deucher struct drm_pending_vblank_event *event, 65141292b1fSDaniel Vetter uint32_t page_flip_flags, uint32_t target, 65241292b1fSDaniel Vetter struct drm_modeset_acquire_ctx *ctx); 653d38ceaf9SAlex Deucher extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 654d38ceaf9SAlex Deucher 655d38ceaf9SAlex Deucher #endif 656