1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_MES_H__
25 #define __AMDGPU_MES_H__
26 
27 #include "amdgpu_irq.h"
28 #include "kgd_kfd_interface.h"
29 #include "amdgpu_gfx.h"
30 #include <linux/sched/mm.h>
31 
32 #define AMDGPU_MES_MAX_COMPUTE_PIPES        8
33 #define AMDGPU_MES_MAX_GFX_PIPES            2
34 #define AMDGPU_MES_MAX_SDMA_PIPES           2
35 
36 #define AMDGPU_MES_API_VERSION_SHIFT	12
37 #define AMDGPU_MES_FEAT_VERSION_SHIFT	24
38 
39 #define AMDGPU_MES_VERSION_MASK		0x00000fff
40 #define AMDGPU_MES_API_VERSION_MASK	0x00fff000
41 #define AMDGPU_MES_FEAT_VERSION_MASK	0xff000000
42 
43 enum amdgpu_mes_priority_level {
44 	AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,
45 	AMDGPU_MES_PRIORITY_LEVEL_NORMAL    = 1,
46 	AMDGPU_MES_PRIORITY_LEVEL_MEDIUM    = 2,
47 	AMDGPU_MES_PRIORITY_LEVEL_HIGH      = 3,
48 	AMDGPU_MES_PRIORITY_LEVEL_REALTIME  = 4,
49 	AMDGPU_MES_PRIORITY_NUM_LEVELS
50 };
51 
52 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
53 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
54 
55 struct amdgpu_mes_funcs;
56 
57 enum admgpu_mes_pipe {
58 	AMDGPU_MES_SCHED_PIPE = 0,
59 	AMDGPU_MES_KIQ_PIPE,
60 	AMDGPU_MAX_MES_PIPES = 2,
61 };
62 
63 struct amdgpu_mes {
64 	struct amdgpu_device            *adev;
65 
66 	struct mutex                    mutex_hidden;
67 
68 	struct idr                      pasid_idr;
69 	struct idr                      gang_id_idr;
70 	struct idr                      queue_id_idr;
71 	struct ida                      doorbell_ida;
72 
73 	spinlock_t                      queue_id_lock;
74 
75 	uint32_t			sched_version;
76 	uint32_t			kiq_version;
77 
78 	uint32_t                        total_max_queue;
79 	uint32_t                        doorbell_id_offset;
80 	uint32_t                        max_doorbell_slices;
81 
82 	uint64_t                        default_process_quantum;
83 	uint64_t                        default_gang_quantum;
84 
85 	struct amdgpu_ring              ring;
86 	spinlock_t                      ring_lock;
87 
88 	const struct firmware           *fw[AMDGPU_MAX_MES_PIPES];
89 
90 	/* mes ucode */
91 	struct amdgpu_bo		*ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
92 	uint64_t			ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
93 	uint32_t			*ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
94 	uint64_t                        uc_start_addr[AMDGPU_MAX_MES_PIPES];
95 
96 	/* mes ucode data */
97 	struct amdgpu_bo		*data_fw_obj[AMDGPU_MAX_MES_PIPES];
98 	uint64_t			data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
99 	uint32_t			*data_fw_ptr[AMDGPU_MAX_MES_PIPES];
100 	uint64_t                        data_start_addr[AMDGPU_MAX_MES_PIPES];
101 
102 	/* eop gpu obj */
103 	struct amdgpu_bo		*eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
104 	uint64_t                        eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
105 
106 	void                            *mqd_backup[AMDGPU_MAX_MES_PIPES];
107 	struct amdgpu_irq_src	        irq[AMDGPU_MAX_MES_PIPES];
108 
109 	uint32_t                        vmid_mask_gfxhub;
110 	uint32_t                        vmid_mask_mmhub;
111 	uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
112 	uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
113 	uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
114 	uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
115 	uint32_t                        sch_ctx_offs;
116 	uint64_t			sch_ctx_gpu_addr;
117 	uint64_t			*sch_ctx_ptr;
118 	uint32_t			query_status_fence_offs;
119 	uint64_t			query_status_fence_gpu_addr;
120 	uint64_t			*query_status_fence_ptr;
121 	uint32_t                        read_val_offs;
122 	uint64_t			read_val_gpu_addr;
123 	uint32_t			*read_val_ptr;
124 
125 	uint32_t			saved_flags;
126 
127 	/* initialize kiq pipe */
128 	int                             (*kiq_hw_init)(struct amdgpu_device *adev);
129 	int                             (*kiq_hw_fini)(struct amdgpu_device *adev);
130 
131 	/* ip specific functions */
132 	const struct amdgpu_mes_funcs   *funcs;
133 };
134 
135 struct amdgpu_mes_process {
136 	int			pasid;
137 	struct			amdgpu_vm *vm;
138 	uint64_t		pd_gpu_addr;
139 	struct amdgpu_bo 	*proc_ctx_bo;
140 	uint64_t 		proc_ctx_gpu_addr;
141 	void 			*proc_ctx_cpu_ptr;
142 	uint64_t 		process_quantum;
143 	struct 			list_head gang_list;
144 	uint32_t 		doorbell_index;
145 	unsigned long 		*doorbell_bitmap;
146 	struct mutex		doorbell_lock;
147 };
148 
149 struct amdgpu_mes_gang {
150 	int 				gang_id;
151 	int 				priority;
152 	int 				inprocess_gang_priority;
153 	int 				global_priority_level;
154 	struct list_head 		list;
155 	struct amdgpu_mes_process 	*process;
156 	struct amdgpu_bo 		*gang_ctx_bo;
157 	uint64_t 			gang_ctx_gpu_addr;
158 	void 				*gang_ctx_cpu_ptr;
159 	uint64_t 			gang_quantum;
160 	struct list_head 		queue_list;
161 };
162 
163 struct amdgpu_mes_queue {
164 	struct list_head 		list;
165 	struct amdgpu_mes_gang 		*gang;
166 	int 				queue_id;
167 	uint64_t 			doorbell_off;
168 	struct amdgpu_bo		*mqd_obj;
169 	void				*mqd_cpu_ptr;
170 	uint64_t 			mqd_gpu_addr;
171 	uint64_t 			wptr_gpu_addr;
172 	int 				queue_type;
173 	int 				paging;
174 	struct amdgpu_ring 		*ring;
175 };
176 
177 struct amdgpu_mes_queue_properties {
178 	int 			queue_type;
179 	uint64_t                hqd_base_gpu_addr;
180 	uint64_t                rptr_gpu_addr;
181 	uint64_t                wptr_gpu_addr;
182 	uint64_t                wptr_mc_addr;
183 	uint32_t                queue_size;
184 	uint64_t                eop_gpu_addr;
185 	uint32_t                hqd_pipe_priority;
186 	uint32_t                hqd_queue_priority;
187 	bool 			paging;
188 	struct amdgpu_ring 	*ring;
189 	/* out */
190 	uint64_t       		doorbell_off;
191 };
192 
193 struct amdgpu_mes_gang_properties {
194 	uint32_t 	priority;
195 	uint32_t 	gang_quantum;
196 	uint32_t 	inprocess_gang_priority;
197 	uint32_t 	priority_level;
198 	int 		global_priority_level;
199 };
200 
201 struct mes_add_queue_input {
202 	uint32_t	process_id;
203 	uint64_t	page_table_base_addr;
204 	uint64_t	process_va_start;
205 	uint64_t	process_va_end;
206 	uint64_t	process_quantum;
207 	uint64_t	process_context_addr;
208 	uint64_t	gang_quantum;
209 	uint64_t	gang_context_addr;
210 	uint32_t	inprocess_gang_priority;
211 	uint32_t	gang_global_priority_level;
212 	uint32_t	doorbell_offset;
213 	uint64_t	mqd_addr;
214 	uint64_t	wptr_addr;
215 	uint64_t	wptr_mc_addr;
216 	uint32_t	queue_type;
217 	uint32_t	paging;
218 	uint32_t        gws_base;
219 	uint32_t        gws_size;
220 	uint64_t	tba_addr;
221 	uint64_t	tma_addr;
222 	uint32_t	is_kfd_process;
223 	uint32_t	is_aql_queue;
224 	uint32_t	queue_size;
225 };
226 
227 struct mes_remove_queue_input {
228 	uint32_t	doorbell_offset;
229 	uint64_t	gang_context_addr;
230 };
231 
232 struct mes_unmap_legacy_queue_input {
233 	enum amdgpu_unmap_queues_action    action;
234 	uint32_t                           queue_type;
235 	uint32_t                           doorbell_offset;
236 	uint32_t                           pipe_id;
237 	uint32_t                           queue_id;
238 	uint64_t                           trail_fence_addr;
239 	uint64_t                           trail_fence_data;
240 };
241 
242 struct mes_suspend_gang_input {
243 	bool		suspend_all_gangs;
244 	uint64_t	gang_context_addr;
245 	uint64_t	suspend_fence_addr;
246 	uint32_t	suspend_fence_value;
247 };
248 
249 struct mes_resume_gang_input {
250 	bool		resume_all_gangs;
251 	uint64_t	gang_context_addr;
252 };
253 
254 enum mes_misc_opcode {
255 	MES_MISC_OP_WRITE_REG,
256 	MES_MISC_OP_READ_REG,
257 	MES_MISC_OP_WRM_REG_WAIT,
258 	MES_MISC_OP_WRM_REG_WR_WAIT,
259 };
260 
261 struct mes_misc_op_input {
262 	enum mes_misc_opcode op;
263 
264 	union {
265 		struct {
266 			uint32_t                  reg_offset;
267 			uint64_t                  buffer_addr;
268 		} read_reg;
269 
270 		struct {
271 			uint32_t                  reg_offset;
272 			uint32_t                  reg_value;
273 		} write_reg;
274 
275 		struct {
276 			uint32_t                   ref;
277 			uint32_t                   mask;
278 			uint32_t                   reg0;
279 			uint32_t                   reg1;
280 		} wrm_reg;
281 	};
282 };
283 
284 struct amdgpu_mes_funcs {
285 	int (*add_hw_queue)(struct amdgpu_mes *mes,
286 			    struct mes_add_queue_input *input);
287 
288 	int (*remove_hw_queue)(struct amdgpu_mes *mes,
289 			       struct mes_remove_queue_input *input);
290 
291 	int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
292 				  struct mes_unmap_legacy_queue_input *input);
293 
294 	int (*suspend_gang)(struct amdgpu_mes *mes,
295 			    struct mes_suspend_gang_input *input);
296 
297 	int (*resume_gang)(struct amdgpu_mes *mes,
298 			   struct mes_resume_gang_input *input);
299 
300 	int (*misc_op)(struct amdgpu_mes *mes,
301 		       struct mes_misc_op_input *input);
302 };
303 
304 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
305 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
306 
307 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
308 
309 int amdgpu_mes_init(struct amdgpu_device *adev);
310 void amdgpu_mes_fini(struct amdgpu_device *adev);
311 
312 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,
313 			      struct amdgpu_vm *vm);
314 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);
315 
316 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,
317 			struct amdgpu_mes_gang_properties *gprops,
318 			int *gang_id);
319 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);
320 
321 int amdgpu_mes_suspend(struct amdgpu_device *adev);
322 int amdgpu_mes_resume(struct amdgpu_device *adev);
323 
324 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
325 			    struct amdgpu_mes_queue_properties *qprops,
326 			    int *queue_id);
327 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
328 
329 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
330 				  struct amdgpu_ring *ring,
331 				  enum amdgpu_unmap_queues_action action,
332 				  u64 gpu_addr, u64 seq);
333 
334 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
335 int amdgpu_mes_wreg(struct amdgpu_device *adev,
336 		    uint32_t reg, uint32_t val);
337 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
338 			uint32_t val, uint32_t mask);
339 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
340 				  uint32_t reg0, uint32_t reg1,
341 				  uint32_t ref, uint32_t mask);
342 
343 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
344 			int queue_type, int idx,
345 			struct amdgpu_mes_ctx_data *ctx_data,
346 			struct amdgpu_ring **out);
347 void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
348 			    struct amdgpu_ring *ring);
349 
350 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
351 						   enum amdgpu_mes_priority_level prio);
352 
353 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
354 				   struct amdgpu_mes_ctx_data *ctx_data);
355 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);
356 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
357 				 struct amdgpu_vm *vm,
358 				 struct amdgpu_mes_ctx_data *ctx_data);
359 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
360 				   struct amdgpu_mes_ctx_data *ctx_data);
361 
362 int amdgpu_mes_self_test(struct amdgpu_device *adev);
363 
364 int amdgpu_mes_alloc_process_doorbells(struct amdgpu_device *adev,
365 					unsigned int *doorbell_index);
366 void amdgpu_mes_free_process_doorbells(struct amdgpu_device *adev,
367 					unsigned int doorbell_index);
368 unsigned int amdgpu_mes_get_doorbell_dw_offset_in_bar(
369 					struct amdgpu_device *adev,
370 					uint32_t doorbell_index,
371 					unsigned int doorbell_id);
372 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
373 
374 /*
375  * MES lock can be taken in MMU notifiers.
376  *
377  * A bit more detail about why to set no-FS reclaim with MES lock:
378  *
379  * The purpose of the MMU notifier is to stop GPU access to memory so
380  * that the Linux VM subsystem can move pages around safely. This is
381  * done by preempting user mode queues for the affected process. When
382  * MES is used, MES lock needs to be taken to preempt the queues.
383  *
384  * The MMU notifier callback entry point in the driver is
385  * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
386  * there is:
387  * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
388  * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
389  *
390  * The last part of the chain is a function pointer where we take the
391  * MES lock.
392  *
393  * The problem with taking locks in the MMU notifier is, that MMU
394  * notifiers can be called in reclaim-FS context. That's where the
395  * kernel frees up pages to make room for new page allocations under
396  * memory pressure. While we are running in reclaim-FS context, we must
397  * not trigger another memory reclaim operation because that would
398  * recursively reenter the reclaim code and cause a deadlock. The
399  * memalloc_nofs_save/restore calls guarantee that.
400  *
401  * In addition we also need to avoid lock dependencies on other locks taken
402  * under the MES lock, for example reservation locks. Here is a possible
403  * scenario of a deadlock:
404  * Thread A: takes and holds reservation lock | triggers reclaim-FS |
405  * MMU notifier | blocks trying to take MES lock
406  * Thread B: takes and holds MES lock | blocks trying to take reservation lock
407  *
408  * In this scenario Thread B gets involved in a deadlock even without
409  * triggering a reclaim-FS operation itself.
410  * To fix this and break the lock dependency chain you'd need to either:
411  * 1. protect reservation locks with memalloc_nofs_save/restore, or
412  * 2. avoid taking reservation locks under the MES lock.
413  *
414  * Reservation locks are taken all over the kernel in different subsystems, we
415  * have no control over them and their lock dependencies.So the only workable
416  * solution is to avoid taking other locks under the MES lock.
417  * As a result, make sure no reclaim-FS happens while holding this lock anywhere
418  * to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
419  */
420 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
421 {
422 	mutex_lock(&mes->mutex_hidden);
423 	mes->saved_flags = memalloc_noreclaim_save();
424 }
425 
426 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
427 {
428 	memalloc_noreclaim_restore(mes->saved_flags);
429 	mutex_unlock(&mes->mutex_hidden);
430 }
431 #endif /* __AMDGPU_MES_H__ */
432