1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include <linux/sched/mm.h> 31 32 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 33 #define AMDGPU_MES_MAX_GFX_PIPES 2 34 #define AMDGPU_MES_MAX_SDMA_PIPES 2 35 36 #define AMDGPU_MES_API_VERSION_SHIFT 12 37 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 38 39 #define AMDGPU_MES_VERSION_MASK 0x00000fff 40 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 41 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 42 43 enum amdgpu_mes_priority_level { 44 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 45 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 46 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 47 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 48 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 49 AMDGPU_MES_PRIORITY_NUM_LEVELS 50 }; 51 52 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 53 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 54 55 struct amdgpu_mes_funcs; 56 57 enum admgpu_mes_pipe { 58 AMDGPU_MES_SCHED_PIPE = 0, 59 AMDGPU_MES_KIQ_PIPE, 60 AMDGPU_MAX_MES_PIPES = 2, 61 }; 62 63 struct amdgpu_mes { 64 struct amdgpu_device *adev; 65 66 struct mutex mutex_hidden; 67 68 struct idr pasid_idr; 69 struct idr gang_id_idr; 70 struct idr queue_id_idr; 71 struct ida doorbell_ida; 72 73 spinlock_t queue_id_lock; 74 75 uint32_t sched_version; 76 uint32_t kiq_version; 77 78 uint32_t total_max_queue; 79 uint32_t doorbell_id_offset; 80 uint32_t max_doorbell_slices; 81 82 uint64_t default_process_quantum; 83 uint64_t default_gang_quantum; 84 85 struct amdgpu_ring ring; 86 87 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 88 89 /* mes ucode */ 90 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 91 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 92 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 93 uint32_t ucode_fw_version[AMDGPU_MAX_MES_PIPES]; 94 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 95 96 /* mes ucode data */ 97 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 98 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 99 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 100 uint32_t data_fw_version[AMDGPU_MAX_MES_PIPES]; 101 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 102 103 /* eop gpu obj */ 104 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 105 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 106 107 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 108 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 109 110 uint32_t vmid_mask_gfxhub; 111 uint32_t vmid_mask_mmhub; 112 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 113 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 114 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 115 uint32_t agreegated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 116 uint32_t sch_ctx_offs; 117 uint64_t sch_ctx_gpu_addr; 118 uint64_t *sch_ctx_ptr; 119 uint32_t query_status_fence_offs; 120 uint64_t query_status_fence_gpu_addr; 121 uint64_t *query_status_fence_ptr; 122 uint32_t read_val_offs; 123 uint64_t read_val_gpu_addr; 124 uint32_t *read_val_ptr; 125 126 uint32_t saved_flags; 127 128 /* initialize kiq pipe */ 129 int (*kiq_hw_init)(struct amdgpu_device *adev); 130 int (*kiq_hw_fini)(struct amdgpu_device *adev); 131 132 /* ip specific functions */ 133 const struct amdgpu_mes_funcs *funcs; 134 }; 135 136 struct amdgpu_mes_process { 137 int pasid; 138 struct amdgpu_vm *vm; 139 uint64_t pd_gpu_addr; 140 struct amdgpu_bo *proc_ctx_bo; 141 uint64_t proc_ctx_gpu_addr; 142 void *proc_ctx_cpu_ptr; 143 uint64_t process_quantum; 144 struct list_head gang_list; 145 uint32_t doorbell_index; 146 unsigned long *doorbell_bitmap; 147 struct mutex doorbell_lock; 148 }; 149 150 struct amdgpu_mes_gang { 151 int gang_id; 152 int priority; 153 int inprocess_gang_priority; 154 int global_priority_level; 155 struct list_head list; 156 struct amdgpu_mes_process *process; 157 struct amdgpu_bo *gang_ctx_bo; 158 uint64_t gang_ctx_gpu_addr; 159 void *gang_ctx_cpu_ptr; 160 uint64_t gang_quantum; 161 struct list_head queue_list; 162 }; 163 164 struct amdgpu_mes_queue { 165 struct list_head list; 166 struct amdgpu_mes_gang *gang; 167 int queue_id; 168 uint64_t doorbell_off; 169 struct amdgpu_bo *mqd_obj; 170 void *mqd_cpu_ptr; 171 uint64_t mqd_gpu_addr; 172 uint64_t wptr_gpu_addr; 173 int queue_type; 174 int paging; 175 struct amdgpu_ring *ring; 176 }; 177 178 struct amdgpu_mes_queue_properties { 179 int queue_type; 180 uint64_t hqd_base_gpu_addr; 181 uint64_t rptr_gpu_addr; 182 uint64_t wptr_gpu_addr; 183 uint64_t wptr_mc_addr; 184 uint32_t queue_size; 185 uint64_t eop_gpu_addr; 186 uint32_t hqd_pipe_priority; 187 uint32_t hqd_queue_priority; 188 bool paging; 189 struct amdgpu_ring *ring; 190 /* out */ 191 uint64_t doorbell_off; 192 }; 193 194 struct amdgpu_mes_gang_properties { 195 uint32_t priority; 196 uint32_t gang_quantum; 197 uint32_t inprocess_gang_priority; 198 uint32_t priority_level; 199 int global_priority_level; 200 }; 201 202 struct mes_add_queue_input { 203 uint32_t process_id; 204 uint64_t page_table_base_addr; 205 uint64_t process_va_start; 206 uint64_t process_va_end; 207 uint64_t process_quantum; 208 uint64_t process_context_addr; 209 uint64_t gang_quantum; 210 uint64_t gang_context_addr; 211 uint32_t inprocess_gang_priority; 212 uint32_t gang_global_priority_level; 213 uint32_t doorbell_offset; 214 uint64_t mqd_addr; 215 uint64_t wptr_addr; 216 uint64_t wptr_mc_addr; 217 uint32_t queue_type; 218 uint32_t paging; 219 uint32_t gws_base; 220 uint32_t gws_size; 221 uint64_t tba_addr; 222 uint64_t tma_addr; 223 uint32_t is_kfd_process; 224 }; 225 226 struct mes_remove_queue_input { 227 uint32_t doorbell_offset; 228 uint64_t gang_context_addr; 229 }; 230 231 struct mes_unmap_legacy_queue_input { 232 enum amdgpu_unmap_queues_action action; 233 uint32_t queue_type; 234 uint32_t doorbell_offset; 235 uint32_t pipe_id; 236 uint32_t queue_id; 237 uint64_t trail_fence_addr; 238 uint64_t trail_fence_data; 239 }; 240 241 struct mes_suspend_gang_input { 242 bool suspend_all_gangs; 243 uint64_t gang_context_addr; 244 uint64_t suspend_fence_addr; 245 uint32_t suspend_fence_value; 246 }; 247 248 struct mes_resume_gang_input { 249 bool resume_all_gangs; 250 uint64_t gang_context_addr; 251 }; 252 253 enum mes_misc_opcode { 254 MES_MISC_OP_WRITE_REG, 255 MES_MISC_OP_READ_REG, 256 MES_MISC_OP_WRM_REG_WAIT, 257 MES_MISC_OP_WRM_REG_WR_WAIT, 258 }; 259 260 struct mes_misc_op_input { 261 enum mes_misc_opcode op; 262 263 union { 264 struct { 265 uint32_t reg_offset; 266 uint64_t buffer_addr; 267 } read_reg; 268 269 struct { 270 uint32_t reg_offset; 271 uint32_t reg_value; 272 } write_reg; 273 274 struct { 275 uint32_t ref; 276 uint32_t mask; 277 uint32_t reg0; 278 uint32_t reg1; 279 } wrm_reg; 280 }; 281 }; 282 283 struct amdgpu_mes_funcs { 284 int (*add_hw_queue)(struct amdgpu_mes *mes, 285 struct mes_add_queue_input *input); 286 287 int (*remove_hw_queue)(struct amdgpu_mes *mes, 288 struct mes_remove_queue_input *input); 289 290 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 291 struct mes_unmap_legacy_queue_input *input); 292 293 int (*suspend_gang)(struct amdgpu_mes *mes, 294 struct mes_suspend_gang_input *input); 295 296 int (*resume_gang)(struct amdgpu_mes *mes, 297 struct mes_resume_gang_input *input); 298 299 int (*misc_op)(struct amdgpu_mes *mes, 300 struct mes_misc_op_input *input); 301 }; 302 303 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 304 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 305 306 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 307 308 int amdgpu_mes_init(struct amdgpu_device *adev); 309 void amdgpu_mes_fini(struct amdgpu_device *adev); 310 311 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 312 struct amdgpu_vm *vm); 313 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 314 315 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 316 struct amdgpu_mes_gang_properties *gprops, 317 int *gang_id); 318 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 319 320 int amdgpu_mes_suspend(struct amdgpu_device *adev); 321 int amdgpu_mes_resume(struct amdgpu_device *adev); 322 323 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 324 struct amdgpu_mes_queue_properties *qprops, 325 int *queue_id); 326 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 327 328 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 329 struct amdgpu_ring *ring, 330 enum amdgpu_unmap_queues_action action, 331 u64 gpu_addr, u64 seq); 332 333 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 334 int amdgpu_mes_wreg(struct amdgpu_device *adev, 335 uint32_t reg, uint32_t val); 336 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 337 uint32_t val, uint32_t mask); 338 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 339 uint32_t reg0, uint32_t reg1, 340 uint32_t ref, uint32_t mask); 341 342 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 343 int queue_type, int idx, 344 struct amdgpu_mes_ctx_data *ctx_data, 345 struct amdgpu_ring **out); 346 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 347 struct amdgpu_ring *ring); 348 349 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 350 struct amdgpu_mes_ctx_data *ctx_data); 351 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 352 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 353 struct amdgpu_vm *vm, 354 struct amdgpu_mes_ctx_data *ctx_data); 355 356 int amdgpu_mes_self_test(struct amdgpu_device *adev); 357 358 int amdgpu_mes_alloc_process_doorbells(struct amdgpu_device *adev, 359 unsigned int *doorbell_index); 360 void amdgpu_mes_free_process_doorbells(struct amdgpu_device *adev, 361 unsigned int doorbell_index); 362 unsigned int amdgpu_mes_get_doorbell_dw_offset_in_bar( 363 struct amdgpu_device *adev, 364 uint32_t doorbell_index, 365 unsigned int doorbell_id); 366 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 367 368 /* 369 * MES lock can be taken in MMU notifiers. 370 * 371 * A bit more detail about why to set no-FS reclaim with MES lock: 372 * 373 * The purpose of the MMU notifier is to stop GPU access to memory so 374 * that the Linux VM subsystem can move pages around safely. This is 375 * done by preempting user mode queues for the affected process. When 376 * MES is used, MES lock needs to be taken to preempt the queues. 377 * 378 * The MMU notifier callback entry point in the driver is 379 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 380 * there is: 381 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 382 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 383 * 384 * The last part of the chain is a function pointer where we take the 385 * MES lock. 386 * 387 * The problem with taking locks in the MMU notifier is, that MMU 388 * notifiers can be called in reclaim-FS context. That's where the 389 * kernel frees up pages to make room for new page allocations under 390 * memory pressure. While we are running in reclaim-FS context, we must 391 * not trigger another memory reclaim operation because that would 392 * recursively reenter the reclaim code and cause a deadlock. The 393 * memalloc_nofs_save/restore calls guarantee that. 394 * 395 * In addition we also need to avoid lock dependencies on other locks taken 396 * under the MES lock, for example reservation locks. Here is a possible 397 * scenario of a deadlock: 398 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 399 * MMU notifier | blocks trying to take MES lock 400 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 401 * 402 * In this scenario Thread B gets involved in a deadlock even without 403 * triggering a reclaim-FS operation itself. 404 * To fix this and break the lock dependency chain you'd need to either: 405 * 1. protect reservation locks with memalloc_nofs_save/restore, or 406 * 2. avoid taking reservation locks under the MES lock. 407 * 408 * Reservation locks are taken all over the kernel in different subsystems, we 409 * have no control over them and their lock dependencies.So the only workable 410 * solution is to avoid taking other locks under the MES lock. 411 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 412 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 413 */ 414 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 415 { 416 mutex_lock(&mes->mutex_hidden); 417 mes->saved_flags = memalloc_noreclaim_save(); 418 } 419 420 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 421 { 422 memalloc_noreclaim_restore(mes->saved_flags); 423 mutex_unlock(&mes->mutex_hidden); 424 } 425 #endif /* __AMDGPU_MES_H__ */ 426