1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 struct amdgpu_mes_funcs; 28 29 struct amdgpu_mes { 30 struct amdgpu_adev *adev; 31 32 const struct firmware *fw; 33 34 /* mes ucode */ 35 struct amdgpu_bo *ucode_fw_obj; 36 uint64_t ucode_fw_gpu_addr; 37 uint32_t *ucode_fw_ptr; 38 uint32_t ucode_fw_version; 39 uint64_t uc_start_addr; 40 41 /* mes ucode data */ 42 struct amdgpu_bo *data_fw_obj; 43 uint64_t data_fw_gpu_addr; 44 uint32_t *data_fw_ptr; 45 uint32_t data_fw_version; 46 uint64_t data_start_addr; 47 48 /* ip specific functions */ 49 struct amdgpu_mes_funcs *funcs; 50 }; 51 52 struct mes_add_queue_input { 53 uint32_t process_id; 54 uint64_t page_table_base_addr; 55 uint64_t process_va_start; 56 uint64_t process_va_end; 57 uint64_t process_quantum; 58 uint64_t process_context_addr; 59 uint64_t gang_quantum; 60 uint64_t gang_context_addr; 61 uint32_t inprocess_gang_priority; 62 uint32_t gang_global_priority_level; 63 uint32_t doorbell_offset; 64 uint64_t mqd_addr; 65 uint64_t wptr_addr; 66 uint32_t queue_type; 67 uint32_t paging; 68 }; 69 70 struct mes_remove_queue_input { 71 uint32_t doorbell_offset; 72 uint64_t gang_context_addr; 73 }; 74 75 struct mes_suspend_gang_input { 76 bool suspend_all_gangs; 77 uint64_t gang_context_addr; 78 uint64_t suspend_fence_addr; 79 uint32_t suspend_fence_value; 80 }; 81 82 struct mes_resume_gang_input { 83 bool resume_all_gangs; 84 uint64_t gang_context_addr; 85 }; 86 87 struct amdgpu_mes_funcs { 88 int (*add_hw_queue)(struct amdgpu_mes *mes, 89 struct mes_add_queue_input *input); 90 91 int (*remove_hw_queue)(struct amdgpu_mes *mes, 92 struct mes_remove_queue_input *input); 93 94 int (*suspend_gang)(struct amdgpu_mes *mes, 95 struct mes_suspend_gang_input *input); 96 97 int (*resume_gang)(struct amdgpu_mes *mes, 98 struct mes_resume_gang_input *input); 99 }; 100 101 #endif /* __AMDGPU_MES_H__ */ 102