1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = dev->dev_private; 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 goto done_free; 90 91 if (adev->runpm) { 92 pm_runtime_get_sync(dev->dev); 93 pm_runtime_forbid(dev->dev); 94 } 95 96 amdgpu_acpi_fini(adev); 97 98 amdgpu_device_fini(adev); 99 100 done_free: 101 kfree(adev); 102 dev->dev_private = NULL; 103 } 104 105 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 106 { 107 struct amdgpu_gpu_instance *gpu_instance; 108 109 mutex_lock(&mgpu_info.mutex); 110 111 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 112 DRM_ERROR("Cannot register more gpu instance\n"); 113 mutex_unlock(&mgpu_info.mutex); 114 return; 115 } 116 117 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 118 gpu_instance->adev = adev; 119 gpu_instance->mgpu_fan_enabled = 0; 120 121 mgpu_info.num_gpu++; 122 if (adev->flags & AMD_IS_APU) 123 mgpu_info.num_apu++; 124 else 125 mgpu_info.num_dgpu++; 126 127 mutex_unlock(&mgpu_info.mutex); 128 } 129 130 /** 131 * amdgpu_driver_load_kms - Main load function for KMS. 132 * 133 * @dev: drm dev pointer 134 * @flags: device flags 135 * 136 * This is the main load function for KMS (all asics). 137 * Returns 0 on success, error on failure. 138 */ 139 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 140 { 141 struct amdgpu_device *adev; 142 int r, acpi_status; 143 144 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 145 if (adev == NULL) { 146 return -ENOMEM; 147 } 148 dev->dev_private = (void *)adev; 149 150 if (amdgpu_has_atpx() && 151 (amdgpu_is_atpx_hybrid() || 152 amdgpu_has_atpx_dgpu_power_cntl()) && 153 ((flags & AMD_IS_APU) == 0) && 154 !pci_is_thunderbolt_attached(dev->pdev)) 155 flags |= AMD_IS_PX; 156 157 /* amdgpu_device_init should report only fatal error 158 * like memory allocation failure or iomapping failure, 159 * or memory manager initialization failure, it must 160 * properly initialize the GPU MC controller and permit 161 * VRAM allocation 162 */ 163 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 164 if (r) { 165 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 166 goto out; 167 } 168 169 if (amdgpu_device_supports_boco(dev) && 170 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 171 adev->runpm = true; 172 } else if (amdgpu_device_supports_baco(dev) && 173 (amdgpu_runtime_pm != 0)) { 174 switch (adev->asic_type) { 175 #ifdef CONFIG_DRM_AMDGPU_CIK 176 case CHIP_BONAIRE: 177 case CHIP_HAWAII: 178 #endif 179 case CHIP_VEGA20: 180 case CHIP_ARCTURUS: 181 case CHIP_SIENNA_CICHLID: 182 case CHIP_NAVY_FLOUNDER: 183 /* enable runpm if runpm=1 */ 184 if (amdgpu_runtime_pm > 0) 185 adev->runpm = true; 186 break; 187 case CHIP_VEGA10: 188 /* turn runpm on if noretry=0 */ 189 if (!amdgpu_noretry) 190 adev->runpm = true; 191 break; 192 default: 193 /* enable runpm on VI+ */ 194 adev->runpm = true; 195 break; 196 } 197 } 198 199 /* Call ACPI methods: require modeset init 200 * but failure is not fatal 201 */ 202 203 acpi_status = amdgpu_acpi_init(adev); 204 if (acpi_status) 205 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 206 207 if (adev->runpm) { 208 /* only need to skip on ATPX */ 209 if (amdgpu_device_supports_boco(dev) && 210 !amdgpu_is_atpx_hybrid()) 211 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 212 pm_runtime_use_autosuspend(dev->dev); 213 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 214 pm_runtime_allow(dev->dev); 215 pm_runtime_mark_last_busy(dev->dev); 216 pm_runtime_put_autosuspend(dev->dev); 217 } 218 219 out: 220 if (r) { 221 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 222 if (adev->rmmio && adev->runpm) 223 pm_runtime_put_noidle(dev->dev); 224 amdgpu_driver_unload_kms(dev); 225 } 226 227 return r; 228 } 229 230 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 231 struct drm_amdgpu_query_fw *query_fw, 232 struct amdgpu_device *adev) 233 { 234 switch (query_fw->fw_type) { 235 case AMDGPU_INFO_FW_VCE: 236 fw_info->ver = adev->vce.fw_version; 237 fw_info->feature = adev->vce.fb_version; 238 break; 239 case AMDGPU_INFO_FW_UVD: 240 fw_info->ver = adev->uvd.fw_version; 241 fw_info->feature = 0; 242 break; 243 case AMDGPU_INFO_FW_VCN: 244 fw_info->ver = adev->vcn.fw_version; 245 fw_info->feature = 0; 246 break; 247 case AMDGPU_INFO_FW_GMC: 248 fw_info->ver = adev->gmc.fw_version; 249 fw_info->feature = 0; 250 break; 251 case AMDGPU_INFO_FW_GFX_ME: 252 fw_info->ver = adev->gfx.me_fw_version; 253 fw_info->feature = adev->gfx.me_feature_version; 254 break; 255 case AMDGPU_INFO_FW_GFX_PFP: 256 fw_info->ver = adev->gfx.pfp_fw_version; 257 fw_info->feature = adev->gfx.pfp_feature_version; 258 break; 259 case AMDGPU_INFO_FW_GFX_CE: 260 fw_info->ver = adev->gfx.ce_fw_version; 261 fw_info->feature = adev->gfx.ce_feature_version; 262 break; 263 case AMDGPU_INFO_FW_GFX_RLC: 264 fw_info->ver = adev->gfx.rlc_fw_version; 265 fw_info->feature = adev->gfx.rlc_feature_version; 266 break; 267 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 268 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 269 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 270 break; 271 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 272 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 273 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 274 break; 275 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 276 fw_info->ver = adev->gfx.rlc_srls_fw_version; 277 fw_info->feature = adev->gfx.rlc_srls_feature_version; 278 break; 279 case AMDGPU_INFO_FW_GFX_MEC: 280 if (query_fw->index == 0) { 281 fw_info->ver = adev->gfx.mec_fw_version; 282 fw_info->feature = adev->gfx.mec_feature_version; 283 } else if (query_fw->index == 1) { 284 fw_info->ver = adev->gfx.mec2_fw_version; 285 fw_info->feature = adev->gfx.mec2_feature_version; 286 } else 287 return -EINVAL; 288 break; 289 case AMDGPU_INFO_FW_SMC: 290 fw_info->ver = adev->pm.fw_version; 291 fw_info->feature = 0; 292 break; 293 case AMDGPU_INFO_FW_TA: 294 if (query_fw->index > 1) 295 return -EINVAL; 296 if (query_fw->index == 0) { 297 fw_info->ver = adev->psp.ta_fw_version; 298 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 299 } else { 300 fw_info->ver = adev->psp.ta_fw_version; 301 fw_info->feature = adev->psp.ta_ras_ucode_version; 302 } 303 break; 304 case AMDGPU_INFO_FW_SDMA: 305 if (query_fw->index >= adev->sdma.num_instances) 306 return -EINVAL; 307 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 308 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 309 break; 310 case AMDGPU_INFO_FW_SOS: 311 fw_info->ver = adev->psp.sos_fw_version; 312 fw_info->feature = adev->psp.sos_feature_version; 313 break; 314 case AMDGPU_INFO_FW_ASD: 315 fw_info->ver = adev->psp.asd_fw_version; 316 fw_info->feature = adev->psp.asd_feature_version; 317 break; 318 case AMDGPU_INFO_FW_DMCU: 319 fw_info->ver = adev->dm.dmcu_fw_version; 320 fw_info->feature = 0; 321 break; 322 case AMDGPU_INFO_FW_DMCUB: 323 fw_info->ver = adev->dm.dmcub_fw_version; 324 fw_info->feature = 0; 325 break; 326 default: 327 return -EINVAL; 328 } 329 return 0; 330 } 331 332 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 333 struct drm_amdgpu_info *info, 334 struct drm_amdgpu_info_hw_ip *result) 335 { 336 uint32_t ib_start_alignment = 0; 337 uint32_t ib_size_alignment = 0; 338 enum amd_ip_block_type type; 339 unsigned int num_rings = 0; 340 unsigned int i, j; 341 342 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 343 return -EINVAL; 344 345 switch (info->query_hw_ip.type) { 346 case AMDGPU_HW_IP_GFX: 347 type = AMD_IP_BLOCK_TYPE_GFX; 348 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 349 if (adev->gfx.gfx_ring[i].sched.ready) 350 ++num_rings; 351 ib_start_alignment = 32; 352 ib_size_alignment = 32; 353 break; 354 case AMDGPU_HW_IP_COMPUTE: 355 type = AMD_IP_BLOCK_TYPE_GFX; 356 for (i = 0; i < adev->gfx.num_compute_rings; i++) 357 if (adev->gfx.compute_ring[i].sched.ready) 358 ++num_rings; 359 ib_start_alignment = 32; 360 ib_size_alignment = 32; 361 break; 362 case AMDGPU_HW_IP_DMA: 363 type = AMD_IP_BLOCK_TYPE_SDMA; 364 for (i = 0; i < adev->sdma.num_instances; i++) 365 if (adev->sdma.instance[i].ring.sched.ready) 366 ++num_rings; 367 ib_start_alignment = 256; 368 ib_size_alignment = 4; 369 break; 370 case AMDGPU_HW_IP_UVD: 371 type = AMD_IP_BLOCK_TYPE_UVD; 372 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 373 if (adev->uvd.harvest_config & (1 << i)) 374 continue; 375 376 if (adev->uvd.inst[i].ring.sched.ready) 377 ++num_rings; 378 } 379 ib_start_alignment = 64; 380 ib_size_alignment = 64; 381 break; 382 case AMDGPU_HW_IP_VCE: 383 type = AMD_IP_BLOCK_TYPE_VCE; 384 for (i = 0; i < adev->vce.num_rings; i++) 385 if (adev->vce.ring[i].sched.ready) 386 ++num_rings; 387 ib_start_alignment = 4; 388 ib_size_alignment = 1; 389 break; 390 case AMDGPU_HW_IP_UVD_ENC: 391 type = AMD_IP_BLOCK_TYPE_UVD; 392 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 393 if (adev->uvd.harvest_config & (1 << i)) 394 continue; 395 396 for (j = 0; j < adev->uvd.num_enc_rings; j++) 397 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 398 ++num_rings; 399 } 400 ib_start_alignment = 64; 401 ib_size_alignment = 64; 402 break; 403 case AMDGPU_HW_IP_VCN_DEC: 404 type = AMD_IP_BLOCK_TYPE_VCN; 405 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 406 if (adev->uvd.harvest_config & (1 << i)) 407 continue; 408 409 if (adev->vcn.inst[i].ring_dec.sched.ready) 410 ++num_rings; 411 } 412 ib_start_alignment = 16; 413 ib_size_alignment = 16; 414 break; 415 case AMDGPU_HW_IP_VCN_ENC: 416 type = AMD_IP_BLOCK_TYPE_VCN; 417 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 418 if (adev->uvd.harvest_config & (1 << i)) 419 continue; 420 421 for (j = 0; j < adev->vcn.num_enc_rings; j++) 422 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 423 ++num_rings; 424 } 425 ib_start_alignment = 64; 426 ib_size_alignment = 1; 427 break; 428 case AMDGPU_HW_IP_VCN_JPEG: 429 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 430 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 431 432 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 433 if (adev->jpeg.harvest_config & (1 << i)) 434 continue; 435 436 if (adev->jpeg.inst[i].ring_dec.sched.ready) 437 ++num_rings; 438 } 439 ib_start_alignment = 16; 440 ib_size_alignment = 16; 441 break; 442 default: 443 return -EINVAL; 444 } 445 446 for (i = 0; i < adev->num_ip_blocks; i++) 447 if (adev->ip_blocks[i].version->type == type && 448 adev->ip_blocks[i].status.valid) 449 break; 450 451 if (i == adev->num_ip_blocks) 452 return 0; 453 454 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 455 num_rings); 456 457 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 458 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 459 result->capabilities_flags = 0; 460 result->available_rings = (1 << num_rings) - 1; 461 result->ib_start_alignment = ib_start_alignment; 462 result->ib_size_alignment = ib_size_alignment; 463 return 0; 464 } 465 466 /* 467 * Userspace get information ioctl 468 */ 469 /** 470 * amdgpu_info_ioctl - answer a device specific request. 471 * 472 * @adev: amdgpu device pointer 473 * @data: request object 474 * @filp: drm filp 475 * 476 * This function is used to pass device specific parameters to the userspace 477 * drivers. Examples include: pci device id, pipeline parms, tiling params, 478 * etc. (all asics). 479 * Returns 0 on success, -EINVAL on failure. 480 */ 481 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 482 { 483 struct amdgpu_device *adev = dev->dev_private; 484 struct drm_amdgpu_info *info = data; 485 struct amdgpu_mode_info *minfo = &adev->mode_info; 486 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 487 uint32_t size = info->return_size; 488 struct drm_crtc *crtc; 489 uint32_t ui32 = 0; 490 uint64_t ui64 = 0; 491 int i, found; 492 int ui32_size = sizeof(ui32); 493 494 if (!info->return_size || !info->return_pointer) 495 return -EINVAL; 496 497 switch (info->query) { 498 case AMDGPU_INFO_ACCEL_WORKING: 499 ui32 = adev->accel_working; 500 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 501 case AMDGPU_INFO_CRTC_FROM_ID: 502 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 503 crtc = (struct drm_crtc *)minfo->crtcs[i]; 504 if (crtc && crtc->base.id == info->mode_crtc.id) { 505 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 506 ui32 = amdgpu_crtc->crtc_id; 507 found = 1; 508 break; 509 } 510 } 511 if (!found) { 512 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 513 return -EINVAL; 514 } 515 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 516 case AMDGPU_INFO_HW_IP_INFO: { 517 struct drm_amdgpu_info_hw_ip ip = {}; 518 int ret; 519 520 ret = amdgpu_hw_ip_info(adev, info, &ip); 521 if (ret) 522 return ret; 523 524 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 525 return ret ? -EFAULT : 0; 526 } 527 case AMDGPU_INFO_HW_IP_COUNT: { 528 enum amd_ip_block_type type; 529 uint32_t count = 0; 530 531 switch (info->query_hw_ip.type) { 532 case AMDGPU_HW_IP_GFX: 533 type = AMD_IP_BLOCK_TYPE_GFX; 534 break; 535 case AMDGPU_HW_IP_COMPUTE: 536 type = AMD_IP_BLOCK_TYPE_GFX; 537 break; 538 case AMDGPU_HW_IP_DMA: 539 type = AMD_IP_BLOCK_TYPE_SDMA; 540 break; 541 case AMDGPU_HW_IP_UVD: 542 type = AMD_IP_BLOCK_TYPE_UVD; 543 break; 544 case AMDGPU_HW_IP_VCE: 545 type = AMD_IP_BLOCK_TYPE_VCE; 546 break; 547 case AMDGPU_HW_IP_UVD_ENC: 548 type = AMD_IP_BLOCK_TYPE_UVD; 549 break; 550 case AMDGPU_HW_IP_VCN_DEC: 551 case AMDGPU_HW_IP_VCN_ENC: 552 type = AMD_IP_BLOCK_TYPE_VCN; 553 break; 554 case AMDGPU_HW_IP_VCN_JPEG: 555 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 556 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 557 break; 558 default: 559 return -EINVAL; 560 } 561 562 for (i = 0; i < adev->num_ip_blocks; i++) 563 if (adev->ip_blocks[i].version->type == type && 564 adev->ip_blocks[i].status.valid && 565 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 566 count++; 567 568 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 569 } 570 case AMDGPU_INFO_TIMESTAMP: 571 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 572 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 573 case AMDGPU_INFO_FW_VERSION: { 574 struct drm_amdgpu_info_firmware fw_info; 575 int ret; 576 577 /* We only support one instance of each IP block right now. */ 578 if (info->query_fw.ip_instance != 0) 579 return -EINVAL; 580 581 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 582 if (ret) 583 return ret; 584 585 return copy_to_user(out, &fw_info, 586 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 587 } 588 case AMDGPU_INFO_NUM_BYTES_MOVED: 589 ui64 = atomic64_read(&adev->num_bytes_moved); 590 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 591 case AMDGPU_INFO_NUM_EVICTIONS: 592 ui64 = atomic64_read(&adev->num_evictions); 593 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 594 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 595 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 596 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 597 case AMDGPU_INFO_VRAM_USAGE: 598 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 599 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 600 case AMDGPU_INFO_VIS_VRAM_USAGE: 601 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 603 case AMDGPU_INFO_GTT_USAGE: 604 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 606 case AMDGPU_INFO_GDS_CONFIG: { 607 struct drm_amdgpu_info_gds gds_info; 608 609 memset(&gds_info, 0, sizeof(gds_info)); 610 gds_info.compute_partition_size = adev->gds.gds_size; 611 gds_info.gds_total_size = adev->gds.gds_size; 612 gds_info.gws_per_compute_partition = adev->gds.gws_size; 613 gds_info.oa_per_compute_partition = adev->gds.oa_size; 614 return copy_to_user(out, &gds_info, 615 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 616 } 617 case AMDGPU_INFO_VRAM_GTT: { 618 struct drm_amdgpu_info_vram_gtt vram_gtt; 619 620 vram_gtt.vram_size = adev->gmc.real_vram_size - 621 atomic64_read(&adev->vram_pin_size) - 622 AMDGPU_VM_RESERVED_VRAM; 623 vram_gtt.vram_cpu_accessible_size = 624 min(adev->gmc.visible_vram_size - 625 atomic64_read(&adev->visible_pin_size), 626 vram_gtt.vram_size); 627 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 628 vram_gtt.gtt_size *= PAGE_SIZE; 629 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 630 return copy_to_user(out, &vram_gtt, 631 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 632 } 633 case AMDGPU_INFO_MEMORY: { 634 struct drm_amdgpu_memory_info mem; 635 636 memset(&mem, 0, sizeof(mem)); 637 mem.vram.total_heap_size = adev->gmc.real_vram_size; 638 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 639 atomic64_read(&adev->vram_pin_size) - 640 AMDGPU_VM_RESERVED_VRAM; 641 mem.vram.heap_usage = 642 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 643 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 644 645 mem.cpu_accessible_vram.total_heap_size = 646 adev->gmc.visible_vram_size; 647 mem.cpu_accessible_vram.usable_heap_size = 648 min(adev->gmc.visible_vram_size - 649 atomic64_read(&adev->visible_pin_size), 650 mem.vram.usable_heap_size); 651 mem.cpu_accessible_vram.heap_usage = 652 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 653 mem.cpu_accessible_vram.max_allocation = 654 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 655 656 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 657 mem.gtt.total_heap_size *= PAGE_SIZE; 658 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 659 atomic64_read(&adev->gart_pin_size); 660 mem.gtt.heap_usage = 661 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 662 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 663 664 return copy_to_user(out, &mem, 665 min((size_t)size, sizeof(mem))) 666 ? -EFAULT : 0; 667 } 668 case AMDGPU_INFO_READ_MMR_REG: { 669 unsigned n, alloc_size; 670 uint32_t *regs; 671 unsigned se_num = (info->read_mmr_reg.instance >> 672 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 673 AMDGPU_INFO_MMR_SE_INDEX_MASK; 674 unsigned sh_num = (info->read_mmr_reg.instance >> 675 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 676 AMDGPU_INFO_MMR_SH_INDEX_MASK; 677 678 /* set full masks if the userspace set all bits 679 * in the bitfields */ 680 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 681 se_num = 0xffffffff; 682 else if (se_num >= AMDGPU_GFX_MAX_SE) 683 return -EINVAL; 684 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 685 sh_num = 0xffffffff; 686 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 687 return -EINVAL; 688 689 if (info->read_mmr_reg.count > 128) 690 return -EINVAL; 691 692 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 693 if (!regs) 694 return -ENOMEM; 695 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 696 697 amdgpu_gfx_off_ctrl(adev, false); 698 for (i = 0; i < info->read_mmr_reg.count; i++) { 699 if (amdgpu_asic_read_register(adev, se_num, sh_num, 700 info->read_mmr_reg.dword_offset + i, 701 ®s[i])) { 702 DRM_DEBUG_KMS("unallowed offset %#x\n", 703 info->read_mmr_reg.dword_offset + i); 704 kfree(regs); 705 amdgpu_gfx_off_ctrl(adev, true); 706 return -EFAULT; 707 } 708 } 709 amdgpu_gfx_off_ctrl(adev, true); 710 n = copy_to_user(out, regs, min(size, alloc_size)); 711 kfree(regs); 712 return n ? -EFAULT : 0; 713 } 714 case AMDGPU_INFO_DEV_INFO: { 715 struct drm_amdgpu_info_device dev_info; 716 uint64_t vm_size; 717 718 memset(&dev_info, 0, sizeof(dev_info)); 719 dev_info.device_id = dev->pdev->device; 720 dev_info.chip_rev = adev->rev_id; 721 dev_info.external_rev = adev->external_rev_id; 722 dev_info.pci_rev = dev->pdev->revision; 723 dev_info.family = adev->family; 724 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 725 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 726 /* return all clocks in KHz */ 727 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 728 if (adev->pm.dpm_enabled) { 729 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 730 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 731 } else { 732 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 733 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 734 } 735 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 736 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 737 adev->gfx.config.max_shader_engines; 738 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 739 dev_info._pad = 0; 740 dev_info.ids_flags = 0; 741 if (adev->flags & AMD_IS_APU) 742 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 743 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 744 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 745 746 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 747 vm_size -= AMDGPU_VA_RESERVED_SIZE; 748 749 /* Older VCE FW versions are buggy and can handle only 40bits */ 750 if (adev->vce.fw_version && 751 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 752 vm_size = min(vm_size, 1ULL << 40); 753 754 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 755 dev_info.virtual_address_max = 756 min(vm_size, AMDGPU_GMC_HOLE_START); 757 758 if (vm_size > AMDGPU_GMC_HOLE_START) { 759 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 760 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 761 } 762 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 763 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 764 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 765 dev_info.cu_active_number = adev->gfx.cu_info.number; 766 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 767 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 768 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 769 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 770 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 771 sizeof(adev->gfx.cu_info.bitmap)); 772 dev_info.vram_type = adev->gmc.vram_type; 773 dev_info.vram_bit_width = adev->gmc.vram_width; 774 dev_info.vce_harvest_config = adev->vce.harvest_config; 775 dev_info.gc_double_offchip_lds_buf = 776 adev->gfx.config.double_offchip_lds_buf; 777 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 778 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 779 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 780 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 781 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 782 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 783 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 784 785 if (adev->family >= AMDGPU_FAMILY_NV) 786 dev_info.pa_sc_tile_steering_override = 787 adev->gfx.config.pa_sc_tile_steering_override; 788 789 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 790 791 return copy_to_user(out, &dev_info, 792 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 793 } 794 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 795 unsigned i; 796 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 797 struct amd_vce_state *vce_state; 798 799 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 800 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 801 if (vce_state) { 802 vce_clk_table.entries[i].sclk = vce_state->sclk; 803 vce_clk_table.entries[i].mclk = vce_state->mclk; 804 vce_clk_table.entries[i].eclk = vce_state->evclk; 805 vce_clk_table.num_valid_entries++; 806 } 807 } 808 809 return copy_to_user(out, &vce_clk_table, 810 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 811 } 812 case AMDGPU_INFO_VBIOS: { 813 uint32_t bios_size = adev->bios_size; 814 815 switch (info->vbios_info.type) { 816 case AMDGPU_INFO_VBIOS_SIZE: 817 return copy_to_user(out, &bios_size, 818 min((size_t)size, sizeof(bios_size))) 819 ? -EFAULT : 0; 820 case AMDGPU_INFO_VBIOS_IMAGE: { 821 uint8_t *bios; 822 uint32_t bios_offset = info->vbios_info.offset; 823 824 if (bios_offset >= bios_size) 825 return -EINVAL; 826 827 bios = adev->bios + bios_offset; 828 return copy_to_user(out, bios, 829 min((size_t)size, (size_t)(bios_size - bios_offset))) 830 ? -EFAULT : 0; 831 } 832 default: 833 DRM_DEBUG_KMS("Invalid request %d\n", 834 info->vbios_info.type); 835 return -EINVAL; 836 } 837 } 838 case AMDGPU_INFO_NUM_HANDLES: { 839 struct drm_amdgpu_info_num_handles handle; 840 841 switch (info->query_hw_ip.type) { 842 case AMDGPU_HW_IP_UVD: 843 /* Starting Polaris, we support unlimited UVD handles */ 844 if (adev->asic_type < CHIP_POLARIS10) { 845 handle.uvd_max_handles = adev->uvd.max_handles; 846 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 847 848 return copy_to_user(out, &handle, 849 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 850 } else { 851 return -ENODATA; 852 } 853 854 break; 855 default: 856 return -EINVAL; 857 } 858 } 859 case AMDGPU_INFO_SENSOR: { 860 if (!adev->pm.dpm_enabled) 861 return -ENOENT; 862 863 switch (info->sensor_info.type) { 864 case AMDGPU_INFO_SENSOR_GFX_SCLK: 865 /* get sclk in Mhz */ 866 if (amdgpu_dpm_read_sensor(adev, 867 AMDGPU_PP_SENSOR_GFX_SCLK, 868 (void *)&ui32, &ui32_size)) { 869 return -EINVAL; 870 } 871 ui32 /= 100; 872 break; 873 case AMDGPU_INFO_SENSOR_GFX_MCLK: 874 /* get mclk in Mhz */ 875 if (amdgpu_dpm_read_sensor(adev, 876 AMDGPU_PP_SENSOR_GFX_MCLK, 877 (void *)&ui32, &ui32_size)) { 878 return -EINVAL; 879 } 880 ui32 /= 100; 881 break; 882 case AMDGPU_INFO_SENSOR_GPU_TEMP: 883 /* get temperature in millidegrees C */ 884 if (amdgpu_dpm_read_sensor(adev, 885 AMDGPU_PP_SENSOR_GPU_TEMP, 886 (void *)&ui32, &ui32_size)) { 887 return -EINVAL; 888 } 889 break; 890 case AMDGPU_INFO_SENSOR_GPU_LOAD: 891 /* get GPU load */ 892 if (amdgpu_dpm_read_sensor(adev, 893 AMDGPU_PP_SENSOR_GPU_LOAD, 894 (void *)&ui32, &ui32_size)) { 895 return -EINVAL; 896 } 897 break; 898 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 899 /* get average GPU power */ 900 if (amdgpu_dpm_read_sensor(adev, 901 AMDGPU_PP_SENSOR_GPU_POWER, 902 (void *)&ui32, &ui32_size)) { 903 return -EINVAL; 904 } 905 ui32 >>= 8; 906 break; 907 case AMDGPU_INFO_SENSOR_VDDNB: 908 /* get VDDNB in millivolts */ 909 if (amdgpu_dpm_read_sensor(adev, 910 AMDGPU_PP_SENSOR_VDDNB, 911 (void *)&ui32, &ui32_size)) { 912 return -EINVAL; 913 } 914 break; 915 case AMDGPU_INFO_SENSOR_VDDGFX: 916 /* get VDDGFX in millivolts */ 917 if (amdgpu_dpm_read_sensor(adev, 918 AMDGPU_PP_SENSOR_VDDGFX, 919 (void *)&ui32, &ui32_size)) { 920 return -EINVAL; 921 } 922 break; 923 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 924 /* get stable pstate sclk in Mhz */ 925 if (amdgpu_dpm_read_sensor(adev, 926 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 927 (void *)&ui32, &ui32_size)) { 928 return -EINVAL; 929 } 930 ui32 /= 100; 931 break; 932 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 933 /* get stable pstate mclk in Mhz */ 934 if (amdgpu_dpm_read_sensor(adev, 935 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 936 (void *)&ui32, &ui32_size)) { 937 return -EINVAL; 938 } 939 ui32 /= 100; 940 break; 941 default: 942 DRM_DEBUG_KMS("Invalid request %d\n", 943 info->sensor_info.type); 944 return -EINVAL; 945 } 946 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 947 } 948 case AMDGPU_INFO_VRAM_LOST_COUNTER: 949 ui32 = atomic_read(&adev->vram_lost_counter); 950 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 951 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 952 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 953 uint64_t ras_mask; 954 955 if (!ras) 956 return -EINVAL; 957 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 958 959 return copy_to_user(out, &ras_mask, 960 min_t(u64, size, sizeof(ras_mask))) ? 961 -EFAULT : 0; 962 } 963 default: 964 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 965 return -EINVAL; 966 } 967 return 0; 968 } 969 970 971 /* 972 * Outdated mess for old drm with Xorg being in charge (void function now). 973 */ 974 /** 975 * amdgpu_driver_lastclose_kms - drm callback for last close 976 * 977 * @dev: drm dev pointer 978 * 979 * Switch vga_switcheroo state after last close (all asics). 980 */ 981 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 982 { 983 drm_fb_helper_lastclose(dev); 984 vga_switcheroo_process_delayed_switch(); 985 } 986 987 /** 988 * amdgpu_driver_open_kms - drm callback for open 989 * 990 * @dev: drm dev pointer 991 * @file_priv: drm file 992 * 993 * On device open, init vm on cayman+ (all asics). 994 * Returns 0 on success, error on failure. 995 */ 996 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 997 { 998 struct amdgpu_device *adev = dev->dev_private; 999 struct amdgpu_fpriv *fpriv; 1000 int r, pasid; 1001 1002 /* Ensure IB tests are run on ring */ 1003 flush_delayed_work(&adev->delayed_init_work); 1004 1005 1006 if (amdgpu_ras_intr_triggered()) { 1007 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1008 return -EHWPOISON; 1009 } 1010 1011 file_priv->driver_priv = NULL; 1012 1013 r = pm_runtime_get_sync(dev->dev); 1014 if (r < 0) 1015 goto pm_put; 1016 1017 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1018 if (unlikely(!fpriv)) { 1019 r = -ENOMEM; 1020 goto out_suspend; 1021 } 1022 1023 pasid = amdgpu_pasid_alloc(16); 1024 if (pasid < 0) { 1025 dev_warn(adev->dev, "No more PASIDs available!"); 1026 pasid = 0; 1027 } 1028 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1029 if (r) 1030 goto error_pasid; 1031 1032 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1033 if (!fpriv->prt_va) { 1034 r = -ENOMEM; 1035 goto error_vm; 1036 } 1037 1038 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1039 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1040 1041 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1042 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1043 if (r) 1044 goto error_vm; 1045 } 1046 1047 mutex_init(&fpriv->bo_list_lock); 1048 idr_init(&fpriv->bo_list_handles); 1049 1050 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1051 1052 file_priv->driver_priv = fpriv; 1053 goto out_suspend; 1054 1055 error_vm: 1056 amdgpu_vm_fini(adev, &fpriv->vm); 1057 1058 error_pasid: 1059 if (pasid) 1060 amdgpu_pasid_free(pasid); 1061 1062 kfree(fpriv); 1063 1064 out_suspend: 1065 pm_runtime_mark_last_busy(dev->dev); 1066 pm_put: 1067 pm_runtime_put_autosuspend(dev->dev); 1068 1069 return r; 1070 } 1071 1072 /** 1073 * amdgpu_driver_postclose_kms - drm callback for post close 1074 * 1075 * @dev: drm dev pointer 1076 * @file_priv: drm file 1077 * 1078 * On device post close, tear down vm on cayman+ (all asics). 1079 */ 1080 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1081 struct drm_file *file_priv) 1082 { 1083 struct amdgpu_device *adev = dev->dev_private; 1084 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1085 struct amdgpu_bo_list *list; 1086 struct amdgpu_bo *pd; 1087 unsigned int pasid; 1088 int handle; 1089 1090 if (!fpriv) 1091 return; 1092 1093 pm_runtime_get_sync(dev->dev); 1094 1095 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1096 amdgpu_uvd_free_handles(adev, file_priv); 1097 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1098 amdgpu_vce_free_handles(adev, file_priv); 1099 1100 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1101 1102 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1103 /* TODO: how to handle reserve failure */ 1104 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1105 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1106 fpriv->csa_va = NULL; 1107 amdgpu_bo_unreserve(adev->virt.csa_obj); 1108 } 1109 1110 pasid = fpriv->vm.pasid; 1111 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1112 1113 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1114 amdgpu_vm_fini(adev, &fpriv->vm); 1115 1116 if (pasid) 1117 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1118 amdgpu_bo_unref(&pd); 1119 1120 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1121 amdgpu_bo_list_put(list); 1122 1123 idr_destroy(&fpriv->bo_list_handles); 1124 mutex_destroy(&fpriv->bo_list_lock); 1125 1126 kfree(fpriv); 1127 file_priv->driver_priv = NULL; 1128 1129 pm_runtime_mark_last_busy(dev->dev); 1130 pm_runtime_put_autosuspend(dev->dev); 1131 } 1132 1133 /* 1134 * VBlank related functions. 1135 */ 1136 /** 1137 * amdgpu_get_vblank_counter_kms - get frame count 1138 * 1139 * @crtc: crtc to get the frame count from 1140 * 1141 * Gets the frame count on the requested crtc (all asics). 1142 * Returns frame count on success, -EINVAL on failure. 1143 */ 1144 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1145 { 1146 struct drm_device *dev = crtc->dev; 1147 unsigned int pipe = crtc->index; 1148 struct amdgpu_device *adev = dev->dev_private; 1149 int vpos, hpos, stat; 1150 u32 count; 1151 1152 if (pipe >= adev->mode_info.num_crtc) { 1153 DRM_ERROR("Invalid crtc %u\n", pipe); 1154 return -EINVAL; 1155 } 1156 1157 /* The hw increments its frame counter at start of vsync, not at start 1158 * of vblank, as is required by DRM core vblank counter handling. 1159 * Cook the hw count here to make it appear to the caller as if it 1160 * incremented at start of vblank. We measure distance to start of 1161 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1162 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1163 * result by 1 to give the proper appearance to caller. 1164 */ 1165 if (adev->mode_info.crtcs[pipe]) { 1166 /* Repeat readout if needed to provide stable result if 1167 * we cross start of vsync during the queries. 1168 */ 1169 do { 1170 count = amdgpu_display_vblank_get_counter(adev, pipe); 1171 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1172 * vpos as distance to start of vblank, instead of 1173 * regular vertical scanout pos. 1174 */ 1175 stat = amdgpu_display_get_crtc_scanoutpos( 1176 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1177 &vpos, &hpos, NULL, NULL, 1178 &adev->mode_info.crtcs[pipe]->base.hwmode); 1179 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1180 1181 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1182 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1183 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1184 } else { 1185 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1186 pipe, vpos); 1187 1188 /* Bump counter if we are at >= leading edge of vblank, 1189 * but before vsync where vpos would turn negative and 1190 * the hw counter really increments. 1191 */ 1192 if (vpos >= 0) 1193 count++; 1194 } 1195 } else { 1196 /* Fallback to use value as is. */ 1197 count = amdgpu_display_vblank_get_counter(adev, pipe); 1198 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1199 } 1200 1201 return count; 1202 } 1203 1204 /** 1205 * amdgpu_enable_vblank_kms - enable vblank interrupt 1206 * 1207 * @crtc: crtc to enable vblank interrupt for 1208 * 1209 * Enable the interrupt on the requested crtc (all asics). 1210 * Returns 0 on success, -EINVAL on failure. 1211 */ 1212 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1213 { 1214 struct drm_device *dev = crtc->dev; 1215 unsigned int pipe = crtc->index; 1216 struct amdgpu_device *adev = dev->dev_private; 1217 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1218 1219 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1220 } 1221 1222 /** 1223 * amdgpu_disable_vblank_kms - disable vblank interrupt 1224 * 1225 * @crtc: crtc to disable vblank interrupt for 1226 * 1227 * Disable the interrupt on the requested crtc (all asics). 1228 */ 1229 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1230 { 1231 struct drm_device *dev = crtc->dev; 1232 unsigned int pipe = crtc->index; 1233 struct amdgpu_device *adev = dev->dev_private; 1234 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1235 1236 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1237 } 1238 1239 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1240 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1241 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1242 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1243 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1244 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1245 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1246 /* KMS */ 1247 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1248 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1249 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1250 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1251 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1252 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1253 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1254 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1255 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1256 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1257 }; 1258 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1259 1260 /* 1261 * Debugfs info 1262 */ 1263 #if defined(CONFIG_DEBUG_FS) 1264 1265 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1266 { 1267 struct drm_info_node *node = (struct drm_info_node *) m->private; 1268 struct drm_device *dev = node->minor->dev; 1269 struct amdgpu_device *adev = dev->dev_private; 1270 struct drm_amdgpu_info_firmware fw_info; 1271 struct drm_amdgpu_query_fw query_fw; 1272 struct atom_context *ctx = adev->mode_info.atom_context; 1273 int ret, i; 1274 1275 /* VCE */ 1276 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1277 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1278 if (ret) 1279 return ret; 1280 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1281 fw_info.feature, fw_info.ver); 1282 1283 /* UVD */ 1284 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1285 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1286 if (ret) 1287 return ret; 1288 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1289 fw_info.feature, fw_info.ver); 1290 1291 /* GMC */ 1292 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1293 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1294 if (ret) 1295 return ret; 1296 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1297 fw_info.feature, fw_info.ver); 1298 1299 /* ME */ 1300 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1301 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1302 if (ret) 1303 return ret; 1304 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1305 fw_info.feature, fw_info.ver); 1306 1307 /* PFP */ 1308 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1309 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1310 if (ret) 1311 return ret; 1312 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1313 fw_info.feature, fw_info.ver); 1314 1315 /* CE */ 1316 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1317 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1318 if (ret) 1319 return ret; 1320 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1321 fw_info.feature, fw_info.ver); 1322 1323 /* RLC */ 1324 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1325 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1326 if (ret) 1327 return ret; 1328 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1329 fw_info.feature, fw_info.ver); 1330 1331 /* RLC SAVE RESTORE LIST CNTL */ 1332 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1333 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1334 if (ret) 1335 return ret; 1336 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1337 fw_info.feature, fw_info.ver); 1338 1339 /* RLC SAVE RESTORE LIST GPM MEM */ 1340 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1341 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1342 if (ret) 1343 return ret; 1344 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1345 fw_info.feature, fw_info.ver); 1346 1347 /* RLC SAVE RESTORE LIST SRM MEM */ 1348 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1349 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1350 if (ret) 1351 return ret; 1352 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1353 fw_info.feature, fw_info.ver); 1354 1355 /* MEC */ 1356 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1357 query_fw.index = 0; 1358 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1359 if (ret) 1360 return ret; 1361 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1362 fw_info.feature, fw_info.ver); 1363 1364 /* MEC2 */ 1365 if (adev->gfx.mec2_fw) { 1366 query_fw.index = 1; 1367 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1368 if (ret) 1369 return ret; 1370 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1371 fw_info.feature, fw_info.ver); 1372 } 1373 1374 /* PSP SOS */ 1375 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1376 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1377 if (ret) 1378 return ret; 1379 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1380 fw_info.feature, fw_info.ver); 1381 1382 1383 /* PSP ASD */ 1384 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1385 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1386 if (ret) 1387 return ret; 1388 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1389 fw_info.feature, fw_info.ver); 1390 1391 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1392 for (i = 0; i < 2; i++) { 1393 query_fw.index = i; 1394 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1395 if (ret) 1396 continue; 1397 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n", 1398 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver); 1399 } 1400 1401 /* SMC */ 1402 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1403 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1404 if (ret) 1405 return ret; 1406 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1407 fw_info.feature, fw_info.ver); 1408 1409 /* SDMA */ 1410 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1411 for (i = 0; i < adev->sdma.num_instances; i++) { 1412 query_fw.index = i; 1413 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1414 if (ret) 1415 return ret; 1416 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1417 i, fw_info.feature, fw_info.ver); 1418 } 1419 1420 /* VCN */ 1421 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1422 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1423 if (ret) 1424 return ret; 1425 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1426 fw_info.feature, fw_info.ver); 1427 1428 /* DMCU */ 1429 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1430 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1431 if (ret) 1432 return ret; 1433 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1434 fw_info.feature, fw_info.ver); 1435 1436 /* DMCUB */ 1437 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1438 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1439 if (ret) 1440 return ret; 1441 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1442 fw_info.feature, fw_info.ver); 1443 1444 1445 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1446 1447 return 0; 1448 } 1449 1450 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1451 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1452 }; 1453 #endif 1454 1455 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1456 { 1457 #if defined(CONFIG_DEBUG_FS) 1458 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1459 ARRAY_SIZE(amdgpu_firmware_info_list)); 1460 #else 1461 return 0; 1462 #endif 1463 } 1464