1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_sched.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/pm_runtime.h> 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * amdgpu_driver_unload_kms - Main unload function for KMS. 43 * 44 * @dev: drm dev pointer 45 * 46 * This is the main unload function for KMS (all asics). 47 * Returns 0 on success. 48 */ 49 void amdgpu_driver_unload_kms(struct drm_device *dev) 50 { 51 struct amdgpu_device *adev = dev->dev_private; 52 53 if (adev == NULL) 54 return; 55 56 if (adev->rmmio == NULL) 57 goto done_free; 58 59 if (amdgpu_sriov_vf(adev)) 60 amdgpu_virt_request_full_gpu(adev, false); 61 62 if (amdgpu_device_is_px(dev)) { 63 pm_runtime_get_sync(dev->dev); 64 pm_runtime_forbid(dev->dev); 65 } 66 67 amdgpu_acpi_fini(adev); 68 69 amdgpu_device_fini(adev); 70 71 done_free: 72 kfree(adev); 73 dev->dev_private = NULL; 74 } 75 76 /** 77 * amdgpu_driver_load_kms - Main load function for KMS. 78 * 79 * @dev: drm dev pointer 80 * @flags: device flags 81 * 82 * This is the main load function for KMS (all asics). 83 * Returns 0 on success, error on failure. 84 */ 85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 86 { 87 struct amdgpu_device *adev; 88 int r, acpi_status; 89 90 #ifdef CONFIG_DRM_AMDGPU_SI 91 if (!amdgpu_si_support) { 92 switch (flags & AMD_ASIC_MASK) { 93 case CHIP_TAHITI: 94 case CHIP_PITCAIRN: 95 case CHIP_VERDE: 96 case CHIP_OLAND: 97 case CHIP_HAINAN: 98 dev_info(dev->dev, 99 "SI support provided by radeon.\n"); 100 dev_info(dev->dev, 101 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 102 ); 103 return -ENODEV; 104 } 105 } 106 #endif 107 #ifdef CONFIG_DRM_AMDGPU_CIK 108 if (!amdgpu_cik_support) { 109 switch (flags & AMD_ASIC_MASK) { 110 case CHIP_KAVERI: 111 case CHIP_BONAIRE: 112 case CHIP_HAWAII: 113 case CHIP_KABINI: 114 case CHIP_MULLINS: 115 dev_info(dev->dev, 116 "CIK support provided by radeon.\n"); 117 dev_info(dev->dev, 118 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 119 ); 120 return -ENODEV; 121 } 122 } 123 #endif 124 125 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 126 if (adev == NULL) { 127 return -ENOMEM; 128 } 129 dev->dev_private = (void *)adev; 130 131 if ((amdgpu_runtime_pm != 0) && 132 amdgpu_has_atpx() && 133 (amdgpu_is_atpx_hybrid() || 134 amdgpu_has_atpx_dgpu_power_cntl()) && 135 ((flags & AMD_IS_APU) == 0) && 136 !pci_is_thunderbolt_attached(dev->pdev)) 137 flags |= AMD_IS_PX; 138 139 /* amdgpu_device_init should report only fatal error 140 * like memory allocation failure or iomapping failure, 141 * or memory manager initialization failure, it must 142 * properly initialize the GPU MC controller and permit 143 * VRAM allocation 144 */ 145 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 146 if (r) { 147 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 148 goto out; 149 } 150 151 /* Call ACPI methods: require modeset init 152 * but failure is not fatal 153 */ 154 if (!r) { 155 acpi_status = amdgpu_acpi_init(adev); 156 if (acpi_status) 157 dev_dbg(&dev->pdev->dev, 158 "Error during ACPI methods call\n"); 159 } 160 161 if (amdgpu_device_is_px(dev)) { 162 pm_runtime_use_autosuspend(dev->dev); 163 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 164 pm_runtime_set_active(dev->dev); 165 pm_runtime_allow(dev->dev); 166 pm_runtime_mark_last_busy(dev->dev); 167 pm_runtime_put_autosuspend(dev->dev); 168 } 169 170 out: 171 if (r) { 172 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 173 if (adev->rmmio && amdgpu_device_is_px(dev)) 174 pm_runtime_put_noidle(dev->dev); 175 amdgpu_driver_unload_kms(dev); 176 } 177 178 return r; 179 } 180 181 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 182 struct drm_amdgpu_query_fw *query_fw, 183 struct amdgpu_device *adev) 184 { 185 switch (query_fw->fw_type) { 186 case AMDGPU_INFO_FW_VCE: 187 fw_info->ver = adev->vce.fw_version; 188 fw_info->feature = adev->vce.fb_version; 189 break; 190 case AMDGPU_INFO_FW_UVD: 191 fw_info->ver = adev->uvd.fw_version; 192 fw_info->feature = 0; 193 break; 194 case AMDGPU_INFO_FW_VCN: 195 fw_info->ver = adev->vcn.fw_version; 196 fw_info->feature = 0; 197 break; 198 case AMDGPU_INFO_FW_GMC: 199 fw_info->ver = adev->gmc.fw_version; 200 fw_info->feature = 0; 201 break; 202 case AMDGPU_INFO_FW_GFX_ME: 203 fw_info->ver = adev->gfx.me_fw_version; 204 fw_info->feature = adev->gfx.me_feature_version; 205 break; 206 case AMDGPU_INFO_FW_GFX_PFP: 207 fw_info->ver = adev->gfx.pfp_fw_version; 208 fw_info->feature = adev->gfx.pfp_feature_version; 209 break; 210 case AMDGPU_INFO_FW_GFX_CE: 211 fw_info->ver = adev->gfx.ce_fw_version; 212 fw_info->feature = adev->gfx.ce_feature_version; 213 break; 214 case AMDGPU_INFO_FW_GFX_RLC: 215 fw_info->ver = adev->gfx.rlc_fw_version; 216 fw_info->feature = adev->gfx.rlc_feature_version; 217 break; 218 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 219 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 220 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 221 break; 222 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 223 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 224 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 225 break; 226 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 227 fw_info->ver = adev->gfx.rlc_srls_fw_version; 228 fw_info->feature = adev->gfx.rlc_srls_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_MEC: 231 if (query_fw->index == 0) { 232 fw_info->ver = adev->gfx.mec_fw_version; 233 fw_info->feature = adev->gfx.mec_feature_version; 234 } else if (query_fw->index == 1) { 235 fw_info->ver = adev->gfx.mec2_fw_version; 236 fw_info->feature = adev->gfx.mec2_feature_version; 237 } else 238 return -EINVAL; 239 break; 240 case AMDGPU_INFO_FW_SMC: 241 fw_info->ver = adev->pm.fw_version; 242 fw_info->feature = 0; 243 break; 244 case AMDGPU_INFO_FW_SDMA: 245 if (query_fw->index >= adev->sdma.num_instances) 246 return -EINVAL; 247 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 248 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 249 break; 250 case AMDGPU_INFO_FW_SOS: 251 fw_info->ver = adev->psp.sos_fw_version; 252 fw_info->feature = adev->psp.sos_feature_version; 253 break; 254 case AMDGPU_INFO_FW_ASD: 255 fw_info->ver = adev->psp.asd_fw_version; 256 fw_info->feature = adev->psp.asd_feature_version; 257 break; 258 default: 259 return -EINVAL; 260 } 261 return 0; 262 } 263 264 /* 265 * Userspace get information ioctl 266 */ 267 /** 268 * amdgpu_info_ioctl - answer a device specific request. 269 * 270 * @adev: amdgpu device pointer 271 * @data: request object 272 * @filp: drm filp 273 * 274 * This function is used to pass device specific parameters to the userspace 275 * drivers. Examples include: pci device id, pipeline parms, tiling params, 276 * etc. (all asics). 277 * Returns 0 on success, -EINVAL on failure. 278 */ 279 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 280 { 281 struct amdgpu_device *adev = dev->dev_private; 282 struct drm_amdgpu_info *info = data; 283 struct amdgpu_mode_info *minfo = &adev->mode_info; 284 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 285 uint32_t size = info->return_size; 286 struct drm_crtc *crtc; 287 uint32_t ui32 = 0; 288 uint64_t ui64 = 0; 289 int i, j, found; 290 int ui32_size = sizeof(ui32); 291 292 if (!info->return_size || !info->return_pointer) 293 return -EINVAL; 294 295 /* Ensure IB tests are run on ring */ 296 flush_delayed_work(&adev->late_init_work); 297 298 switch (info->query) { 299 case AMDGPU_INFO_ACCEL_WORKING: 300 ui32 = adev->accel_working; 301 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 302 case AMDGPU_INFO_CRTC_FROM_ID: 303 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 304 crtc = (struct drm_crtc *)minfo->crtcs[i]; 305 if (crtc && crtc->base.id == info->mode_crtc.id) { 306 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 307 ui32 = amdgpu_crtc->crtc_id; 308 found = 1; 309 break; 310 } 311 } 312 if (!found) { 313 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 314 return -EINVAL; 315 } 316 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 317 case AMDGPU_INFO_HW_IP_INFO: { 318 struct drm_amdgpu_info_hw_ip ip = {}; 319 enum amd_ip_block_type type; 320 uint32_t ring_mask = 0; 321 uint32_t ib_start_alignment = 0; 322 uint32_t ib_size_alignment = 0; 323 324 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 325 return -EINVAL; 326 327 switch (info->query_hw_ip.type) { 328 case AMDGPU_HW_IP_GFX: 329 type = AMD_IP_BLOCK_TYPE_GFX; 330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 331 ring_mask |= adev->gfx.gfx_ring[i].ready << i; 332 ib_start_alignment = 32; 333 ib_size_alignment = 32; 334 break; 335 case AMDGPU_HW_IP_COMPUTE: 336 type = AMD_IP_BLOCK_TYPE_GFX; 337 for (i = 0; i < adev->gfx.num_compute_rings; i++) 338 ring_mask |= adev->gfx.compute_ring[i].ready << i; 339 ib_start_alignment = 32; 340 ib_size_alignment = 32; 341 break; 342 case AMDGPU_HW_IP_DMA: 343 type = AMD_IP_BLOCK_TYPE_SDMA; 344 for (i = 0; i < adev->sdma.num_instances; i++) 345 ring_mask |= adev->sdma.instance[i].ring.ready << i; 346 ib_start_alignment = 256; 347 ib_size_alignment = 4; 348 break; 349 case AMDGPU_HW_IP_UVD: 350 type = AMD_IP_BLOCK_TYPE_UVD; 351 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 352 if (adev->uvd.harvest_config & (1 << i)) 353 continue; 354 ring_mask |= adev->uvd.inst[i].ring.ready; 355 } 356 ib_start_alignment = 64; 357 ib_size_alignment = 64; 358 break; 359 case AMDGPU_HW_IP_VCE: 360 type = AMD_IP_BLOCK_TYPE_VCE; 361 for (i = 0; i < adev->vce.num_rings; i++) 362 ring_mask |= adev->vce.ring[i].ready << i; 363 ib_start_alignment = 4; 364 ib_size_alignment = 1; 365 break; 366 case AMDGPU_HW_IP_UVD_ENC: 367 type = AMD_IP_BLOCK_TYPE_UVD; 368 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 369 if (adev->uvd.harvest_config & (1 << i)) 370 continue; 371 for (j = 0; j < adev->uvd.num_enc_rings; j++) 372 ring_mask |= adev->uvd.inst[i].ring_enc[j].ready << j; 373 } 374 ib_start_alignment = 64; 375 ib_size_alignment = 64; 376 break; 377 case AMDGPU_HW_IP_VCN_DEC: 378 type = AMD_IP_BLOCK_TYPE_VCN; 379 ring_mask = adev->vcn.ring_dec.ready; 380 ib_start_alignment = 16; 381 ib_size_alignment = 16; 382 break; 383 case AMDGPU_HW_IP_VCN_ENC: 384 type = AMD_IP_BLOCK_TYPE_VCN; 385 for (i = 0; i < adev->vcn.num_enc_rings; i++) 386 ring_mask |= adev->vcn.ring_enc[i].ready << i; 387 ib_start_alignment = 64; 388 ib_size_alignment = 1; 389 break; 390 case AMDGPU_HW_IP_VCN_JPEG: 391 type = AMD_IP_BLOCK_TYPE_VCN; 392 ring_mask = adev->vcn.ring_jpeg.ready; 393 ib_start_alignment = 16; 394 ib_size_alignment = 16; 395 break; 396 default: 397 return -EINVAL; 398 } 399 400 for (i = 0; i < adev->num_ip_blocks; i++) { 401 if (adev->ip_blocks[i].version->type == type && 402 adev->ip_blocks[i].status.valid) { 403 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 404 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 405 ip.capabilities_flags = 0; 406 ip.available_rings = ring_mask; 407 ip.ib_start_alignment = ib_start_alignment; 408 ip.ib_size_alignment = ib_size_alignment; 409 break; 410 } 411 } 412 return copy_to_user(out, &ip, 413 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 414 } 415 case AMDGPU_INFO_HW_IP_COUNT: { 416 enum amd_ip_block_type type; 417 uint32_t count = 0; 418 419 switch (info->query_hw_ip.type) { 420 case AMDGPU_HW_IP_GFX: 421 type = AMD_IP_BLOCK_TYPE_GFX; 422 break; 423 case AMDGPU_HW_IP_COMPUTE: 424 type = AMD_IP_BLOCK_TYPE_GFX; 425 break; 426 case AMDGPU_HW_IP_DMA: 427 type = AMD_IP_BLOCK_TYPE_SDMA; 428 break; 429 case AMDGPU_HW_IP_UVD: 430 type = AMD_IP_BLOCK_TYPE_UVD; 431 break; 432 case AMDGPU_HW_IP_VCE: 433 type = AMD_IP_BLOCK_TYPE_VCE; 434 break; 435 case AMDGPU_HW_IP_UVD_ENC: 436 type = AMD_IP_BLOCK_TYPE_UVD; 437 break; 438 case AMDGPU_HW_IP_VCN_DEC: 439 case AMDGPU_HW_IP_VCN_ENC: 440 case AMDGPU_HW_IP_VCN_JPEG: 441 type = AMD_IP_BLOCK_TYPE_VCN; 442 break; 443 default: 444 return -EINVAL; 445 } 446 447 for (i = 0; i < adev->num_ip_blocks; i++) 448 if (adev->ip_blocks[i].version->type == type && 449 adev->ip_blocks[i].status.valid && 450 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 451 count++; 452 453 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 454 } 455 case AMDGPU_INFO_TIMESTAMP: 456 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 457 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 458 case AMDGPU_INFO_FW_VERSION: { 459 struct drm_amdgpu_info_firmware fw_info; 460 int ret; 461 462 /* We only support one instance of each IP block right now. */ 463 if (info->query_fw.ip_instance != 0) 464 return -EINVAL; 465 466 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 467 if (ret) 468 return ret; 469 470 return copy_to_user(out, &fw_info, 471 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 472 } 473 case AMDGPU_INFO_NUM_BYTES_MOVED: 474 ui64 = atomic64_read(&adev->num_bytes_moved); 475 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 476 case AMDGPU_INFO_NUM_EVICTIONS: 477 ui64 = atomic64_read(&adev->num_evictions); 478 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 479 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 480 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 481 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 482 case AMDGPU_INFO_VRAM_USAGE: 483 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 484 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 485 case AMDGPU_INFO_VIS_VRAM_USAGE: 486 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 487 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 488 case AMDGPU_INFO_GTT_USAGE: 489 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 490 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 491 case AMDGPU_INFO_GDS_CONFIG: { 492 struct drm_amdgpu_info_gds gds_info; 493 494 memset(&gds_info, 0, sizeof(gds_info)); 495 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 496 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 497 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 498 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 499 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 500 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 501 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 502 return copy_to_user(out, &gds_info, 503 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 504 } 505 case AMDGPU_INFO_VRAM_GTT: { 506 struct drm_amdgpu_info_vram_gtt vram_gtt; 507 508 vram_gtt.vram_size = adev->gmc.real_vram_size - 509 atomic64_read(&adev->vram_pin_size); 510 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size - 511 atomic64_read(&adev->visible_pin_size); 512 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 513 vram_gtt.gtt_size *= PAGE_SIZE; 514 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 515 return copy_to_user(out, &vram_gtt, 516 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 517 } 518 case AMDGPU_INFO_MEMORY: { 519 struct drm_amdgpu_memory_info mem; 520 521 memset(&mem, 0, sizeof(mem)); 522 mem.vram.total_heap_size = adev->gmc.real_vram_size; 523 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 524 atomic64_read(&adev->vram_pin_size); 525 mem.vram.heap_usage = 526 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 527 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 528 529 mem.cpu_accessible_vram.total_heap_size = 530 adev->gmc.visible_vram_size; 531 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size - 532 atomic64_read(&adev->visible_pin_size); 533 mem.cpu_accessible_vram.heap_usage = 534 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 535 mem.cpu_accessible_vram.max_allocation = 536 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 537 538 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 539 mem.gtt.total_heap_size *= PAGE_SIZE; 540 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 541 atomic64_read(&adev->gart_pin_size); 542 mem.gtt.heap_usage = 543 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 544 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 545 546 return copy_to_user(out, &mem, 547 min((size_t)size, sizeof(mem))) 548 ? -EFAULT : 0; 549 } 550 case AMDGPU_INFO_READ_MMR_REG: { 551 unsigned n, alloc_size; 552 uint32_t *regs; 553 unsigned se_num = (info->read_mmr_reg.instance >> 554 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 555 AMDGPU_INFO_MMR_SE_INDEX_MASK; 556 unsigned sh_num = (info->read_mmr_reg.instance >> 557 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 558 AMDGPU_INFO_MMR_SH_INDEX_MASK; 559 560 /* set full masks if the userspace set all bits 561 * in the bitfields */ 562 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 563 se_num = 0xffffffff; 564 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 565 sh_num = 0xffffffff; 566 567 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 568 if (!regs) 569 return -ENOMEM; 570 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 571 572 for (i = 0; i < info->read_mmr_reg.count; i++) 573 if (amdgpu_asic_read_register(adev, se_num, sh_num, 574 info->read_mmr_reg.dword_offset + i, 575 ®s[i])) { 576 DRM_DEBUG_KMS("unallowed offset %#x\n", 577 info->read_mmr_reg.dword_offset + i); 578 kfree(regs); 579 return -EFAULT; 580 } 581 n = copy_to_user(out, regs, min(size, alloc_size)); 582 kfree(regs); 583 return n ? -EFAULT : 0; 584 } 585 case AMDGPU_INFO_DEV_INFO: { 586 struct drm_amdgpu_info_device dev_info = {}; 587 uint64_t vm_size; 588 589 dev_info.device_id = dev->pdev->device; 590 dev_info.chip_rev = adev->rev_id; 591 dev_info.external_rev = adev->external_rev_id; 592 dev_info.pci_rev = dev->pdev->revision; 593 dev_info.family = adev->family; 594 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 595 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 596 /* return all clocks in KHz */ 597 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 598 if (adev->pm.dpm_enabled) { 599 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 600 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 601 } else { 602 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 603 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 604 } 605 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 606 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 607 adev->gfx.config.max_shader_engines; 608 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 609 dev_info._pad = 0; 610 dev_info.ids_flags = 0; 611 if (adev->flags & AMD_IS_APU) 612 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 613 if (amdgpu_sriov_vf(adev)) 614 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 615 616 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 617 vm_size -= AMDGPU_VA_RESERVED_SIZE; 618 619 /* Older VCE FW versions are buggy and can handle only 40bits */ 620 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 621 vm_size = min(vm_size, 1ULL << 40); 622 623 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 624 dev_info.virtual_address_max = 625 min(vm_size, AMDGPU_VA_HOLE_START); 626 627 if (vm_size > AMDGPU_VA_HOLE_START) { 628 dev_info.high_va_offset = AMDGPU_VA_HOLE_END; 629 dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; 630 } 631 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 632 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 633 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 634 dev_info.cu_active_number = adev->gfx.cu_info.number; 635 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 636 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 637 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 638 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 639 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 640 sizeof(adev->gfx.cu_info.bitmap)); 641 dev_info.vram_type = adev->gmc.vram_type; 642 dev_info.vram_bit_width = adev->gmc.vram_width; 643 dev_info.vce_harvest_config = adev->vce.harvest_config; 644 dev_info.gc_double_offchip_lds_buf = 645 adev->gfx.config.double_offchip_lds_buf; 646 647 if (amdgpu_ngg) { 648 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 649 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 650 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 651 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 652 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 653 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 654 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 655 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 656 } 657 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 658 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 659 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 660 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 661 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 662 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 663 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 664 665 return copy_to_user(out, &dev_info, 666 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 667 } 668 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 669 unsigned i; 670 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 671 struct amd_vce_state *vce_state; 672 673 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 674 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 675 if (vce_state) { 676 vce_clk_table.entries[i].sclk = vce_state->sclk; 677 vce_clk_table.entries[i].mclk = vce_state->mclk; 678 vce_clk_table.entries[i].eclk = vce_state->evclk; 679 vce_clk_table.num_valid_entries++; 680 } 681 } 682 683 return copy_to_user(out, &vce_clk_table, 684 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 685 } 686 case AMDGPU_INFO_VBIOS: { 687 uint32_t bios_size = adev->bios_size; 688 689 switch (info->vbios_info.type) { 690 case AMDGPU_INFO_VBIOS_SIZE: 691 return copy_to_user(out, &bios_size, 692 min((size_t)size, sizeof(bios_size))) 693 ? -EFAULT : 0; 694 case AMDGPU_INFO_VBIOS_IMAGE: { 695 uint8_t *bios; 696 uint32_t bios_offset = info->vbios_info.offset; 697 698 if (bios_offset >= bios_size) 699 return -EINVAL; 700 701 bios = adev->bios + bios_offset; 702 return copy_to_user(out, bios, 703 min((size_t)size, (size_t)(bios_size - bios_offset))) 704 ? -EFAULT : 0; 705 } 706 default: 707 DRM_DEBUG_KMS("Invalid request %d\n", 708 info->vbios_info.type); 709 return -EINVAL; 710 } 711 } 712 case AMDGPU_INFO_NUM_HANDLES: { 713 struct drm_amdgpu_info_num_handles handle; 714 715 switch (info->query_hw_ip.type) { 716 case AMDGPU_HW_IP_UVD: 717 /* Starting Polaris, we support unlimited UVD handles */ 718 if (adev->asic_type < CHIP_POLARIS10) { 719 handle.uvd_max_handles = adev->uvd.max_handles; 720 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 721 722 return copy_to_user(out, &handle, 723 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 724 } else { 725 return -ENODATA; 726 } 727 728 break; 729 default: 730 return -EINVAL; 731 } 732 } 733 case AMDGPU_INFO_SENSOR: { 734 if (!adev->pm.dpm_enabled) 735 return -ENOENT; 736 737 switch (info->sensor_info.type) { 738 case AMDGPU_INFO_SENSOR_GFX_SCLK: 739 /* get sclk in Mhz */ 740 if (amdgpu_dpm_read_sensor(adev, 741 AMDGPU_PP_SENSOR_GFX_SCLK, 742 (void *)&ui32, &ui32_size)) { 743 return -EINVAL; 744 } 745 ui32 /= 100; 746 break; 747 case AMDGPU_INFO_SENSOR_GFX_MCLK: 748 /* get mclk in Mhz */ 749 if (amdgpu_dpm_read_sensor(adev, 750 AMDGPU_PP_SENSOR_GFX_MCLK, 751 (void *)&ui32, &ui32_size)) { 752 return -EINVAL; 753 } 754 ui32 /= 100; 755 break; 756 case AMDGPU_INFO_SENSOR_GPU_TEMP: 757 /* get temperature in millidegrees C */ 758 if (amdgpu_dpm_read_sensor(adev, 759 AMDGPU_PP_SENSOR_GPU_TEMP, 760 (void *)&ui32, &ui32_size)) { 761 return -EINVAL; 762 } 763 break; 764 case AMDGPU_INFO_SENSOR_GPU_LOAD: 765 /* get GPU load */ 766 if (amdgpu_dpm_read_sensor(adev, 767 AMDGPU_PP_SENSOR_GPU_LOAD, 768 (void *)&ui32, &ui32_size)) { 769 return -EINVAL; 770 } 771 break; 772 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 773 /* get average GPU power */ 774 if (amdgpu_dpm_read_sensor(adev, 775 AMDGPU_PP_SENSOR_GPU_POWER, 776 (void *)&ui32, &ui32_size)) { 777 return -EINVAL; 778 } 779 ui32 >>= 8; 780 break; 781 case AMDGPU_INFO_SENSOR_VDDNB: 782 /* get VDDNB in millivolts */ 783 if (amdgpu_dpm_read_sensor(adev, 784 AMDGPU_PP_SENSOR_VDDNB, 785 (void *)&ui32, &ui32_size)) { 786 return -EINVAL; 787 } 788 break; 789 case AMDGPU_INFO_SENSOR_VDDGFX: 790 /* get VDDGFX in millivolts */ 791 if (amdgpu_dpm_read_sensor(adev, 792 AMDGPU_PP_SENSOR_VDDGFX, 793 (void *)&ui32, &ui32_size)) { 794 return -EINVAL; 795 } 796 break; 797 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 798 /* get stable pstate sclk in Mhz */ 799 if (amdgpu_dpm_read_sensor(adev, 800 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 801 (void *)&ui32, &ui32_size)) { 802 return -EINVAL; 803 } 804 ui32 /= 100; 805 break; 806 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 807 /* get stable pstate mclk in Mhz */ 808 if (amdgpu_dpm_read_sensor(adev, 809 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 810 (void *)&ui32, &ui32_size)) { 811 return -EINVAL; 812 } 813 ui32 /= 100; 814 break; 815 default: 816 DRM_DEBUG_KMS("Invalid request %d\n", 817 info->sensor_info.type); 818 return -EINVAL; 819 } 820 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 821 } 822 case AMDGPU_INFO_VRAM_LOST_COUNTER: 823 ui32 = atomic_read(&adev->vram_lost_counter); 824 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 825 default: 826 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 827 return -EINVAL; 828 } 829 return 0; 830 } 831 832 833 /* 834 * Outdated mess for old drm with Xorg being in charge (void function now). 835 */ 836 /** 837 * amdgpu_driver_lastclose_kms - drm callback for last close 838 * 839 * @dev: drm dev pointer 840 * 841 * Switch vga_switcheroo state after last close (all asics). 842 */ 843 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 844 { 845 drm_fb_helper_lastclose(dev); 846 vga_switcheroo_process_delayed_switch(); 847 } 848 849 /** 850 * amdgpu_driver_open_kms - drm callback for open 851 * 852 * @dev: drm dev pointer 853 * @file_priv: drm file 854 * 855 * On device open, init vm on cayman+ (all asics). 856 * Returns 0 on success, error on failure. 857 */ 858 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 859 { 860 struct amdgpu_device *adev = dev->dev_private; 861 struct amdgpu_fpriv *fpriv; 862 int r, pasid; 863 864 file_priv->driver_priv = NULL; 865 866 r = pm_runtime_get_sync(dev->dev); 867 if (r < 0) 868 return r; 869 870 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 871 if (unlikely(!fpriv)) { 872 r = -ENOMEM; 873 goto out_suspend; 874 } 875 876 pasid = amdgpu_pasid_alloc(16); 877 if (pasid < 0) { 878 dev_warn(adev->dev, "No more PASIDs available!"); 879 pasid = 0; 880 } 881 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 882 if (r) 883 goto error_pasid; 884 885 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 886 if (!fpriv->prt_va) { 887 r = -ENOMEM; 888 goto error_vm; 889 } 890 891 if (amdgpu_sriov_vf(adev)) { 892 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); 893 if (r) 894 goto error_vm; 895 } 896 897 mutex_init(&fpriv->bo_list_lock); 898 idr_init(&fpriv->bo_list_handles); 899 900 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 901 902 file_priv->driver_priv = fpriv; 903 goto out_suspend; 904 905 error_vm: 906 amdgpu_vm_fini(adev, &fpriv->vm); 907 908 error_pasid: 909 if (pasid) 910 amdgpu_pasid_free(pasid); 911 912 kfree(fpriv); 913 914 out_suspend: 915 pm_runtime_mark_last_busy(dev->dev); 916 pm_runtime_put_autosuspend(dev->dev); 917 918 return r; 919 } 920 921 /** 922 * amdgpu_driver_postclose_kms - drm callback for post close 923 * 924 * @dev: drm dev pointer 925 * @file_priv: drm file 926 * 927 * On device post close, tear down vm on cayman+ (all asics). 928 */ 929 void amdgpu_driver_postclose_kms(struct drm_device *dev, 930 struct drm_file *file_priv) 931 { 932 struct amdgpu_device *adev = dev->dev_private; 933 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 934 struct amdgpu_bo_list *list; 935 struct amdgpu_bo *pd; 936 unsigned int pasid; 937 int handle; 938 939 if (!fpriv) 940 return; 941 942 pm_runtime_get_sync(dev->dev); 943 944 if (adev->asic_type != CHIP_RAVEN) { 945 amdgpu_uvd_free_handles(adev, file_priv); 946 amdgpu_vce_free_handles(adev, file_priv); 947 } 948 949 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 950 951 if (amdgpu_sriov_vf(adev)) { 952 /* TODO: how to handle reserve failure */ 953 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 954 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 955 fpriv->csa_va = NULL; 956 amdgpu_bo_unreserve(adev->virt.csa_obj); 957 } 958 959 pasid = fpriv->vm.pasid; 960 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 961 962 amdgpu_vm_fini(adev, &fpriv->vm); 963 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 964 965 if (pasid) 966 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); 967 amdgpu_bo_unref(&pd); 968 969 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 970 amdgpu_bo_list_put(list); 971 972 idr_destroy(&fpriv->bo_list_handles); 973 mutex_destroy(&fpriv->bo_list_lock); 974 975 kfree(fpriv); 976 file_priv->driver_priv = NULL; 977 978 pm_runtime_mark_last_busy(dev->dev); 979 pm_runtime_put_autosuspend(dev->dev); 980 } 981 982 /* 983 * VBlank related functions. 984 */ 985 /** 986 * amdgpu_get_vblank_counter_kms - get frame count 987 * 988 * @dev: drm dev pointer 989 * @pipe: crtc to get the frame count from 990 * 991 * Gets the frame count on the requested crtc (all asics). 992 * Returns frame count on success, -EINVAL on failure. 993 */ 994 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 995 { 996 struct amdgpu_device *adev = dev->dev_private; 997 int vpos, hpos, stat; 998 u32 count; 999 1000 if (pipe >= adev->mode_info.num_crtc) { 1001 DRM_ERROR("Invalid crtc %u\n", pipe); 1002 return -EINVAL; 1003 } 1004 1005 /* The hw increments its frame counter at start of vsync, not at start 1006 * of vblank, as is required by DRM core vblank counter handling. 1007 * Cook the hw count here to make it appear to the caller as if it 1008 * incremented at start of vblank. We measure distance to start of 1009 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1010 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1011 * result by 1 to give the proper appearance to caller. 1012 */ 1013 if (adev->mode_info.crtcs[pipe]) { 1014 /* Repeat readout if needed to provide stable result if 1015 * we cross start of vsync during the queries. 1016 */ 1017 do { 1018 count = amdgpu_display_vblank_get_counter(adev, pipe); 1019 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1020 * vpos as distance to start of vblank, instead of 1021 * regular vertical scanout pos. 1022 */ 1023 stat = amdgpu_display_get_crtc_scanoutpos( 1024 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1025 &vpos, &hpos, NULL, NULL, 1026 &adev->mode_info.crtcs[pipe]->base.hwmode); 1027 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1028 1029 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1030 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1031 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1032 } else { 1033 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1034 pipe, vpos); 1035 1036 /* Bump counter if we are at >= leading edge of vblank, 1037 * but before vsync where vpos would turn negative and 1038 * the hw counter really increments. 1039 */ 1040 if (vpos >= 0) 1041 count++; 1042 } 1043 } else { 1044 /* Fallback to use value as is. */ 1045 count = amdgpu_display_vblank_get_counter(adev, pipe); 1046 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1047 } 1048 1049 return count; 1050 } 1051 1052 /** 1053 * amdgpu_enable_vblank_kms - enable vblank interrupt 1054 * 1055 * @dev: drm dev pointer 1056 * @pipe: crtc to enable vblank interrupt for 1057 * 1058 * Enable the interrupt on the requested crtc (all asics). 1059 * Returns 0 on success, -EINVAL on failure. 1060 */ 1061 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1062 { 1063 struct amdgpu_device *adev = dev->dev_private; 1064 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1065 1066 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1067 } 1068 1069 /** 1070 * amdgpu_disable_vblank_kms - disable vblank interrupt 1071 * 1072 * @dev: drm dev pointer 1073 * @pipe: crtc to disable vblank interrupt for 1074 * 1075 * Disable the interrupt on the requested crtc (all asics). 1076 */ 1077 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1078 { 1079 struct amdgpu_device *adev = dev->dev_private; 1080 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1081 1082 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1083 } 1084 1085 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1086 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1087 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1088 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1089 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1090 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1091 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1092 /* KMS */ 1093 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1094 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1095 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1096 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1097 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1098 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1099 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1100 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1101 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1102 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1103 }; 1104 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1105 1106 /* 1107 * Debugfs info 1108 */ 1109 #if defined(CONFIG_DEBUG_FS) 1110 1111 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1112 { 1113 struct drm_info_node *node = (struct drm_info_node *) m->private; 1114 struct drm_device *dev = node->minor->dev; 1115 struct amdgpu_device *adev = dev->dev_private; 1116 struct drm_amdgpu_info_firmware fw_info; 1117 struct drm_amdgpu_query_fw query_fw; 1118 struct atom_context *ctx = adev->mode_info.atom_context; 1119 int ret, i; 1120 1121 /* VCE */ 1122 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1123 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1124 if (ret) 1125 return ret; 1126 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1127 fw_info.feature, fw_info.ver); 1128 1129 /* UVD */ 1130 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1131 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1132 if (ret) 1133 return ret; 1134 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1135 fw_info.feature, fw_info.ver); 1136 1137 /* GMC */ 1138 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1139 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1140 if (ret) 1141 return ret; 1142 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1143 fw_info.feature, fw_info.ver); 1144 1145 /* ME */ 1146 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1147 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1148 if (ret) 1149 return ret; 1150 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1151 fw_info.feature, fw_info.ver); 1152 1153 /* PFP */ 1154 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1155 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1156 if (ret) 1157 return ret; 1158 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1159 fw_info.feature, fw_info.ver); 1160 1161 /* CE */ 1162 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1163 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1164 if (ret) 1165 return ret; 1166 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1167 fw_info.feature, fw_info.ver); 1168 1169 /* RLC */ 1170 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1171 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1172 if (ret) 1173 return ret; 1174 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1175 fw_info.feature, fw_info.ver); 1176 1177 /* RLC SAVE RESTORE LIST CNTL */ 1178 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1179 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1180 if (ret) 1181 return ret; 1182 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1183 fw_info.feature, fw_info.ver); 1184 1185 /* RLC SAVE RESTORE LIST GPM MEM */ 1186 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1187 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1188 if (ret) 1189 return ret; 1190 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1191 fw_info.feature, fw_info.ver); 1192 1193 /* RLC SAVE RESTORE LIST SRM MEM */ 1194 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1195 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1196 if (ret) 1197 return ret; 1198 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1199 fw_info.feature, fw_info.ver); 1200 1201 /* MEC */ 1202 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1203 query_fw.index = 0; 1204 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1205 if (ret) 1206 return ret; 1207 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1208 fw_info.feature, fw_info.ver); 1209 1210 /* MEC2 */ 1211 if (adev->asic_type == CHIP_KAVERI || 1212 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1213 query_fw.index = 1; 1214 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1215 if (ret) 1216 return ret; 1217 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1218 fw_info.feature, fw_info.ver); 1219 } 1220 1221 /* PSP SOS */ 1222 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1223 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1224 if (ret) 1225 return ret; 1226 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1227 fw_info.feature, fw_info.ver); 1228 1229 1230 /* PSP ASD */ 1231 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1232 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1233 if (ret) 1234 return ret; 1235 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1236 fw_info.feature, fw_info.ver); 1237 1238 /* SMC */ 1239 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1240 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1241 if (ret) 1242 return ret; 1243 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1244 fw_info.feature, fw_info.ver); 1245 1246 /* SDMA */ 1247 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1248 for (i = 0; i < adev->sdma.num_instances; i++) { 1249 query_fw.index = i; 1250 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1251 if (ret) 1252 return ret; 1253 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1254 i, fw_info.feature, fw_info.ver); 1255 } 1256 1257 /* VCN */ 1258 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1259 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1260 if (ret) 1261 return ret; 1262 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1263 fw_info.feature, fw_info.ver); 1264 1265 1266 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1267 1268 return 0; 1269 } 1270 1271 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1272 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1273 }; 1274 #endif 1275 1276 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1277 { 1278 #if defined(CONFIG_DEBUG_FS) 1279 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1280 ARRAY_SIZE(amdgpu_firmware_info_list)); 1281 #else 1282 return 0; 1283 #endif 1284 } 1285