1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_sched.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 35 #include <linux/vga_switcheroo.h> 36 #include <linux/slab.h> 37 #include <linux/pm_runtime.h> 38 #include "amdgpu_amdkfd.h" 39 40 /** 41 * amdgpu_driver_unload_kms - Main unload function for KMS. 42 * 43 * @dev: drm dev pointer 44 * 45 * This is the main unload function for KMS (all asics). 46 * Returns 0 on success. 47 */ 48 void amdgpu_driver_unload_kms(struct drm_device *dev) 49 { 50 struct amdgpu_device *adev = dev->dev_private; 51 52 if (adev == NULL) 53 return; 54 55 if (adev->rmmio == NULL) 56 goto done_free; 57 58 if (amdgpu_sriov_vf(adev)) 59 amdgpu_virt_request_full_gpu(adev, false); 60 61 if (amdgpu_device_is_px(dev)) { 62 pm_runtime_get_sync(dev->dev); 63 pm_runtime_forbid(dev->dev); 64 } 65 66 amdgpu_amdkfd_device_fini(adev); 67 68 amdgpu_acpi_fini(adev); 69 70 amdgpu_device_fini(adev); 71 72 done_free: 73 kfree(adev); 74 dev->dev_private = NULL; 75 } 76 77 /** 78 * amdgpu_driver_load_kms - Main load function for KMS. 79 * 80 * @dev: drm dev pointer 81 * @flags: device flags 82 * 83 * This is the main load function for KMS (all asics). 84 * Returns 0 on success, error on failure. 85 */ 86 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 87 { 88 struct amdgpu_device *adev; 89 int r, acpi_status; 90 91 #ifdef CONFIG_DRM_AMDGPU_SI 92 if (!amdgpu_si_support) { 93 switch (flags & AMD_ASIC_MASK) { 94 case CHIP_TAHITI: 95 case CHIP_PITCAIRN: 96 case CHIP_VERDE: 97 case CHIP_OLAND: 98 case CHIP_HAINAN: 99 dev_info(dev->dev, 100 "SI support provided by radeon.\n"); 101 dev_info(dev->dev, 102 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 103 ); 104 return -ENODEV; 105 } 106 } 107 #endif 108 #ifdef CONFIG_DRM_AMDGPU_CIK 109 if (!amdgpu_cik_support) { 110 switch (flags & AMD_ASIC_MASK) { 111 case CHIP_KAVERI: 112 case CHIP_BONAIRE: 113 case CHIP_HAWAII: 114 case CHIP_KABINI: 115 case CHIP_MULLINS: 116 dev_info(dev->dev, 117 "CIK support provided by radeon.\n"); 118 dev_info(dev->dev, 119 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 120 ); 121 return -ENODEV; 122 } 123 } 124 #endif 125 126 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 127 if (adev == NULL) { 128 return -ENOMEM; 129 } 130 dev->dev_private = (void *)adev; 131 132 if ((amdgpu_runtime_pm != 0) && 133 amdgpu_has_atpx() && 134 (amdgpu_is_atpx_hybrid() || 135 amdgpu_has_atpx_dgpu_power_cntl()) && 136 ((flags & AMD_IS_APU) == 0) && 137 !pci_is_thunderbolt_attached(dev->pdev)) 138 flags |= AMD_IS_PX; 139 140 /* amdgpu_device_init should report only fatal error 141 * like memory allocation failure or iomapping failure, 142 * or memory manager initialization failure, it must 143 * properly initialize the GPU MC controller and permit 144 * VRAM allocation 145 */ 146 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 147 if (r) { 148 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 149 goto out; 150 } 151 152 /* Call ACPI methods: require modeset init 153 * but failure is not fatal 154 */ 155 if (!r) { 156 acpi_status = amdgpu_acpi_init(adev); 157 if (acpi_status) 158 dev_dbg(&dev->pdev->dev, 159 "Error during ACPI methods call\n"); 160 } 161 162 amdgpu_amdkfd_device_probe(adev); 163 amdgpu_amdkfd_device_init(adev); 164 165 if (amdgpu_device_is_px(dev)) { 166 pm_runtime_use_autosuspend(dev->dev); 167 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 168 pm_runtime_set_active(dev->dev); 169 pm_runtime_allow(dev->dev); 170 pm_runtime_mark_last_busy(dev->dev); 171 pm_runtime_put_autosuspend(dev->dev); 172 } 173 174 if (amdgpu_sriov_vf(adev)) 175 amdgpu_virt_release_full_gpu(adev, true); 176 177 out: 178 if (r) { 179 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 180 if (adev->rmmio && amdgpu_device_is_px(dev)) 181 pm_runtime_put_noidle(dev->dev); 182 amdgpu_driver_unload_kms(dev); 183 } 184 185 return r; 186 } 187 188 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 189 struct drm_amdgpu_query_fw *query_fw, 190 struct amdgpu_device *adev) 191 { 192 switch (query_fw->fw_type) { 193 case AMDGPU_INFO_FW_VCE: 194 fw_info->ver = adev->vce.fw_version; 195 fw_info->feature = adev->vce.fb_version; 196 break; 197 case AMDGPU_INFO_FW_UVD: 198 fw_info->ver = adev->uvd.fw_version; 199 fw_info->feature = 0; 200 break; 201 case AMDGPU_INFO_FW_GMC: 202 fw_info->ver = adev->mc.fw_version; 203 fw_info->feature = 0; 204 break; 205 case AMDGPU_INFO_FW_GFX_ME: 206 fw_info->ver = adev->gfx.me_fw_version; 207 fw_info->feature = adev->gfx.me_feature_version; 208 break; 209 case AMDGPU_INFO_FW_GFX_PFP: 210 fw_info->ver = adev->gfx.pfp_fw_version; 211 fw_info->feature = adev->gfx.pfp_feature_version; 212 break; 213 case AMDGPU_INFO_FW_GFX_CE: 214 fw_info->ver = adev->gfx.ce_fw_version; 215 fw_info->feature = adev->gfx.ce_feature_version; 216 break; 217 case AMDGPU_INFO_FW_GFX_RLC: 218 fw_info->ver = adev->gfx.rlc_fw_version; 219 fw_info->feature = adev->gfx.rlc_feature_version; 220 break; 221 case AMDGPU_INFO_FW_GFX_MEC: 222 if (query_fw->index == 0) { 223 fw_info->ver = adev->gfx.mec_fw_version; 224 fw_info->feature = adev->gfx.mec_feature_version; 225 } else if (query_fw->index == 1) { 226 fw_info->ver = adev->gfx.mec2_fw_version; 227 fw_info->feature = adev->gfx.mec2_feature_version; 228 } else 229 return -EINVAL; 230 break; 231 case AMDGPU_INFO_FW_SMC: 232 fw_info->ver = adev->pm.fw_version; 233 fw_info->feature = 0; 234 break; 235 case AMDGPU_INFO_FW_SDMA: 236 if (query_fw->index >= adev->sdma.num_instances) 237 return -EINVAL; 238 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 239 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 240 break; 241 case AMDGPU_INFO_FW_SOS: 242 fw_info->ver = adev->psp.sos_fw_version; 243 fw_info->feature = adev->psp.sos_feature_version; 244 break; 245 case AMDGPU_INFO_FW_ASD: 246 fw_info->ver = adev->psp.asd_fw_version; 247 fw_info->feature = adev->psp.asd_feature_version; 248 break; 249 default: 250 return -EINVAL; 251 } 252 return 0; 253 } 254 255 /* 256 * Userspace get information ioctl 257 */ 258 /** 259 * amdgpu_info_ioctl - answer a device specific request. 260 * 261 * @adev: amdgpu device pointer 262 * @data: request object 263 * @filp: drm filp 264 * 265 * This function is used to pass device specific parameters to the userspace 266 * drivers. Examples include: pci device id, pipeline parms, tiling params, 267 * etc. (all asics). 268 * Returns 0 on success, -EINVAL on failure. 269 */ 270 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 271 { 272 struct amdgpu_device *adev = dev->dev_private; 273 struct drm_amdgpu_info *info = data; 274 struct amdgpu_mode_info *minfo = &adev->mode_info; 275 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 276 uint32_t size = info->return_size; 277 struct drm_crtc *crtc; 278 uint32_t ui32 = 0; 279 uint64_t ui64 = 0; 280 int i, found; 281 int ui32_size = sizeof(ui32); 282 283 if (!info->return_size || !info->return_pointer) 284 return -EINVAL; 285 286 switch (info->query) { 287 case AMDGPU_INFO_ACCEL_WORKING: 288 ui32 = adev->accel_working; 289 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 290 case AMDGPU_INFO_CRTC_FROM_ID: 291 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 292 crtc = (struct drm_crtc *)minfo->crtcs[i]; 293 if (crtc && crtc->base.id == info->mode_crtc.id) { 294 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 295 ui32 = amdgpu_crtc->crtc_id; 296 found = 1; 297 break; 298 } 299 } 300 if (!found) { 301 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 302 return -EINVAL; 303 } 304 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 305 case AMDGPU_INFO_HW_IP_INFO: { 306 struct drm_amdgpu_info_hw_ip ip = {}; 307 enum amd_ip_block_type type; 308 uint32_t ring_mask = 0; 309 uint32_t ib_start_alignment = 0; 310 uint32_t ib_size_alignment = 0; 311 312 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 313 return -EINVAL; 314 315 switch (info->query_hw_ip.type) { 316 case AMDGPU_HW_IP_GFX: 317 type = AMD_IP_BLOCK_TYPE_GFX; 318 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 319 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 320 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 321 ib_size_alignment = 8; 322 break; 323 case AMDGPU_HW_IP_COMPUTE: 324 type = AMD_IP_BLOCK_TYPE_GFX; 325 for (i = 0; i < adev->gfx.num_compute_rings; i++) 326 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 327 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 328 ib_size_alignment = 8; 329 break; 330 case AMDGPU_HW_IP_DMA: 331 type = AMD_IP_BLOCK_TYPE_SDMA; 332 for (i = 0; i < adev->sdma.num_instances; i++) 333 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 334 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 335 ib_size_alignment = 1; 336 break; 337 case AMDGPU_HW_IP_UVD: 338 type = AMD_IP_BLOCK_TYPE_UVD; 339 ring_mask = adev->uvd.ring.ready ? 1 : 0; 340 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 341 ib_size_alignment = 16; 342 break; 343 case AMDGPU_HW_IP_VCE: 344 type = AMD_IP_BLOCK_TYPE_VCE; 345 for (i = 0; i < adev->vce.num_rings; i++) 346 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 347 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 348 ib_size_alignment = 1; 349 break; 350 case AMDGPU_HW_IP_UVD_ENC: 351 type = AMD_IP_BLOCK_TYPE_UVD; 352 for (i = 0; i < adev->uvd.num_enc_rings; i++) 353 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); 354 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 355 ib_size_alignment = 1; 356 break; 357 case AMDGPU_HW_IP_VCN_DEC: 358 type = AMD_IP_BLOCK_TYPE_VCN; 359 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; 360 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 361 ib_size_alignment = 16; 362 break; 363 case AMDGPU_HW_IP_VCN_ENC: 364 type = AMD_IP_BLOCK_TYPE_VCN; 365 for (i = 0; i < adev->vcn.num_enc_rings; i++) 366 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); 367 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 368 ib_size_alignment = 1; 369 break; 370 default: 371 return -EINVAL; 372 } 373 374 for (i = 0; i < adev->num_ip_blocks; i++) { 375 if (adev->ip_blocks[i].version->type == type && 376 adev->ip_blocks[i].status.valid) { 377 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 378 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 379 ip.capabilities_flags = 0; 380 ip.available_rings = ring_mask; 381 ip.ib_start_alignment = ib_start_alignment; 382 ip.ib_size_alignment = ib_size_alignment; 383 break; 384 } 385 } 386 return copy_to_user(out, &ip, 387 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 388 } 389 case AMDGPU_INFO_HW_IP_COUNT: { 390 enum amd_ip_block_type type; 391 uint32_t count = 0; 392 393 switch (info->query_hw_ip.type) { 394 case AMDGPU_HW_IP_GFX: 395 type = AMD_IP_BLOCK_TYPE_GFX; 396 break; 397 case AMDGPU_HW_IP_COMPUTE: 398 type = AMD_IP_BLOCK_TYPE_GFX; 399 break; 400 case AMDGPU_HW_IP_DMA: 401 type = AMD_IP_BLOCK_TYPE_SDMA; 402 break; 403 case AMDGPU_HW_IP_UVD: 404 type = AMD_IP_BLOCK_TYPE_UVD; 405 break; 406 case AMDGPU_HW_IP_VCE: 407 type = AMD_IP_BLOCK_TYPE_VCE; 408 break; 409 case AMDGPU_HW_IP_UVD_ENC: 410 type = AMD_IP_BLOCK_TYPE_UVD; 411 break; 412 case AMDGPU_HW_IP_VCN_DEC: 413 case AMDGPU_HW_IP_VCN_ENC: 414 type = AMD_IP_BLOCK_TYPE_VCN; 415 break; 416 default: 417 return -EINVAL; 418 } 419 420 for (i = 0; i < adev->num_ip_blocks; i++) 421 if (adev->ip_blocks[i].version->type == type && 422 adev->ip_blocks[i].status.valid && 423 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 424 count++; 425 426 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 427 } 428 case AMDGPU_INFO_TIMESTAMP: 429 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 430 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 431 case AMDGPU_INFO_FW_VERSION: { 432 struct drm_amdgpu_info_firmware fw_info; 433 int ret; 434 435 /* We only support one instance of each IP block right now. */ 436 if (info->query_fw.ip_instance != 0) 437 return -EINVAL; 438 439 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 440 if (ret) 441 return ret; 442 443 return copy_to_user(out, &fw_info, 444 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 445 } 446 case AMDGPU_INFO_NUM_BYTES_MOVED: 447 ui64 = atomic64_read(&adev->num_bytes_moved); 448 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 449 case AMDGPU_INFO_NUM_EVICTIONS: 450 ui64 = atomic64_read(&adev->num_evictions); 451 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 452 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 453 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 454 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 455 case AMDGPU_INFO_VRAM_USAGE: 456 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 457 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 458 case AMDGPU_INFO_VIS_VRAM_USAGE: 459 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 460 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 461 case AMDGPU_INFO_GTT_USAGE: 462 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 463 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 464 case AMDGPU_INFO_GDS_CONFIG: { 465 struct drm_amdgpu_info_gds gds_info; 466 467 memset(&gds_info, 0, sizeof(gds_info)); 468 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 469 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 470 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 471 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 472 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 473 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 474 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 475 return copy_to_user(out, &gds_info, 476 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 477 } 478 case AMDGPU_INFO_VRAM_GTT: { 479 struct drm_amdgpu_info_vram_gtt vram_gtt; 480 481 vram_gtt.vram_size = adev->mc.real_vram_size; 482 vram_gtt.vram_size -= adev->vram_pin_size; 483 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 484 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 485 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 486 vram_gtt.gtt_size *= PAGE_SIZE; 487 vram_gtt.gtt_size -= adev->gart_pin_size; 488 return copy_to_user(out, &vram_gtt, 489 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 490 } 491 case AMDGPU_INFO_MEMORY: { 492 struct drm_amdgpu_memory_info mem; 493 494 memset(&mem, 0, sizeof(mem)); 495 mem.vram.total_heap_size = adev->mc.real_vram_size; 496 mem.vram.usable_heap_size = 497 adev->mc.real_vram_size - adev->vram_pin_size; 498 mem.vram.heap_usage = 499 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 500 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 501 502 mem.cpu_accessible_vram.total_heap_size = 503 adev->mc.visible_vram_size; 504 mem.cpu_accessible_vram.usable_heap_size = 505 adev->mc.visible_vram_size - 506 (adev->vram_pin_size - adev->invisible_pin_size); 507 mem.cpu_accessible_vram.heap_usage = 508 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 509 mem.cpu_accessible_vram.max_allocation = 510 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 511 512 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 513 mem.gtt.total_heap_size *= PAGE_SIZE; 514 mem.gtt.usable_heap_size = mem.gtt.total_heap_size 515 - adev->gart_pin_size; 516 mem.gtt.heap_usage = 517 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 518 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 519 520 return copy_to_user(out, &mem, 521 min((size_t)size, sizeof(mem))) 522 ? -EFAULT : 0; 523 } 524 case AMDGPU_INFO_READ_MMR_REG: { 525 unsigned n, alloc_size; 526 uint32_t *regs; 527 unsigned se_num = (info->read_mmr_reg.instance >> 528 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 529 AMDGPU_INFO_MMR_SE_INDEX_MASK; 530 unsigned sh_num = (info->read_mmr_reg.instance >> 531 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 532 AMDGPU_INFO_MMR_SH_INDEX_MASK; 533 534 /* set full masks if the userspace set all bits 535 * in the bitfields */ 536 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 537 se_num = 0xffffffff; 538 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 539 sh_num = 0xffffffff; 540 541 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 542 if (!regs) 543 return -ENOMEM; 544 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 545 546 for (i = 0; i < info->read_mmr_reg.count; i++) 547 if (amdgpu_asic_read_register(adev, se_num, sh_num, 548 info->read_mmr_reg.dword_offset + i, 549 ®s[i])) { 550 DRM_DEBUG_KMS("unallowed offset %#x\n", 551 info->read_mmr_reg.dword_offset + i); 552 kfree(regs); 553 return -EFAULT; 554 } 555 n = copy_to_user(out, regs, min(size, alloc_size)); 556 kfree(regs); 557 return n ? -EFAULT : 0; 558 } 559 case AMDGPU_INFO_DEV_INFO: { 560 struct drm_amdgpu_info_device dev_info = {}; 561 562 dev_info.device_id = dev->pdev->device; 563 dev_info.chip_rev = adev->rev_id; 564 dev_info.external_rev = adev->external_rev_id; 565 dev_info.pci_rev = dev->pdev->revision; 566 dev_info.family = adev->family; 567 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 568 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 569 /* return all clocks in KHz */ 570 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 571 if (adev->pm.dpm_enabled) { 572 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 573 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 574 } else { 575 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 576 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 577 } 578 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 579 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 580 adev->gfx.config.max_shader_engines; 581 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 582 dev_info._pad = 0; 583 dev_info.ids_flags = 0; 584 if (adev->flags & AMD_IS_APU) 585 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 586 if (amdgpu_sriov_vf(adev)) 587 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 588 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 589 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 590 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 591 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 592 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 593 dev_info.cu_active_number = adev->gfx.cu_info.number; 594 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 595 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 596 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 597 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 598 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 599 sizeof(adev->gfx.cu_info.bitmap)); 600 dev_info.vram_type = adev->mc.vram_type; 601 dev_info.vram_bit_width = adev->mc.vram_width; 602 dev_info.vce_harvest_config = adev->vce.harvest_config; 603 dev_info.gc_double_offchip_lds_buf = 604 adev->gfx.config.double_offchip_lds_buf; 605 606 if (amdgpu_ngg) { 607 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 608 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 609 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 610 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 611 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 612 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 613 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 614 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 615 } 616 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 617 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 618 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 619 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 620 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 621 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 622 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 623 624 return copy_to_user(out, &dev_info, 625 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 626 } 627 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 628 unsigned i; 629 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 630 struct amd_vce_state *vce_state; 631 632 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 633 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 634 if (vce_state) { 635 vce_clk_table.entries[i].sclk = vce_state->sclk; 636 vce_clk_table.entries[i].mclk = vce_state->mclk; 637 vce_clk_table.entries[i].eclk = vce_state->evclk; 638 vce_clk_table.num_valid_entries++; 639 } 640 } 641 642 return copy_to_user(out, &vce_clk_table, 643 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 644 } 645 case AMDGPU_INFO_VBIOS: { 646 uint32_t bios_size = adev->bios_size; 647 648 switch (info->vbios_info.type) { 649 case AMDGPU_INFO_VBIOS_SIZE: 650 return copy_to_user(out, &bios_size, 651 min((size_t)size, sizeof(bios_size))) 652 ? -EFAULT : 0; 653 case AMDGPU_INFO_VBIOS_IMAGE: { 654 uint8_t *bios; 655 uint32_t bios_offset = info->vbios_info.offset; 656 657 if (bios_offset >= bios_size) 658 return -EINVAL; 659 660 bios = adev->bios + bios_offset; 661 return copy_to_user(out, bios, 662 min((size_t)size, (size_t)(bios_size - bios_offset))) 663 ? -EFAULT : 0; 664 } 665 default: 666 DRM_DEBUG_KMS("Invalid request %d\n", 667 info->vbios_info.type); 668 return -EINVAL; 669 } 670 } 671 case AMDGPU_INFO_NUM_HANDLES: { 672 struct drm_amdgpu_info_num_handles handle; 673 674 switch (info->query_hw_ip.type) { 675 case AMDGPU_HW_IP_UVD: 676 /* Starting Polaris, we support unlimited UVD handles */ 677 if (adev->asic_type < CHIP_POLARIS10) { 678 handle.uvd_max_handles = adev->uvd.max_handles; 679 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 680 681 return copy_to_user(out, &handle, 682 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 683 } else { 684 return -ENODATA; 685 } 686 687 break; 688 default: 689 return -EINVAL; 690 } 691 } 692 case AMDGPU_INFO_SENSOR: { 693 struct pp_gpu_power query = {0}; 694 int query_size = sizeof(query); 695 696 if (amdgpu_dpm == 0) 697 return -ENOENT; 698 699 switch (info->sensor_info.type) { 700 case AMDGPU_INFO_SENSOR_GFX_SCLK: 701 /* get sclk in Mhz */ 702 if (amdgpu_dpm_read_sensor(adev, 703 AMDGPU_PP_SENSOR_GFX_SCLK, 704 (void *)&ui32, &ui32_size)) { 705 return -EINVAL; 706 } 707 ui32 /= 100; 708 break; 709 case AMDGPU_INFO_SENSOR_GFX_MCLK: 710 /* get mclk in Mhz */ 711 if (amdgpu_dpm_read_sensor(adev, 712 AMDGPU_PP_SENSOR_GFX_MCLK, 713 (void *)&ui32, &ui32_size)) { 714 return -EINVAL; 715 } 716 ui32 /= 100; 717 break; 718 case AMDGPU_INFO_SENSOR_GPU_TEMP: 719 /* get temperature in millidegrees C */ 720 if (amdgpu_dpm_read_sensor(adev, 721 AMDGPU_PP_SENSOR_GPU_TEMP, 722 (void *)&ui32, &ui32_size)) { 723 return -EINVAL; 724 } 725 break; 726 case AMDGPU_INFO_SENSOR_GPU_LOAD: 727 /* get GPU load */ 728 if (amdgpu_dpm_read_sensor(adev, 729 AMDGPU_PP_SENSOR_GPU_LOAD, 730 (void *)&ui32, &ui32_size)) { 731 return -EINVAL; 732 } 733 break; 734 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 735 /* get average GPU power */ 736 if (amdgpu_dpm_read_sensor(adev, 737 AMDGPU_PP_SENSOR_GPU_POWER, 738 (void *)&query, &query_size)) { 739 return -EINVAL; 740 } 741 ui32 = query.average_gpu_power >> 8; 742 break; 743 case AMDGPU_INFO_SENSOR_VDDNB: 744 /* get VDDNB in millivolts */ 745 if (amdgpu_dpm_read_sensor(adev, 746 AMDGPU_PP_SENSOR_VDDNB, 747 (void *)&ui32, &ui32_size)) { 748 return -EINVAL; 749 } 750 break; 751 case AMDGPU_INFO_SENSOR_VDDGFX: 752 /* get VDDGFX in millivolts */ 753 if (amdgpu_dpm_read_sensor(adev, 754 AMDGPU_PP_SENSOR_VDDGFX, 755 (void *)&ui32, &ui32_size)) { 756 return -EINVAL; 757 } 758 break; 759 default: 760 DRM_DEBUG_KMS("Invalid request %d\n", 761 info->sensor_info.type); 762 return -EINVAL; 763 } 764 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 765 } 766 case AMDGPU_INFO_VRAM_LOST_COUNTER: 767 ui32 = atomic_read(&adev->vram_lost_counter); 768 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 769 default: 770 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 771 return -EINVAL; 772 } 773 return 0; 774 } 775 776 777 /* 778 * Outdated mess for old drm with Xorg being in charge (void function now). 779 */ 780 /** 781 * amdgpu_driver_lastclose_kms - drm callback for last close 782 * 783 * @dev: drm dev pointer 784 * 785 * Switch vga_switcheroo state after last close (all asics). 786 */ 787 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 788 { 789 struct amdgpu_device *adev = dev->dev_private; 790 791 amdgpu_fbdev_restore_mode(adev); 792 vga_switcheroo_process_delayed_switch(); 793 } 794 795 /** 796 * amdgpu_driver_open_kms - drm callback for open 797 * 798 * @dev: drm dev pointer 799 * @file_priv: drm file 800 * 801 * On device open, init vm on cayman+ (all asics). 802 * Returns 0 on success, error on failure. 803 */ 804 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 805 { 806 struct amdgpu_device *adev = dev->dev_private; 807 struct amdgpu_fpriv *fpriv; 808 int r; 809 810 file_priv->driver_priv = NULL; 811 812 r = pm_runtime_get_sync(dev->dev); 813 if (r < 0) 814 return r; 815 816 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 817 if (unlikely(!fpriv)) { 818 r = -ENOMEM; 819 goto out_suspend; 820 } 821 822 r = amdgpu_vm_init(adev, &fpriv->vm, 823 AMDGPU_VM_CONTEXT_GFX, 0); 824 if (r) { 825 kfree(fpriv); 826 goto out_suspend; 827 } 828 829 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 830 if (!fpriv->prt_va) { 831 r = -ENOMEM; 832 amdgpu_vm_fini(adev, &fpriv->vm); 833 kfree(fpriv); 834 goto out_suspend; 835 } 836 837 if (amdgpu_sriov_vf(adev)) { 838 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); 839 if (r) { 840 amdgpu_vm_fini(adev, &fpriv->vm); 841 kfree(fpriv); 842 goto out_suspend; 843 } 844 } 845 846 mutex_init(&fpriv->bo_list_lock); 847 idr_init(&fpriv->bo_list_handles); 848 849 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 850 851 file_priv->driver_priv = fpriv; 852 853 out_suspend: 854 pm_runtime_mark_last_busy(dev->dev); 855 pm_runtime_put_autosuspend(dev->dev); 856 857 return r; 858 } 859 860 /** 861 * amdgpu_driver_postclose_kms - drm callback for post close 862 * 863 * @dev: drm dev pointer 864 * @file_priv: drm file 865 * 866 * On device post close, tear down vm on cayman+ (all asics). 867 */ 868 void amdgpu_driver_postclose_kms(struct drm_device *dev, 869 struct drm_file *file_priv) 870 { 871 struct amdgpu_device *adev = dev->dev_private; 872 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 873 struct amdgpu_bo_list *list; 874 int handle; 875 876 if (!fpriv) 877 return; 878 879 pm_runtime_get_sync(dev->dev); 880 881 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 882 883 if (adev->asic_type != CHIP_RAVEN) { 884 amdgpu_uvd_free_handles(adev, file_priv); 885 amdgpu_vce_free_handles(adev, file_priv); 886 } 887 888 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 889 890 if (amdgpu_sriov_vf(adev)) { 891 /* TODO: how to handle reserve failure */ 892 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 893 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 894 fpriv->csa_va = NULL; 895 amdgpu_bo_unreserve(adev->virt.csa_obj); 896 } 897 898 amdgpu_vm_fini(adev, &fpriv->vm); 899 900 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 901 amdgpu_bo_list_free(list); 902 903 idr_destroy(&fpriv->bo_list_handles); 904 mutex_destroy(&fpriv->bo_list_lock); 905 906 kfree(fpriv); 907 file_priv->driver_priv = NULL; 908 909 pm_runtime_mark_last_busy(dev->dev); 910 pm_runtime_put_autosuspend(dev->dev); 911 } 912 913 /* 914 * VBlank related functions. 915 */ 916 /** 917 * amdgpu_get_vblank_counter_kms - get frame count 918 * 919 * @dev: drm dev pointer 920 * @pipe: crtc to get the frame count from 921 * 922 * Gets the frame count on the requested crtc (all asics). 923 * Returns frame count on success, -EINVAL on failure. 924 */ 925 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 926 { 927 struct amdgpu_device *adev = dev->dev_private; 928 int vpos, hpos, stat; 929 u32 count; 930 931 if (pipe >= adev->mode_info.num_crtc) { 932 DRM_ERROR("Invalid crtc %u\n", pipe); 933 return -EINVAL; 934 } 935 936 /* The hw increments its frame counter at start of vsync, not at start 937 * of vblank, as is required by DRM core vblank counter handling. 938 * Cook the hw count here to make it appear to the caller as if it 939 * incremented at start of vblank. We measure distance to start of 940 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 941 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 942 * result by 1 to give the proper appearance to caller. 943 */ 944 if (adev->mode_info.crtcs[pipe]) { 945 /* Repeat readout if needed to provide stable result if 946 * we cross start of vsync during the queries. 947 */ 948 do { 949 count = amdgpu_display_vblank_get_counter(adev, pipe); 950 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 951 * distance to start of vblank, instead of regular 952 * vertical scanout pos. 953 */ 954 stat = amdgpu_get_crtc_scanoutpos( 955 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 956 &vpos, &hpos, NULL, NULL, 957 &adev->mode_info.crtcs[pipe]->base.hwmode); 958 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 959 960 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 961 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 962 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 963 } else { 964 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 965 pipe, vpos); 966 967 /* Bump counter if we are at >= leading edge of vblank, 968 * but before vsync where vpos would turn negative and 969 * the hw counter really increments. 970 */ 971 if (vpos >= 0) 972 count++; 973 } 974 } else { 975 /* Fallback to use value as is. */ 976 count = amdgpu_display_vblank_get_counter(adev, pipe); 977 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 978 } 979 980 return count; 981 } 982 983 /** 984 * amdgpu_enable_vblank_kms - enable vblank interrupt 985 * 986 * @dev: drm dev pointer 987 * @pipe: crtc to enable vblank interrupt for 988 * 989 * Enable the interrupt on the requested crtc (all asics). 990 * Returns 0 on success, -EINVAL on failure. 991 */ 992 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 993 { 994 struct amdgpu_device *adev = dev->dev_private; 995 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 996 997 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 998 } 999 1000 /** 1001 * amdgpu_disable_vblank_kms - disable vblank interrupt 1002 * 1003 * @dev: drm dev pointer 1004 * @pipe: crtc to disable vblank interrupt for 1005 * 1006 * Disable the interrupt on the requested crtc (all asics). 1007 */ 1008 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1009 { 1010 struct amdgpu_device *adev = dev->dev_private; 1011 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 1012 1013 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1014 } 1015 1016 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1017 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1018 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1019 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1020 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1021 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1022 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1023 /* KMS */ 1024 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1025 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1026 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1027 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1028 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1029 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1030 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1031 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1032 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1033 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1034 }; 1035 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1036 1037 /* 1038 * Debugfs info 1039 */ 1040 #if defined(CONFIG_DEBUG_FS) 1041 1042 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1043 { 1044 struct drm_info_node *node = (struct drm_info_node *) m->private; 1045 struct drm_device *dev = node->minor->dev; 1046 struct amdgpu_device *adev = dev->dev_private; 1047 struct drm_amdgpu_info_firmware fw_info; 1048 struct drm_amdgpu_query_fw query_fw; 1049 int ret, i; 1050 1051 /* VCE */ 1052 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1053 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1054 if (ret) 1055 return ret; 1056 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1057 fw_info.feature, fw_info.ver); 1058 1059 /* UVD */ 1060 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1061 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1062 if (ret) 1063 return ret; 1064 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1065 fw_info.feature, fw_info.ver); 1066 1067 /* GMC */ 1068 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1069 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1070 if (ret) 1071 return ret; 1072 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1073 fw_info.feature, fw_info.ver); 1074 1075 /* ME */ 1076 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1077 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1078 if (ret) 1079 return ret; 1080 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1081 fw_info.feature, fw_info.ver); 1082 1083 /* PFP */ 1084 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1085 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1086 if (ret) 1087 return ret; 1088 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1089 fw_info.feature, fw_info.ver); 1090 1091 /* CE */ 1092 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1093 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1094 if (ret) 1095 return ret; 1096 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1097 fw_info.feature, fw_info.ver); 1098 1099 /* RLC */ 1100 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1101 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1102 if (ret) 1103 return ret; 1104 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1105 fw_info.feature, fw_info.ver); 1106 1107 /* MEC */ 1108 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1109 query_fw.index = 0; 1110 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1111 if (ret) 1112 return ret; 1113 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1114 fw_info.feature, fw_info.ver); 1115 1116 /* MEC2 */ 1117 if (adev->asic_type == CHIP_KAVERI || 1118 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1119 query_fw.index = 1; 1120 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1121 if (ret) 1122 return ret; 1123 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1124 fw_info.feature, fw_info.ver); 1125 } 1126 1127 /* PSP SOS */ 1128 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1129 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1130 if (ret) 1131 return ret; 1132 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1133 fw_info.feature, fw_info.ver); 1134 1135 1136 /* PSP ASD */ 1137 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1138 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1139 if (ret) 1140 return ret; 1141 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1142 fw_info.feature, fw_info.ver); 1143 1144 /* SMC */ 1145 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1146 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1147 if (ret) 1148 return ret; 1149 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1150 fw_info.feature, fw_info.ver); 1151 1152 /* SDMA */ 1153 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1154 for (i = 0; i < adev->sdma.num_instances; i++) { 1155 query_fw.index = i; 1156 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1157 if (ret) 1158 return ret; 1159 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1160 i, fw_info.feature, fw_info.ver); 1161 } 1162 1163 return 0; 1164 } 1165 1166 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1167 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1168 }; 1169 #endif 1170 1171 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1172 { 1173 #if defined(CONFIG_DEBUG_FS) 1174 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1175 ARRAY_SIZE(amdgpu_firmware_info_list)); 1176 #else 1177 return 0; 1178 #endif 1179 } 1180