1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = drm_to_adev(dev); 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 return; 90 91 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 92 DRM_WARN("smart shift update failed\n"); 93 94 amdgpu_acpi_fini(adev); 95 amdgpu_device_fini_hw(adev); 96 } 97 98 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 99 { 100 struct amdgpu_gpu_instance *gpu_instance; 101 102 mutex_lock(&mgpu_info.mutex); 103 104 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 105 DRM_ERROR("Cannot register more gpu instance\n"); 106 mutex_unlock(&mgpu_info.mutex); 107 return; 108 } 109 110 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 111 gpu_instance->adev = adev; 112 gpu_instance->mgpu_fan_enabled = 0; 113 114 mgpu_info.num_gpu++; 115 if (adev->flags & AMD_IS_APU) 116 mgpu_info.num_apu++; 117 else 118 mgpu_info.num_dgpu++; 119 120 mutex_unlock(&mgpu_info.mutex); 121 } 122 123 /** 124 * amdgpu_driver_load_kms - Main load function for KMS. 125 * 126 * @adev: pointer to struct amdgpu_device 127 * @flags: device flags 128 * 129 * This is the main load function for KMS (all asics). 130 * Returns 0 on success, error on failure. 131 */ 132 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 133 { 134 struct drm_device *dev; 135 int r, acpi_status; 136 137 dev = adev_to_drm(adev); 138 139 /* amdgpu_device_init should report only fatal error 140 * like memory allocation failure or iomapping failure, 141 * or memory manager initialization failure, it must 142 * properly initialize the GPU MC controller and permit 143 * VRAM allocation 144 */ 145 r = amdgpu_device_init(adev, flags); 146 if (r) { 147 dev_err(dev->dev, "Fatal error during GPU init\n"); 148 goto out; 149 } 150 151 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 152 if (amdgpu_device_supports_px(dev) && 153 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 154 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 155 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 156 } else if (amdgpu_device_supports_boco(dev) && 157 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 158 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 159 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 160 } else if (amdgpu_device_supports_baco(dev) && 161 (amdgpu_runtime_pm != 0)) { 162 switch (adev->asic_type) { 163 case CHIP_VEGA20: 164 case CHIP_ARCTURUS: 165 /* enable BACO as runpm mode if runpm=1 */ 166 if (amdgpu_runtime_pm > 0) 167 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 168 break; 169 case CHIP_VEGA10: 170 /* enable BACO as runpm mode if noretry=0 */ 171 if (!adev->gmc.noretry) 172 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 173 break; 174 default: 175 /* enable BACO as runpm mode on CI+ */ 176 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 177 break; 178 } 179 180 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 181 dev_info(adev->dev, "Using BACO for runtime pm\n"); 182 } 183 184 /* Call ACPI methods: require modeset init 185 * but failure is not fatal 186 */ 187 188 acpi_status = amdgpu_acpi_init(adev); 189 if (acpi_status) 190 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 191 192 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 193 DRM_WARN("smart shift update failed\n"); 194 195 out: 196 if (r) 197 amdgpu_driver_unload_kms(dev); 198 199 return r; 200 } 201 202 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 203 struct drm_amdgpu_query_fw *query_fw, 204 struct amdgpu_device *adev) 205 { 206 switch (query_fw->fw_type) { 207 case AMDGPU_INFO_FW_VCE: 208 fw_info->ver = adev->vce.fw_version; 209 fw_info->feature = adev->vce.fb_version; 210 break; 211 case AMDGPU_INFO_FW_UVD: 212 fw_info->ver = adev->uvd.fw_version; 213 fw_info->feature = 0; 214 break; 215 case AMDGPU_INFO_FW_VCN: 216 fw_info->ver = adev->vcn.fw_version; 217 fw_info->feature = 0; 218 break; 219 case AMDGPU_INFO_FW_GMC: 220 fw_info->ver = adev->gmc.fw_version; 221 fw_info->feature = 0; 222 break; 223 case AMDGPU_INFO_FW_GFX_ME: 224 fw_info->ver = adev->gfx.me_fw_version; 225 fw_info->feature = adev->gfx.me_feature_version; 226 break; 227 case AMDGPU_INFO_FW_GFX_PFP: 228 fw_info->ver = adev->gfx.pfp_fw_version; 229 fw_info->feature = adev->gfx.pfp_feature_version; 230 break; 231 case AMDGPU_INFO_FW_GFX_CE: 232 fw_info->ver = adev->gfx.ce_fw_version; 233 fw_info->feature = adev->gfx.ce_feature_version; 234 break; 235 case AMDGPU_INFO_FW_GFX_RLC: 236 fw_info->ver = adev->gfx.rlc_fw_version; 237 fw_info->feature = adev->gfx.rlc_feature_version; 238 break; 239 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 240 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 241 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 242 break; 243 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 244 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 245 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 246 break; 247 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 248 fw_info->ver = adev->gfx.rlc_srls_fw_version; 249 fw_info->feature = adev->gfx.rlc_srls_feature_version; 250 break; 251 case AMDGPU_INFO_FW_GFX_RLCP: 252 fw_info->ver = adev->gfx.rlcp_ucode_version; 253 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 254 break; 255 case AMDGPU_INFO_FW_GFX_RLCV: 256 fw_info->ver = adev->gfx.rlcv_ucode_version; 257 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 258 break; 259 case AMDGPU_INFO_FW_GFX_MEC: 260 if (query_fw->index == 0) { 261 fw_info->ver = adev->gfx.mec_fw_version; 262 fw_info->feature = adev->gfx.mec_feature_version; 263 } else if (query_fw->index == 1) { 264 fw_info->ver = adev->gfx.mec2_fw_version; 265 fw_info->feature = adev->gfx.mec2_feature_version; 266 } else 267 return -EINVAL; 268 break; 269 case AMDGPU_INFO_FW_SMC: 270 fw_info->ver = adev->pm.fw_version; 271 fw_info->feature = 0; 272 break; 273 case AMDGPU_INFO_FW_TA: 274 switch (query_fw->index) { 275 case TA_FW_TYPE_PSP_XGMI: 276 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 277 fw_info->feature = adev->psp.xgmi_context.context 278 .bin_desc.feature_version; 279 break; 280 case TA_FW_TYPE_PSP_RAS: 281 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 282 fw_info->feature = adev->psp.ras_context.context 283 .bin_desc.feature_version; 284 break; 285 case TA_FW_TYPE_PSP_HDCP: 286 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 287 fw_info->feature = adev->psp.hdcp_context.context 288 .bin_desc.feature_version; 289 break; 290 case TA_FW_TYPE_PSP_DTM: 291 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 292 fw_info->feature = adev->psp.dtm_context.context 293 .bin_desc.feature_version; 294 break; 295 case TA_FW_TYPE_PSP_RAP: 296 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 297 fw_info->feature = adev->psp.rap_context.context 298 .bin_desc.feature_version; 299 break; 300 case TA_FW_TYPE_PSP_SECUREDISPLAY: 301 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 302 fw_info->feature = 303 adev->psp.securedisplay_context.context.bin_desc 304 .feature_version; 305 break; 306 default: 307 return -EINVAL; 308 } 309 break; 310 case AMDGPU_INFO_FW_SDMA: 311 if (query_fw->index >= adev->sdma.num_instances) 312 return -EINVAL; 313 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 314 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 315 break; 316 case AMDGPU_INFO_FW_SOS: 317 fw_info->ver = adev->psp.sos.fw_version; 318 fw_info->feature = adev->psp.sos.feature_version; 319 break; 320 case AMDGPU_INFO_FW_ASD: 321 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 322 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 323 break; 324 case AMDGPU_INFO_FW_DMCU: 325 fw_info->ver = adev->dm.dmcu_fw_version; 326 fw_info->feature = 0; 327 break; 328 case AMDGPU_INFO_FW_DMCUB: 329 fw_info->ver = adev->dm.dmcub_fw_version; 330 fw_info->feature = 0; 331 break; 332 case AMDGPU_INFO_FW_TOC: 333 fw_info->ver = adev->psp.toc.fw_version; 334 fw_info->feature = adev->psp.toc.feature_version; 335 break; 336 case AMDGPU_INFO_FW_CAP: 337 fw_info->ver = adev->psp.cap_fw_version; 338 fw_info->feature = adev->psp.cap_feature_version; 339 break; 340 case AMDGPU_INFO_FW_MES_KIQ: 341 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 342 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 343 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 344 break; 345 case AMDGPU_INFO_FW_MES: 346 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 347 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 348 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 349 break; 350 case AMDGPU_INFO_FW_IMU: 351 fw_info->ver = adev->gfx.imu_fw_version; 352 fw_info->feature = 0; 353 break; 354 default: 355 return -EINVAL; 356 } 357 return 0; 358 } 359 360 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 361 struct drm_amdgpu_info *info, 362 struct drm_amdgpu_info_hw_ip *result) 363 { 364 uint32_t ib_start_alignment = 0; 365 uint32_t ib_size_alignment = 0; 366 enum amd_ip_block_type type; 367 unsigned int num_rings = 0; 368 unsigned int i, j; 369 370 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 371 return -EINVAL; 372 373 switch (info->query_hw_ip.type) { 374 case AMDGPU_HW_IP_GFX: 375 type = AMD_IP_BLOCK_TYPE_GFX; 376 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 377 if (adev->gfx.gfx_ring[i].sched.ready) 378 ++num_rings; 379 ib_start_alignment = 32; 380 ib_size_alignment = 32; 381 break; 382 case AMDGPU_HW_IP_COMPUTE: 383 type = AMD_IP_BLOCK_TYPE_GFX; 384 for (i = 0; i < adev->gfx.num_compute_rings; i++) 385 if (adev->gfx.compute_ring[i].sched.ready) 386 ++num_rings; 387 ib_start_alignment = 32; 388 ib_size_alignment = 32; 389 break; 390 case AMDGPU_HW_IP_DMA: 391 type = AMD_IP_BLOCK_TYPE_SDMA; 392 for (i = 0; i < adev->sdma.num_instances; i++) 393 if (adev->sdma.instance[i].ring.sched.ready) 394 ++num_rings; 395 ib_start_alignment = 256; 396 ib_size_alignment = 4; 397 break; 398 case AMDGPU_HW_IP_UVD: 399 type = AMD_IP_BLOCK_TYPE_UVD; 400 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 401 if (adev->uvd.harvest_config & (1 << i)) 402 continue; 403 404 if (adev->uvd.inst[i].ring.sched.ready) 405 ++num_rings; 406 } 407 ib_start_alignment = 64; 408 ib_size_alignment = 64; 409 break; 410 case AMDGPU_HW_IP_VCE: 411 type = AMD_IP_BLOCK_TYPE_VCE; 412 for (i = 0; i < adev->vce.num_rings; i++) 413 if (adev->vce.ring[i].sched.ready) 414 ++num_rings; 415 ib_start_alignment = 4; 416 ib_size_alignment = 1; 417 break; 418 case AMDGPU_HW_IP_UVD_ENC: 419 type = AMD_IP_BLOCK_TYPE_UVD; 420 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 421 if (adev->uvd.harvest_config & (1 << i)) 422 continue; 423 424 for (j = 0; j < adev->uvd.num_enc_rings; j++) 425 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 426 ++num_rings; 427 } 428 ib_start_alignment = 64; 429 ib_size_alignment = 64; 430 break; 431 case AMDGPU_HW_IP_VCN_DEC: 432 type = AMD_IP_BLOCK_TYPE_VCN; 433 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 434 if (adev->vcn.harvest_config & (1 << i)) 435 continue; 436 437 if (adev->vcn.inst[i].ring_dec.sched.ready) 438 ++num_rings; 439 } 440 ib_start_alignment = 16; 441 ib_size_alignment = 16; 442 break; 443 case AMDGPU_HW_IP_VCN_ENC: 444 type = AMD_IP_BLOCK_TYPE_VCN; 445 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 446 if (adev->vcn.harvest_config & (1 << i)) 447 continue; 448 449 for (j = 0; j < adev->vcn.num_enc_rings; j++) 450 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 451 ++num_rings; 452 } 453 ib_start_alignment = 64; 454 ib_size_alignment = 1; 455 break; 456 case AMDGPU_HW_IP_VCN_JPEG: 457 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 458 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 459 460 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 461 if (adev->jpeg.harvest_config & (1 << i)) 462 continue; 463 464 if (adev->jpeg.inst[i].ring_dec.sched.ready) 465 ++num_rings; 466 } 467 ib_start_alignment = 16; 468 ib_size_alignment = 16; 469 break; 470 default: 471 return -EINVAL; 472 } 473 474 for (i = 0; i < adev->num_ip_blocks; i++) 475 if (adev->ip_blocks[i].version->type == type && 476 adev->ip_blocks[i].status.valid) 477 break; 478 479 if (i == adev->num_ip_blocks) 480 return 0; 481 482 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 483 num_rings); 484 485 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 486 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 487 488 if (adev->asic_type >= CHIP_VEGA10) { 489 switch (type) { 490 case AMD_IP_BLOCK_TYPE_GFX: 491 result->ip_discovery_version = adev->ip_versions[GC_HWIP][0]; 492 break; 493 case AMD_IP_BLOCK_TYPE_SDMA: 494 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0]; 495 break; 496 case AMD_IP_BLOCK_TYPE_UVD: 497 case AMD_IP_BLOCK_TYPE_VCN: 498 case AMD_IP_BLOCK_TYPE_JPEG: 499 result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0]; 500 break; 501 case AMD_IP_BLOCK_TYPE_VCE: 502 result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0]; 503 break; 504 default: 505 result->ip_discovery_version = 0; 506 break; 507 } 508 } else { 509 result->ip_discovery_version = 0; 510 } 511 result->capabilities_flags = 0; 512 result->available_rings = (1 << num_rings) - 1; 513 result->ib_start_alignment = ib_start_alignment; 514 result->ib_size_alignment = ib_size_alignment; 515 return 0; 516 } 517 518 /* 519 * Userspace get information ioctl 520 */ 521 /** 522 * amdgpu_info_ioctl - answer a device specific request. 523 * 524 * @dev: drm device pointer 525 * @data: request object 526 * @filp: drm filp 527 * 528 * This function is used to pass device specific parameters to the userspace 529 * drivers. Examples include: pci device id, pipeline parms, tiling params, 530 * etc. (all asics). 531 * Returns 0 on success, -EINVAL on failure. 532 */ 533 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 534 { 535 struct amdgpu_device *adev = drm_to_adev(dev); 536 struct drm_amdgpu_info *info = data; 537 struct amdgpu_mode_info *minfo = &adev->mode_info; 538 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 539 uint32_t size = info->return_size; 540 struct drm_crtc *crtc; 541 uint32_t ui32 = 0; 542 uint64_t ui64 = 0; 543 int i, found; 544 int ui32_size = sizeof(ui32); 545 546 if (!info->return_size || !info->return_pointer) 547 return -EINVAL; 548 549 switch (info->query) { 550 case AMDGPU_INFO_ACCEL_WORKING: 551 ui32 = adev->accel_working; 552 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 553 case AMDGPU_INFO_CRTC_FROM_ID: 554 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 555 crtc = (struct drm_crtc *)minfo->crtcs[i]; 556 if (crtc && crtc->base.id == info->mode_crtc.id) { 557 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 558 ui32 = amdgpu_crtc->crtc_id; 559 found = 1; 560 break; 561 } 562 } 563 if (!found) { 564 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 565 return -EINVAL; 566 } 567 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 568 case AMDGPU_INFO_HW_IP_INFO: { 569 struct drm_amdgpu_info_hw_ip ip = {}; 570 int ret; 571 572 ret = amdgpu_hw_ip_info(adev, info, &ip); 573 if (ret) 574 return ret; 575 576 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 577 return ret ? -EFAULT : 0; 578 } 579 case AMDGPU_INFO_HW_IP_COUNT: { 580 enum amd_ip_block_type type; 581 uint32_t count = 0; 582 583 switch (info->query_hw_ip.type) { 584 case AMDGPU_HW_IP_GFX: 585 type = AMD_IP_BLOCK_TYPE_GFX; 586 break; 587 case AMDGPU_HW_IP_COMPUTE: 588 type = AMD_IP_BLOCK_TYPE_GFX; 589 break; 590 case AMDGPU_HW_IP_DMA: 591 type = AMD_IP_BLOCK_TYPE_SDMA; 592 break; 593 case AMDGPU_HW_IP_UVD: 594 type = AMD_IP_BLOCK_TYPE_UVD; 595 break; 596 case AMDGPU_HW_IP_VCE: 597 type = AMD_IP_BLOCK_TYPE_VCE; 598 break; 599 case AMDGPU_HW_IP_UVD_ENC: 600 type = AMD_IP_BLOCK_TYPE_UVD; 601 break; 602 case AMDGPU_HW_IP_VCN_DEC: 603 case AMDGPU_HW_IP_VCN_ENC: 604 type = AMD_IP_BLOCK_TYPE_VCN; 605 break; 606 case AMDGPU_HW_IP_VCN_JPEG: 607 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 608 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 609 break; 610 default: 611 return -EINVAL; 612 } 613 614 for (i = 0; i < adev->num_ip_blocks; i++) 615 if (adev->ip_blocks[i].version->type == type && 616 adev->ip_blocks[i].status.valid && 617 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 618 count++; 619 620 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 621 } 622 case AMDGPU_INFO_TIMESTAMP: 623 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 624 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 625 case AMDGPU_INFO_FW_VERSION: { 626 struct drm_amdgpu_info_firmware fw_info; 627 int ret; 628 629 /* We only support one instance of each IP block right now. */ 630 if (info->query_fw.ip_instance != 0) 631 return -EINVAL; 632 633 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 634 if (ret) 635 return ret; 636 637 return copy_to_user(out, &fw_info, 638 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 639 } 640 case AMDGPU_INFO_NUM_BYTES_MOVED: 641 ui64 = atomic64_read(&adev->num_bytes_moved); 642 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 643 case AMDGPU_INFO_NUM_EVICTIONS: 644 ui64 = atomic64_read(&adev->num_evictions); 645 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 646 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 647 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 648 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 649 case AMDGPU_INFO_VRAM_USAGE: 650 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 651 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 652 case AMDGPU_INFO_VIS_VRAM_USAGE: 653 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 654 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 655 case AMDGPU_INFO_GTT_USAGE: 656 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 657 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 658 case AMDGPU_INFO_GDS_CONFIG: { 659 struct drm_amdgpu_info_gds gds_info; 660 661 memset(&gds_info, 0, sizeof(gds_info)); 662 gds_info.compute_partition_size = adev->gds.gds_size; 663 gds_info.gds_total_size = adev->gds.gds_size; 664 gds_info.gws_per_compute_partition = adev->gds.gws_size; 665 gds_info.oa_per_compute_partition = adev->gds.oa_size; 666 return copy_to_user(out, &gds_info, 667 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 668 } 669 case AMDGPU_INFO_VRAM_GTT: { 670 struct drm_amdgpu_info_vram_gtt vram_gtt; 671 672 vram_gtt.vram_size = adev->gmc.real_vram_size - 673 atomic64_read(&adev->vram_pin_size) - 674 AMDGPU_VM_RESERVED_VRAM; 675 vram_gtt.vram_cpu_accessible_size = 676 min(adev->gmc.visible_vram_size - 677 atomic64_read(&adev->visible_pin_size), 678 vram_gtt.vram_size); 679 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 680 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 681 return copy_to_user(out, &vram_gtt, 682 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 683 } 684 case AMDGPU_INFO_MEMORY: { 685 struct drm_amdgpu_memory_info mem; 686 struct ttm_resource_manager *gtt_man = 687 &adev->mman.gtt_mgr.manager; 688 struct ttm_resource_manager *vram_man = 689 &adev->mman.vram_mgr.manager; 690 691 memset(&mem, 0, sizeof(mem)); 692 mem.vram.total_heap_size = adev->gmc.real_vram_size; 693 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 694 atomic64_read(&adev->vram_pin_size) - 695 AMDGPU_VM_RESERVED_VRAM; 696 mem.vram.heap_usage = 697 ttm_resource_manager_usage(vram_man); 698 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 699 700 mem.cpu_accessible_vram.total_heap_size = 701 adev->gmc.visible_vram_size; 702 mem.cpu_accessible_vram.usable_heap_size = 703 min(adev->gmc.visible_vram_size - 704 atomic64_read(&adev->visible_pin_size), 705 mem.vram.usable_heap_size); 706 mem.cpu_accessible_vram.heap_usage = 707 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 708 mem.cpu_accessible_vram.max_allocation = 709 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 710 711 mem.gtt.total_heap_size = gtt_man->size; 712 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 713 atomic64_read(&adev->gart_pin_size); 714 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 715 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 716 717 return copy_to_user(out, &mem, 718 min((size_t)size, sizeof(mem))) 719 ? -EFAULT : 0; 720 } 721 case AMDGPU_INFO_READ_MMR_REG: { 722 unsigned n, alloc_size; 723 uint32_t *regs; 724 unsigned se_num = (info->read_mmr_reg.instance >> 725 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 726 AMDGPU_INFO_MMR_SE_INDEX_MASK; 727 unsigned sh_num = (info->read_mmr_reg.instance >> 728 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 729 AMDGPU_INFO_MMR_SH_INDEX_MASK; 730 731 /* set full masks if the userspace set all bits 732 * in the bitfields */ 733 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 734 se_num = 0xffffffff; 735 else if (se_num >= AMDGPU_GFX_MAX_SE) 736 return -EINVAL; 737 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 738 sh_num = 0xffffffff; 739 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 740 return -EINVAL; 741 742 if (info->read_mmr_reg.count > 128) 743 return -EINVAL; 744 745 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 746 if (!regs) 747 return -ENOMEM; 748 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 749 750 amdgpu_gfx_off_ctrl(adev, false); 751 for (i = 0; i < info->read_mmr_reg.count; i++) { 752 if (amdgpu_asic_read_register(adev, se_num, sh_num, 753 info->read_mmr_reg.dword_offset + i, 754 ®s[i])) { 755 DRM_DEBUG_KMS("unallowed offset %#x\n", 756 info->read_mmr_reg.dword_offset + i); 757 kfree(regs); 758 amdgpu_gfx_off_ctrl(adev, true); 759 return -EFAULT; 760 } 761 } 762 amdgpu_gfx_off_ctrl(adev, true); 763 n = copy_to_user(out, regs, min(size, alloc_size)); 764 kfree(regs); 765 return n ? -EFAULT : 0; 766 } 767 case AMDGPU_INFO_DEV_INFO: { 768 struct drm_amdgpu_info_device *dev_info; 769 uint64_t vm_size; 770 int ret; 771 772 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 773 if (!dev_info) 774 return -ENOMEM; 775 776 dev_info->device_id = adev->pdev->device; 777 dev_info->chip_rev = adev->rev_id; 778 dev_info->external_rev = adev->external_rev_id; 779 dev_info->pci_rev = adev->pdev->revision; 780 dev_info->family = adev->family; 781 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 782 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 783 /* return all clocks in KHz */ 784 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 785 if (adev->pm.dpm_enabled) { 786 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 787 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 788 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 789 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 790 } else { 791 dev_info->max_engine_clock = 792 dev_info->min_engine_clock = 793 adev->clock.default_sclk * 10; 794 dev_info->max_memory_clock = 795 dev_info->min_memory_clock = 796 adev->clock.default_mclk * 10; 797 } 798 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 799 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 800 adev->gfx.config.max_shader_engines; 801 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 802 dev_info->_pad = 0; 803 dev_info->ids_flags = 0; 804 if (adev->flags & AMD_IS_APU) 805 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 806 if (amdgpu_mcbp) 807 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 808 if (amdgpu_is_tmz(adev)) 809 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 810 811 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 812 vm_size -= AMDGPU_VA_RESERVED_SIZE; 813 814 /* Older VCE FW versions are buggy and can handle only 40bits */ 815 if (adev->vce.fw_version && 816 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 817 vm_size = min(vm_size, 1ULL << 40); 818 819 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 820 dev_info->virtual_address_max = 821 min(vm_size, AMDGPU_GMC_HOLE_START); 822 823 if (vm_size > AMDGPU_GMC_HOLE_START) { 824 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 825 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 826 } 827 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 828 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 829 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 830 dev_info->cu_active_number = adev->gfx.cu_info.number; 831 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 832 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 833 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 834 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 835 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 836 sizeof(adev->gfx.cu_info.bitmap)); 837 dev_info->vram_type = adev->gmc.vram_type; 838 dev_info->vram_bit_width = adev->gmc.vram_width; 839 dev_info->vce_harvest_config = adev->vce.harvest_config; 840 dev_info->gc_double_offchip_lds_buf = 841 adev->gfx.config.double_offchip_lds_buf; 842 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 843 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 844 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 845 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 846 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 847 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 848 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 849 850 if (adev->family >= AMDGPU_FAMILY_NV) 851 dev_info->pa_sc_tile_steering_override = 852 adev->gfx.config.pa_sc_tile_steering_override; 853 854 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 855 856 ret = copy_to_user(out, dev_info, 857 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 858 kfree(dev_info); 859 return ret; 860 } 861 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 862 unsigned i; 863 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 864 struct amd_vce_state *vce_state; 865 866 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 867 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 868 if (vce_state) { 869 vce_clk_table.entries[i].sclk = vce_state->sclk; 870 vce_clk_table.entries[i].mclk = vce_state->mclk; 871 vce_clk_table.entries[i].eclk = vce_state->evclk; 872 vce_clk_table.num_valid_entries++; 873 } 874 } 875 876 return copy_to_user(out, &vce_clk_table, 877 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 878 } 879 case AMDGPU_INFO_VBIOS: { 880 uint32_t bios_size = adev->bios_size; 881 882 switch (info->vbios_info.type) { 883 case AMDGPU_INFO_VBIOS_SIZE: 884 return copy_to_user(out, &bios_size, 885 min((size_t)size, sizeof(bios_size))) 886 ? -EFAULT : 0; 887 case AMDGPU_INFO_VBIOS_IMAGE: { 888 uint8_t *bios; 889 uint32_t bios_offset = info->vbios_info.offset; 890 891 if (bios_offset >= bios_size) 892 return -EINVAL; 893 894 bios = adev->bios + bios_offset; 895 return copy_to_user(out, bios, 896 min((size_t)size, (size_t)(bios_size - bios_offset))) 897 ? -EFAULT : 0; 898 } 899 case AMDGPU_INFO_VBIOS_INFO: { 900 struct drm_amdgpu_info_vbios vbios_info = {}; 901 struct atom_context *atom_context; 902 903 atom_context = adev->mode_info.atom_context; 904 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 905 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 906 vbios_info.version = atom_context->version; 907 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 908 sizeof(atom_context->vbios_ver_str)); 909 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 910 911 return copy_to_user(out, &vbios_info, 912 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 913 } 914 default: 915 DRM_DEBUG_KMS("Invalid request %d\n", 916 info->vbios_info.type); 917 return -EINVAL; 918 } 919 } 920 case AMDGPU_INFO_NUM_HANDLES: { 921 struct drm_amdgpu_info_num_handles handle; 922 923 switch (info->query_hw_ip.type) { 924 case AMDGPU_HW_IP_UVD: 925 /* Starting Polaris, we support unlimited UVD handles */ 926 if (adev->asic_type < CHIP_POLARIS10) { 927 handle.uvd_max_handles = adev->uvd.max_handles; 928 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 929 930 return copy_to_user(out, &handle, 931 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 932 } else { 933 return -ENODATA; 934 } 935 936 break; 937 default: 938 return -EINVAL; 939 } 940 } 941 case AMDGPU_INFO_SENSOR: { 942 if (!adev->pm.dpm_enabled) 943 return -ENOENT; 944 945 switch (info->sensor_info.type) { 946 case AMDGPU_INFO_SENSOR_GFX_SCLK: 947 /* get sclk in Mhz */ 948 if (amdgpu_dpm_read_sensor(adev, 949 AMDGPU_PP_SENSOR_GFX_SCLK, 950 (void *)&ui32, &ui32_size)) { 951 return -EINVAL; 952 } 953 ui32 /= 100; 954 break; 955 case AMDGPU_INFO_SENSOR_GFX_MCLK: 956 /* get mclk in Mhz */ 957 if (amdgpu_dpm_read_sensor(adev, 958 AMDGPU_PP_SENSOR_GFX_MCLK, 959 (void *)&ui32, &ui32_size)) { 960 return -EINVAL; 961 } 962 ui32 /= 100; 963 break; 964 case AMDGPU_INFO_SENSOR_GPU_TEMP: 965 /* get temperature in millidegrees C */ 966 if (amdgpu_dpm_read_sensor(adev, 967 AMDGPU_PP_SENSOR_GPU_TEMP, 968 (void *)&ui32, &ui32_size)) { 969 return -EINVAL; 970 } 971 break; 972 case AMDGPU_INFO_SENSOR_GPU_LOAD: 973 /* get GPU load */ 974 if (amdgpu_dpm_read_sensor(adev, 975 AMDGPU_PP_SENSOR_GPU_LOAD, 976 (void *)&ui32, &ui32_size)) { 977 return -EINVAL; 978 } 979 break; 980 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 981 /* get average GPU power */ 982 if (amdgpu_dpm_read_sensor(adev, 983 AMDGPU_PP_SENSOR_GPU_POWER, 984 (void *)&ui32, &ui32_size)) { 985 return -EINVAL; 986 } 987 ui32 >>= 8; 988 break; 989 case AMDGPU_INFO_SENSOR_VDDNB: 990 /* get VDDNB in millivolts */ 991 if (amdgpu_dpm_read_sensor(adev, 992 AMDGPU_PP_SENSOR_VDDNB, 993 (void *)&ui32, &ui32_size)) { 994 return -EINVAL; 995 } 996 break; 997 case AMDGPU_INFO_SENSOR_VDDGFX: 998 /* get VDDGFX in millivolts */ 999 if (amdgpu_dpm_read_sensor(adev, 1000 AMDGPU_PP_SENSOR_VDDGFX, 1001 (void *)&ui32, &ui32_size)) { 1002 return -EINVAL; 1003 } 1004 break; 1005 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1006 /* get stable pstate sclk in Mhz */ 1007 if (amdgpu_dpm_read_sensor(adev, 1008 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1009 (void *)&ui32, &ui32_size)) { 1010 return -EINVAL; 1011 } 1012 ui32 /= 100; 1013 break; 1014 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1015 /* get stable pstate mclk in Mhz */ 1016 if (amdgpu_dpm_read_sensor(adev, 1017 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1018 (void *)&ui32, &ui32_size)) { 1019 return -EINVAL; 1020 } 1021 ui32 /= 100; 1022 break; 1023 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1024 /* get peak pstate sclk in Mhz */ 1025 if (amdgpu_dpm_read_sensor(adev, 1026 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1027 (void *)&ui32, &ui32_size)) { 1028 return -EINVAL; 1029 } 1030 ui32 /= 100; 1031 break; 1032 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1033 /* get peak pstate mclk in Mhz */ 1034 if (amdgpu_dpm_read_sensor(adev, 1035 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1036 (void *)&ui32, &ui32_size)) { 1037 return -EINVAL; 1038 } 1039 ui32 /= 100; 1040 break; 1041 default: 1042 DRM_DEBUG_KMS("Invalid request %d\n", 1043 info->sensor_info.type); 1044 return -EINVAL; 1045 } 1046 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1047 } 1048 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1049 ui32 = atomic_read(&adev->vram_lost_counter); 1050 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1051 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1052 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1053 uint64_t ras_mask; 1054 1055 if (!ras) 1056 return -EINVAL; 1057 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1058 1059 return copy_to_user(out, &ras_mask, 1060 min_t(u64, size, sizeof(ras_mask))) ? 1061 -EFAULT : 0; 1062 } 1063 case AMDGPU_INFO_VIDEO_CAPS: { 1064 const struct amdgpu_video_codecs *codecs; 1065 struct drm_amdgpu_info_video_caps *caps; 1066 int r; 1067 1068 switch (info->video_cap.type) { 1069 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1070 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1071 if (r) 1072 return -EINVAL; 1073 break; 1074 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1075 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1076 if (r) 1077 return -EINVAL; 1078 break; 1079 default: 1080 DRM_DEBUG_KMS("Invalid request %d\n", 1081 info->video_cap.type); 1082 return -EINVAL; 1083 } 1084 1085 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1086 if (!caps) 1087 return -ENOMEM; 1088 1089 for (i = 0; i < codecs->codec_count; i++) { 1090 int idx = codecs->codec_array[i].codec_type; 1091 1092 switch (idx) { 1093 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1094 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1095 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1096 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1097 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1098 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1099 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1100 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1101 caps->codec_info[idx].valid = 1; 1102 caps->codec_info[idx].max_width = 1103 codecs->codec_array[i].max_width; 1104 caps->codec_info[idx].max_height = 1105 codecs->codec_array[i].max_height; 1106 caps->codec_info[idx].max_pixels_per_frame = 1107 codecs->codec_array[i].max_pixels_per_frame; 1108 caps->codec_info[idx].max_level = 1109 codecs->codec_array[i].max_level; 1110 break; 1111 default: 1112 break; 1113 } 1114 } 1115 r = copy_to_user(out, caps, 1116 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1117 kfree(caps); 1118 return r; 1119 } 1120 default: 1121 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1122 return -EINVAL; 1123 } 1124 return 0; 1125 } 1126 1127 1128 /* 1129 * Outdated mess for old drm with Xorg being in charge (void function now). 1130 */ 1131 /** 1132 * amdgpu_driver_lastclose_kms - drm callback for last close 1133 * 1134 * @dev: drm dev pointer 1135 * 1136 * Switch vga_switcheroo state after last close (all asics). 1137 */ 1138 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1139 { 1140 drm_fb_helper_lastclose(dev); 1141 vga_switcheroo_process_delayed_switch(); 1142 } 1143 1144 /** 1145 * amdgpu_driver_open_kms - drm callback for open 1146 * 1147 * @dev: drm dev pointer 1148 * @file_priv: drm file 1149 * 1150 * On device open, init vm on cayman+ (all asics). 1151 * Returns 0 on success, error on failure. 1152 */ 1153 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1154 { 1155 struct amdgpu_device *adev = drm_to_adev(dev); 1156 struct amdgpu_fpriv *fpriv; 1157 int r, pasid; 1158 1159 /* Ensure IB tests are run on ring */ 1160 flush_delayed_work(&adev->delayed_init_work); 1161 1162 1163 if (amdgpu_ras_intr_triggered()) { 1164 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1165 return -EHWPOISON; 1166 } 1167 1168 file_priv->driver_priv = NULL; 1169 1170 r = pm_runtime_get_sync(dev->dev); 1171 if (r < 0) 1172 goto pm_put; 1173 1174 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1175 if (unlikely(!fpriv)) { 1176 r = -ENOMEM; 1177 goto out_suspend; 1178 } 1179 1180 pasid = amdgpu_pasid_alloc(16); 1181 if (pasid < 0) { 1182 dev_warn(adev->dev, "No more PASIDs available!"); 1183 pasid = 0; 1184 } 1185 1186 r = amdgpu_vm_init(adev, &fpriv->vm); 1187 if (r) 1188 goto error_pasid; 1189 1190 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1191 if (r) 1192 goto error_vm; 1193 1194 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1195 if (!fpriv->prt_va) { 1196 r = -ENOMEM; 1197 goto error_vm; 1198 } 1199 1200 if (amdgpu_mcbp) { 1201 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1202 1203 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1204 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1205 if (r) 1206 goto error_vm; 1207 } 1208 1209 mutex_init(&fpriv->bo_list_lock); 1210 idr_init_base(&fpriv->bo_list_handles, 1); 1211 1212 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1213 1214 file_priv->driver_priv = fpriv; 1215 goto out_suspend; 1216 1217 error_vm: 1218 amdgpu_vm_fini(adev, &fpriv->vm); 1219 1220 error_pasid: 1221 if (pasid) { 1222 amdgpu_pasid_free(pasid); 1223 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1224 } 1225 1226 kfree(fpriv); 1227 1228 out_suspend: 1229 pm_runtime_mark_last_busy(dev->dev); 1230 pm_put: 1231 pm_runtime_put_autosuspend(dev->dev); 1232 1233 return r; 1234 } 1235 1236 /** 1237 * amdgpu_driver_postclose_kms - drm callback for post close 1238 * 1239 * @dev: drm dev pointer 1240 * @file_priv: drm file 1241 * 1242 * On device post close, tear down vm on cayman+ (all asics). 1243 */ 1244 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1245 struct drm_file *file_priv) 1246 { 1247 struct amdgpu_device *adev = drm_to_adev(dev); 1248 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1249 struct amdgpu_bo_list *list; 1250 struct amdgpu_bo *pd; 1251 u32 pasid; 1252 int handle; 1253 1254 if (!fpriv) 1255 return; 1256 1257 pm_runtime_get_sync(dev->dev); 1258 1259 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1260 amdgpu_uvd_free_handles(adev, file_priv); 1261 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1262 amdgpu_vce_free_handles(adev, file_priv); 1263 1264 if (amdgpu_mcbp) { 1265 /* TODO: how to handle reserve failure */ 1266 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1267 amdgpu_vm_bo_del(adev, fpriv->csa_va); 1268 fpriv->csa_va = NULL; 1269 amdgpu_bo_unreserve(adev->virt.csa_obj); 1270 } 1271 1272 pasid = fpriv->vm.pasid; 1273 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1274 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1275 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1276 amdgpu_bo_unreserve(pd); 1277 } 1278 1279 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1280 amdgpu_vm_fini(adev, &fpriv->vm); 1281 1282 if (pasid) 1283 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1284 amdgpu_bo_unref(&pd); 1285 1286 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1287 amdgpu_bo_list_put(list); 1288 1289 idr_destroy(&fpriv->bo_list_handles); 1290 mutex_destroy(&fpriv->bo_list_lock); 1291 1292 kfree(fpriv); 1293 file_priv->driver_priv = NULL; 1294 1295 pm_runtime_mark_last_busy(dev->dev); 1296 pm_runtime_put_autosuspend(dev->dev); 1297 } 1298 1299 1300 void amdgpu_driver_release_kms(struct drm_device *dev) 1301 { 1302 struct amdgpu_device *adev = drm_to_adev(dev); 1303 1304 amdgpu_device_fini_sw(adev); 1305 pci_set_drvdata(adev->pdev, NULL); 1306 } 1307 1308 /* 1309 * VBlank related functions. 1310 */ 1311 /** 1312 * amdgpu_get_vblank_counter_kms - get frame count 1313 * 1314 * @crtc: crtc to get the frame count from 1315 * 1316 * Gets the frame count on the requested crtc (all asics). 1317 * Returns frame count on success, -EINVAL on failure. 1318 */ 1319 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1320 { 1321 struct drm_device *dev = crtc->dev; 1322 unsigned int pipe = crtc->index; 1323 struct amdgpu_device *adev = drm_to_adev(dev); 1324 int vpos, hpos, stat; 1325 u32 count; 1326 1327 if (pipe >= adev->mode_info.num_crtc) { 1328 DRM_ERROR("Invalid crtc %u\n", pipe); 1329 return -EINVAL; 1330 } 1331 1332 /* The hw increments its frame counter at start of vsync, not at start 1333 * of vblank, as is required by DRM core vblank counter handling. 1334 * Cook the hw count here to make it appear to the caller as if it 1335 * incremented at start of vblank. We measure distance to start of 1336 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1337 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1338 * result by 1 to give the proper appearance to caller. 1339 */ 1340 if (adev->mode_info.crtcs[pipe]) { 1341 /* Repeat readout if needed to provide stable result if 1342 * we cross start of vsync during the queries. 1343 */ 1344 do { 1345 count = amdgpu_display_vblank_get_counter(adev, pipe); 1346 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1347 * vpos as distance to start of vblank, instead of 1348 * regular vertical scanout pos. 1349 */ 1350 stat = amdgpu_display_get_crtc_scanoutpos( 1351 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1352 &vpos, &hpos, NULL, NULL, 1353 &adev->mode_info.crtcs[pipe]->base.hwmode); 1354 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1355 1356 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1357 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1358 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1359 } else { 1360 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1361 pipe, vpos); 1362 1363 /* Bump counter if we are at >= leading edge of vblank, 1364 * but before vsync where vpos would turn negative and 1365 * the hw counter really increments. 1366 */ 1367 if (vpos >= 0) 1368 count++; 1369 } 1370 } else { 1371 /* Fallback to use value as is. */ 1372 count = amdgpu_display_vblank_get_counter(adev, pipe); 1373 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1374 } 1375 1376 return count; 1377 } 1378 1379 /** 1380 * amdgpu_enable_vblank_kms - enable vblank interrupt 1381 * 1382 * @crtc: crtc to enable vblank interrupt for 1383 * 1384 * Enable the interrupt on the requested crtc (all asics). 1385 * Returns 0 on success, -EINVAL on failure. 1386 */ 1387 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1388 { 1389 struct drm_device *dev = crtc->dev; 1390 unsigned int pipe = crtc->index; 1391 struct amdgpu_device *adev = drm_to_adev(dev); 1392 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1393 1394 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1395 } 1396 1397 /** 1398 * amdgpu_disable_vblank_kms - disable vblank interrupt 1399 * 1400 * @crtc: crtc to disable vblank interrupt for 1401 * 1402 * Disable the interrupt on the requested crtc (all asics). 1403 */ 1404 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1405 { 1406 struct drm_device *dev = crtc->dev; 1407 unsigned int pipe = crtc->index; 1408 struct amdgpu_device *adev = drm_to_adev(dev); 1409 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1410 1411 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1412 } 1413 1414 /* 1415 * Debugfs info 1416 */ 1417 #if defined(CONFIG_DEBUG_FS) 1418 1419 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1420 { 1421 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1422 struct drm_amdgpu_info_firmware fw_info; 1423 struct drm_amdgpu_query_fw query_fw; 1424 struct atom_context *ctx = adev->mode_info.atom_context; 1425 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1426 int ret, i; 1427 1428 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1429 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1430 TA_FW_NAME(XGMI), 1431 TA_FW_NAME(RAS), 1432 TA_FW_NAME(HDCP), 1433 TA_FW_NAME(DTM), 1434 TA_FW_NAME(RAP), 1435 TA_FW_NAME(SECUREDISPLAY), 1436 #undef TA_FW_NAME 1437 }; 1438 1439 /* VCE */ 1440 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1441 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1442 if (ret) 1443 return ret; 1444 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1445 fw_info.feature, fw_info.ver); 1446 1447 /* UVD */ 1448 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1449 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1450 if (ret) 1451 return ret; 1452 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1453 fw_info.feature, fw_info.ver); 1454 1455 /* GMC */ 1456 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1457 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1458 if (ret) 1459 return ret; 1460 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1461 fw_info.feature, fw_info.ver); 1462 1463 /* ME */ 1464 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1465 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1466 if (ret) 1467 return ret; 1468 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1469 fw_info.feature, fw_info.ver); 1470 1471 /* PFP */ 1472 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1473 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1474 if (ret) 1475 return ret; 1476 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1477 fw_info.feature, fw_info.ver); 1478 1479 /* CE */ 1480 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1481 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1482 if (ret) 1483 return ret; 1484 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1485 fw_info.feature, fw_info.ver); 1486 1487 /* RLC */ 1488 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1489 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1490 if (ret) 1491 return ret; 1492 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1493 fw_info.feature, fw_info.ver); 1494 1495 /* RLC SAVE RESTORE LIST CNTL */ 1496 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1497 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1498 if (ret) 1499 return ret; 1500 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1501 fw_info.feature, fw_info.ver); 1502 1503 /* RLC SAVE RESTORE LIST GPM MEM */ 1504 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1505 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1506 if (ret) 1507 return ret; 1508 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1509 fw_info.feature, fw_info.ver); 1510 1511 /* RLC SAVE RESTORE LIST SRM MEM */ 1512 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1513 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1514 if (ret) 1515 return ret; 1516 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1517 fw_info.feature, fw_info.ver); 1518 1519 /* RLCP */ 1520 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1521 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1522 if (ret) 1523 return ret; 1524 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1525 fw_info.feature, fw_info.ver); 1526 1527 /* RLCV */ 1528 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1529 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1530 if (ret) 1531 return ret; 1532 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1533 fw_info.feature, fw_info.ver); 1534 1535 /* MEC */ 1536 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1537 query_fw.index = 0; 1538 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1539 if (ret) 1540 return ret; 1541 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1542 fw_info.feature, fw_info.ver); 1543 1544 /* MEC2 */ 1545 if (adev->gfx.mec2_fw) { 1546 query_fw.index = 1; 1547 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1548 if (ret) 1549 return ret; 1550 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1551 fw_info.feature, fw_info.ver); 1552 } 1553 1554 /* IMU */ 1555 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1556 query_fw.index = 0; 1557 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1558 if (ret) 1559 return ret; 1560 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1561 fw_info.feature, fw_info.ver); 1562 1563 /* PSP SOS */ 1564 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1565 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1566 if (ret) 1567 return ret; 1568 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1569 fw_info.feature, fw_info.ver); 1570 1571 1572 /* PSP ASD */ 1573 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1574 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1575 if (ret) 1576 return ret; 1577 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1578 fw_info.feature, fw_info.ver); 1579 1580 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1581 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1582 query_fw.index = i; 1583 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1584 if (ret) 1585 continue; 1586 1587 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1588 ta_fw_name[i], fw_info.feature, fw_info.ver); 1589 } 1590 1591 /* SMC */ 1592 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1593 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1594 if (ret) 1595 return ret; 1596 smu_program = (fw_info.ver >> 24) & 0xff; 1597 smu_major = (fw_info.ver >> 16) & 0xff; 1598 smu_minor = (fw_info.ver >> 8) & 0xff; 1599 smu_debug = (fw_info.ver >> 0) & 0xff; 1600 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1601 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1602 1603 /* SDMA */ 1604 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1605 for (i = 0; i < adev->sdma.num_instances; i++) { 1606 query_fw.index = i; 1607 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1608 if (ret) 1609 return ret; 1610 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1611 i, fw_info.feature, fw_info.ver); 1612 } 1613 1614 /* VCN */ 1615 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1616 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1617 if (ret) 1618 return ret; 1619 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1620 fw_info.feature, fw_info.ver); 1621 1622 /* DMCU */ 1623 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1624 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1625 if (ret) 1626 return ret; 1627 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1628 fw_info.feature, fw_info.ver); 1629 1630 /* DMCUB */ 1631 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1632 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1633 if (ret) 1634 return ret; 1635 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1636 fw_info.feature, fw_info.ver); 1637 1638 /* TOC */ 1639 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1640 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1641 if (ret) 1642 return ret; 1643 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1644 fw_info.feature, fw_info.ver); 1645 1646 /* CAP */ 1647 if (adev->psp.cap_fw) { 1648 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1649 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1650 if (ret) 1651 return ret; 1652 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1653 fw_info.feature, fw_info.ver); 1654 } 1655 1656 /* MES_KIQ */ 1657 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1658 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1659 if (ret) 1660 return ret; 1661 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1662 fw_info.feature, fw_info.ver); 1663 1664 /* MES */ 1665 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1666 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1667 if (ret) 1668 return ret; 1669 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1670 fw_info.feature, fw_info.ver); 1671 1672 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1673 1674 return 0; 1675 } 1676 1677 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1678 1679 #endif 1680 1681 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1682 { 1683 #if defined(CONFIG_DEBUG_FS) 1684 struct drm_minor *minor = adev_to_drm(adev)->primary; 1685 struct dentry *root = minor->debugfs_root; 1686 1687 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1688 adev, &amdgpu_debugfs_firmware_info_fops); 1689 1690 #endif 1691 } 1692