1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_sched.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/pm_runtime.h> 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * amdgpu_driver_unload_kms - Main unload function for KMS. 43 * 44 * @dev: drm dev pointer 45 * 46 * This is the main unload function for KMS (all asics). 47 * Returns 0 on success. 48 */ 49 void amdgpu_driver_unload_kms(struct drm_device *dev) 50 { 51 struct amdgpu_device *adev = dev->dev_private; 52 53 if (adev == NULL) 54 return; 55 56 if (adev->rmmio == NULL) 57 goto done_free; 58 59 if (amdgpu_sriov_vf(adev)) 60 amdgpu_virt_request_full_gpu(adev, false); 61 62 if (amdgpu_device_is_px(dev)) { 63 pm_runtime_get_sync(dev->dev); 64 pm_runtime_forbid(dev->dev); 65 } 66 67 amdgpu_acpi_fini(adev); 68 69 amdgpu_device_fini(adev); 70 71 done_free: 72 kfree(adev); 73 dev->dev_private = NULL; 74 } 75 76 /** 77 * amdgpu_driver_load_kms - Main load function for KMS. 78 * 79 * @dev: drm dev pointer 80 * @flags: device flags 81 * 82 * This is the main load function for KMS (all asics). 83 * Returns 0 on success, error on failure. 84 */ 85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 86 { 87 struct amdgpu_device *adev; 88 int r, acpi_status; 89 90 #ifdef CONFIG_DRM_AMDGPU_SI 91 if (!amdgpu_si_support) { 92 switch (flags & AMD_ASIC_MASK) { 93 case CHIP_TAHITI: 94 case CHIP_PITCAIRN: 95 case CHIP_VERDE: 96 case CHIP_OLAND: 97 case CHIP_HAINAN: 98 dev_info(dev->dev, 99 "SI support provided by radeon.\n"); 100 dev_info(dev->dev, 101 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 102 ); 103 return -ENODEV; 104 } 105 } 106 #endif 107 #ifdef CONFIG_DRM_AMDGPU_CIK 108 if (!amdgpu_cik_support) { 109 switch (flags & AMD_ASIC_MASK) { 110 case CHIP_KAVERI: 111 case CHIP_BONAIRE: 112 case CHIP_HAWAII: 113 case CHIP_KABINI: 114 case CHIP_MULLINS: 115 dev_info(dev->dev, 116 "CIK support provided by radeon.\n"); 117 dev_info(dev->dev, 118 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 119 ); 120 return -ENODEV; 121 } 122 } 123 #endif 124 125 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 126 if (adev == NULL) { 127 return -ENOMEM; 128 } 129 dev->dev_private = (void *)adev; 130 131 if ((amdgpu_runtime_pm != 0) && 132 amdgpu_has_atpx() && 133 (amdgpu_is_atpx_hybrid() || 134 amdgpu_has_atpx_dgpu_power_cntl()) && 135 ((flags & AMD_IS_APU) == 0) && 136 !pci_is_thunderbolt_attached(dev->pdev)) 137 flags |= AMD_IS_PX; 138 139 /* amdgpu_device_init should report only fatal error 140 * like memory allocation failure or iomapping failure, 141 * or memory manager initialization failure, it must 142 * properly initialize the GPU MC controller and permit 143 * VRAM allocation 144 */ 145 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 146 if (r) { 147 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 148 goto out; 149 } 150 151 /* Call ACPI methods: require modeset init 152 * but failure is not fatal 153 */ 154 if (!r) { 155 acpi_status = amdgpu_acpi_init(adev); 156 if (acpi_status) 157 dev_dbg(&dev->pdev->dev, 158 "Error during ACPI methods call\n"); 159 } 160 161 if (amdgpu_device_is_px(dev)) { 162 pm_runtime_use_autosuspend(dev->dev); 163 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 164 pm_runtime_set_active(dev->dev); 165 pm_runtime_allow(dev->dev); 166 pm_runtime_mark_last_busy(dev->dev); 167 pm_runtime_put_autosuspend(dev->dev); 168 } 169 170 out: 171 if (r) { 172 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 173 if (adev->rmmio && amdgpu_device_is_px(dev)) 174 pm_runtime_put_noidle(dev->dev); 175 amdgpu_driver_unload_kms(dev); 176 } 177 178 return r; 179 } 180 181 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 182 struct drm_amdgpu_query_fw *query_fw, 183 struct amdgpu_device *adev) 184 { 185 switch (query_fw->fw_type) { 186 case AMDGPU_INFO_FW_VCE: 187 fw_info->ver = adev->vce.fw_version; 188 fw_info->feature = adev->vce.fb_version; 189 break; 190 case AMDGPU_INFO_FW_UVD: 191 fw_info->ver = adev->uvd.fw_version; 192 fw_info->feature = 0; 193 break; 194 case AMDGPU_INFO_FW_VCN: 195 fw_info->ver = adev->vcn.fw_version; 196 fw_info->feature = 0; 197 break; 198 case AMDGPU_INFO_FW_GMC: 199 fw_info->ver = adev->gmc.fw_version; 200 fw_info->feature = 0; 201 break; 202 case AMDGPU_INFO_FW_GFX_ME: 203 fw_info->ver = adev->gfx.me_fw_version; 204 fw_info->feature = adev->gfx.me_feature_version; 205 break; 206 case AMDGPU_INFO_FW_GFX_PFP: 207 fw_info->ver = adev->gfx.pfp_fw_version; 208 fw_info->feature = adev->gfx.pfp_feature_version; 209 break; 210 case AMDGPU_INFO_FW_GFX_CE: 211 fw_info->ver = adev->gfx.ce_fw_version; 212 fw_info->feature = adev->gfx.ce_feature_version; 213 break; 214 case AMDGPU_INFO_FW_GFX_RLC: 215 fw_info->ver = adev->gfx.rlc_fw_version; 216 fw_info->feature = adev->gfx.rlc_feature_version; 217 break; 218 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 219 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 220 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 221 break; 222 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 223 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 224 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 225 break; 226 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 227 fw_info->ver = adev->gfx.rlc_srls_fw_version; 228 fw_info->feature = adev->gfx.rlc_srls_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_MEC: 231 if (query_fw->index == 0) { 232 fw_info->ver = adev->gfx.mec_fw_version; 233 fw_info->feature = adev->gfx.mec_feature_version; 234 } else if (query_fw->index == 1) { 235 fw_info->ver = adev->gfx.mec2_fw_version; 236 fw_info->feature = adev->gfx.mec2_feature_version; 237 } else 238 return -EINVAL; 239 break; 240 case AMDGPU_INFO_FW_SMC: 241 fw_info->ver = adev->pm.fw_version; 242 fw_info->feature = 0; 243 break; 244 case AMDGPU_INFO_FW_SDMA: 245 if (query_fw->index >= adev->sdma.num_instances) 246 return -EINVAL; 247 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 248 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 249 break; 250 case AMDGPU_INFO_FW_SOS: 251 fw_info->ver = adev->psp.sos_fw_version; 252 fw_info->feature = adev->psp.sos_feature_version; 253 break; 254 case AMDGPU_INFO_FW_ASD: 255 fw_info->ver = adev->psp.asd_fw_version; 256 fw_info->feature = adev->psp.asd_feature_version; 257 break; 258 default: 259 return -EINVAL; 260 } 261 return 0; 262 } 263 264 /* 265 * Userspace get information ioctl 266 */ 267 /** 268 * amdgpu_info_ioctl - answer a device specific request. 269 * 270 * @adev: amdgpu device pointer 271 * @data: request object 272 * @filp: drm filp 273 * 274 * This function is used to pass device specific parameters to the userspace 275 * drivers. Examples include: pci device id, pipeline parms, tiling params, 276 * etc. (all asics). 277 * Returns 0 on success, -EINVAL on failure. 278 */ 279 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 280 { 281 struct amdgpu_device *adev = dev->dev_private; 282 struct drm_amdgpu_info *info = data; 283 struct amdgpu_mode_info *minfo = &adev->mode_info; 284 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 285 uint32_t size = info->return_size; 286 struct drm_crtc *crtc; 287 uint32_t ui32 = 0; 288 uint64_t ui64 = 0; 289 int i, j, found; 290 int ui32_size = sizeof(ui32); 291 292 if (!info->return_size || !info->return_pointer) 293 return -EINVAL; 294 295 /* Ensure IB tests are run on ring */ 296 flush_delayed_work(&adev->late_init_work); 297 298 switch (info->query) { 299 case AMDGPU_INFO_ACCEL_WORKING: 300 ui32 = adev->accel_working; 301 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 302 case AMDGPU_INFO_CRTC_FROM_ID: 303 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 304 crtc = (struct drm_crtc *)minfo->crtcs[i]; 305 if (crtc && crtc->base.id == info->mode_crtc.id) { 306 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 307 ui32 = amdgpu_crtc->crtc_id; 308 found = 1; 309 break; 310 } 311 } 312 if (!found) { 313 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 314 return -EINVAL; 315 } 316 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 317 case AMDGPU_INFO_HW_IP_INFO: { 318 struct drm_amdgpu_info_hw_ip ip = {}; 319 enum amd_ip_block_type type; 320 uint32_t ring_mask = 0; 321 uint32_t ib_start_alignment = 0; 322 uint32_t ib_size_alignment = 0; 323 324 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 325 return -EINVAL; 326 327 switch (info->query_hw_ip.type) { 328 case AMDGPU_HW_IP_GFX: 329 type = AMD_IP_BLOCK_TYPE_GFX; 330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 331 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 332 ib_start_alignment = 32; 333 ib_size_alignment = 32; 334 break; 335 case AMDGPU_HW_IP_COMPUTE: 336 type = AMD_IP_BLOCK_TYPE_GFX; 337 for (i = 0; i < adev->gfx.num_compute_rings; i++) 338 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 339 ib_start_alignment = 32; 340 ib_size_alignment = 32; 341 break; 342 case AMDGPU_HW_IP_DMA: 343 type = AMD_IP_BLOCK_TYPE_SDMA; 344 for (i = 0; i < adev->sdma.num_instances; i++) 345 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 346 ib_start_alignment = 256; 347 ib_size_alignment = 4; 348 break; 349 case AMDGPU_HW_IP_UVD: 350 type = AMD_IP_BLOCK_TYPE_UVD; 351 for (i = 0; i < adev->uvd.num_uvd_inst; i++) 352 ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i); 353 ib_start_alignment = 64; 354 ib_size_alignment = 64; 355 break; 356 case AMDGPU_HW_IP_VCE: 357 type = AMD_IP_BLOCK_TYPE_VCE; 358 for (i = 0; i < adev->vce.num_rings; i++) 359 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 360 ib_start_alignment = 4; 361 ib_size_alignment = 1; 362 break; 363 case AMDGPU_HW_IP_UVD_ENC: 364 type = AMD_IP_BLOCK_TYPE_UVD; 365 for (i = 0; i < adev->uvd.num_uvd_inst; i++) 366 for (j = 0; j < adev->uvd.num_enc_rings; j++) 367 ring_mask |= 368 ((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) << 369 (j + i * adev->uvd.num_enc_rings)); 370 ib_start_alignment = 64; 371 ib_size_alignment = 64; 372 break; 373 case AMDGPU_HW_IP_VCN_DEC: 374 type = AMD_IP_BLOCK_TYPE_VCN; 375 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; 376 ib_start_alignment = 16; 377 ib_size_alignment = 16; 378 break; 379 case AMDGPU_HW_IP_VCN_ENC: 380 type = AMD_IP_BLOCK_TYPE_VCN; 381 for (i = 0; i < adev->vcn.num_enc_rings; i++) 382 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); 383 ib_start_alignment = 64; 384 ib_size_alignment = 1; 385 break; 386 case AMDGPU_HW_IP_VCN_JPEG: 387 type = AMD_IP_BLOCK_TYPE_VCN; 388 ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0; 389 ib_start_alignment = 16; 390 ib_size_alignment = 16; 391 break; 392 default: 393 return -EINVAL; 394 } 395 396 for (i = 0; i < adev->num_ip_blocks; i++) { 397 if (adev->ip_blocks[i].version->type == type && 398 adev->ip_blocks[i].status.valid) { 399 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 400 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 401 ip.capabilities_flags = 0; 402 ip.available_rings = ring_mask; 403 ip.ib_start_alignment = ib_start_alignment; 404 ip.ib_size_alignment = ib_size_alignment; 405 break; 406 } 407 } 408 return copy_to_user(out, &ip, 409 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 410 } 411 case AMDGPU_INFO_HW_IP_COUNT: { 412 enum amd_ip_block_type type; 413 uint32_t count = 0; 414 415 switch (info->query_hw_ip.type) { 416 case AMDGPU_HW_IP_GFX: 417 type = AMD_IP_BLOCK_TYPE_GFX; 418 break; 419 case AMDGPU_HW_IP_COMPUTE: 420 type = AMD_IP_BLOCK_TYPE_GFX; 421 break; 422 case AMDGPU_HW_IP_DMA: 423 type = AMD_IP_BLOCK_TYPE_SDMA; 424 break; 425 case AMDGPU_HW_IP_UVD: 426 type = AMD_IP_BLOCK_TYPE_UVD; 427 break; 428 case AMDGPU_HW_IP_VCE: 429 type = AMD_IP_BLOCK_TYPE_VCE; 430 break; 431 case AMDGPU_HW_IP_UVD_ENC: 432 type = AMD_IP_BLOCK_TYPE_UVD; 433 break; 434 case AMDGPU_HW_IP_VCN_DEC: 435 case AMDGPU_HW_IP_VCN_ENC: 436 case AMDGPU_HW_IP_VCN_JPEG: 437 type = AMD_IP_BLOCK_TYPE_VCN; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 for (i = 0; i < adev->num_ip_blocks; i++) 444 if (adev->ip_blocks[i].version->type == type && 445 adev->ip_blocks[i].status.valid && 446 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 447 count++; 448 449 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 450 } 451 case AMDGPU_INFO_TIMESTAMP: 452 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 453 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 454 case AMDGPU_INFO_FW_VERSION: { 455 struct drm_amdgpu_info_firmware fw_info; 456 int ret; 457 458 /* We only support one instance of each IP block right now. */ 459 if (info->query_fw.ip_instance != 0) 460 return -EINVAL; 461 462 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 463 if (ret) 464 return ret; 465 466 return copy_to_user(out, &fw_info, 467 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 468 } 469 case AMDGPU_INFO_NUM_BYTES_MOVED: 470 ui64 = atomic64_read(&adev->num_bytes_moved); 471 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 472 case AMDGPU_INFO_NUM_EVICTIONS: 473 ui64 = atomic64_read(&adev->num_evictions); 474 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 475 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 476 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 477 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 478 case AMDGPU_INFO_VRAM_USAGE: 479 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 480 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 481 case AMDGPU_INFO_VIS_VRAM_USAGE: 482 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 483 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 484 case AMDGPU_INFO_GTT_USAGE: 485 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 486 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 487 case AMDGPU_INFO_GDS_CONFIG: { 488 struct drm_amdgpu_info_gds gds_info; 489 490 memset(&gds_info, 0, sizeof(gds_info)); 491 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 492 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 493 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 494 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 495 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 496 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 497 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 498 return copy_to_user(out, &gds_info, 499 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 500 } 501 case AMDGPU_INFO_VRAM_GTT: { 502 struct drm_amdgpu_info_vram_gtt vram_gtt; 503 504 vram_gtt.vram_size = adev->gmc.real_vram_size; 505 vram_gtt.vram_size -= adev->vram_pin_size; 506 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size; 507 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 508 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 509 vram_gtt.gtt_size *= PAGE_SIZE; 510 vram_gtt.gtt_size -= adev->gart_pin_size; 511 return copy_to_user(out, &vram_gtt, 512 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 513 } 514 case AMDGPU_INFO_MEMORY: { 515 struct drm_amdgpu_memory_info mem; 516 517 memset(&mem, 0, sizeof(mem)); 518 mem.vram.total_heap_size = adev->gmc.real_vram_size; 519 mem.vram.usable_heap_size = 520 adev->gmc.real_vram_size - adev->vram_pin_size; 521 mem.vram.heap_usage = 522 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 523 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 524 525 mem.cpu_accessible_vram.total_heap_size = 526 adev->gmc.visible_vram_size; 527 mem.cpu_accessible_vram.usable_heap_size = 528 adev->gmc.visible_vram_size - 529 (adev->vram_pin_size - adev->invisible_pin_size); 530 mem.cpu_accessible_vram.heap_usage = 531 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 532 mem.cpu_accessible_vram.max_allocation = 533 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 534 535 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 536 mem.gtt.total_heap_size *= PAGE_SIZE; 537 mem.gtt.usable_heap_size = mem.gtt.total_heap_size 538 - adev->gart_pin_size; 539 mem.gtt.heap_usage = 540 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 541 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 542 543 return copy_to_user(out, &mem, 544 min((size_t)size, sizeof(mem))) 545 ? -EFAULT : 0; 546 } 547 case AMDGPU_INFO_READ_MMR_REG: { 548 unsigned n, alloc_size; 549 uint32_t *regs; 550 unsigned se_num = (info->read_mmr_reg.instance >> 551 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 552 AMDGPU_INFO_MMR_SE_INDEX_MASK; 553 unsigned sh_num = (info->read_mmr_reg.instance >> 554 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 555 AMDGPU_INFO_MMR_SH_INDEX_MASK; 556 557 /* set full masks if the userspace set all bits 558 * in the bitfields */ 559 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 560 se_num = 0xffffffff; 561 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 562 sh_num = 0xffffffff; 563 564 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 565 if (!regs) 566 return -ENOMEM; 567 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 568 569 for (i = 0; i < info->read_mmr_reg.count; i++) 570 if (amdgpu_asic_read_register(adev, se_num, sh_num, 571 info->read_mmr_reg.dword_offset + i, 572 ®s[i])) { 573 DRM_DEBUG_KMS("unallowed offset %#x\n", 574 info->read_mmr_reg.dword_offset + i); 575 kfree(regs); 576 return -EFAULT; 577 } 578 n = copy_to_user(out, regs, min(size, alloc_size)); 579 kfree(regs); 580 return n ? -EFAULT : 0; 581 } 582 case AMDGPU_INFO_DEV_INFO: { 583 struct drm_amdgpu_info_device dev_info = {}; 584 uint64_t vm_size; 585 586 dev_info.device_id = dev->pdev->device; 587 dev_info.chip_rev = adev->rev_id; 588 dev_info.external_rev = adev->external_rev_id; 589 dev_info.pci_rev = dev->pdev->revision; 590 dev_info.family = adev->family; 591 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 592 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 593 /* return all clocks in KHz */ 594 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 595 if (adev->pm.dpm_enabled) { 596 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 597 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 598 } else { 599 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 600 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 601 } 602 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 603 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 604 adev->gfx.config.max_shader_engines; 605 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 606 dev_info._pad = 0; 607 dev_info.ids_flags = 0; 608 if (adev->flags & AMD_IS_APU) 609 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 610 if (amdgpu_sriov_vf(adev)) 611 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 612 613 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 614 vm_size -= AMDGPU_VA_RESERVED_SIZE; 615 616 /* Older VCE FW versions are buggy and can handle only 40bits */ 617 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 618 vm_size = min(vm_size, 1ULL << 40); 619 620 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 621 dev_info.virtual_address_max = 622 min(vm_size, AMDGPU_VA_HOLE_START); 623 624 if (vm_size > AMDGPU_VA_HOLE_START) { 625 dev_info.high_va_offset = AMDGPU_VA_HOLE_END; 626 dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; 627 } 628 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 629 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 630 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 631 dev_info.cu_active_number = adev->gfx.cu_info.number; 632 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 633 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 634 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 635 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 636 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 637 sizeof(adev->gfx.cu_info.bitmap)); 638 dev_info.vram_type = adev->gmc.vram_type; 639 dev_info.vram_bit_width = adev->gmc.vram_width; 640 dev_info.vce_harvest_config = adev->vce.harvest_config; 641 dev_info.gc_double_offchip_lds_buf = 642 adev->gfx.config.double_offchip_lds_buf; 643 644 if (amdgpu_ngg) { 645 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 646 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 647 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 648 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 649 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 650 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 651 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 652 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 653 } 654 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 655 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 656 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 657 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 658 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 659 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 660 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 661 662 return copy_to_user(out, &dev_info, 663 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 664 } 665 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 666 unsigned i; 667 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 668 struct amd_vce_state *vce_state; 669 670 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 671 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 672 if (vce_state) { 673 vce_clk_table.entries[i].sclk = vce_state->sclk; 674 vce_clk_table.entries[i].mclk = vce_state->mclk; 675 vce_clk_table.entries[i].eclk = vce_state->evclk; 676 vce_clk_table.num_valid_entries++; 677 } 678 } 679 680 return copy_to_user(out, &vce_clk_table, 681 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 682 } 683 case AMDGPU_INFO_VBIOS: { 684 uint32_t bios_size = adev->bios_size; 685 686 switch (info->vbios_info.type) { 687 case AMDGPU_INFO_VBIOS_SIZE: 688 return copy_to_user(out, &bios_size, 689 min((size_t)size, sizeof(bios_size))) 690 ? -EFAULT : 0; 691 case AMDGPU_INFO_VBIOS_IMAGE: { 692 uint8_t *bios; 693 uint32_t bios_offset = info->vbios_info.offset; 694 695 if (bios_offset >= bios_size) 696 return -EINVAL; 697 698 bios = adev->bios + bios_offset; 699 return copy_to_user(out, bios, 700 min((size_t)size, (size_t)(bios_size - bios_offset))) 701 ? -EFAULT : 0; 702 } 703 default: 704 DRM_DEBUG_KMS("Invalid request %d\n", 705 info->vbios_info.type); 706 return -EINVAL; 707 } 708 } 709 case AMDGPU_INFO_NUM_HANDLES: { 710 struct drm_amdgpu_info_num_handles handle; 711 712 switch (info->query_hw_ip.type) { 713 case AMDGPU_HW_IP_UVD: 714 /* Starting Polaris, we support unlimited UVD handles */ 715 if (adev->asic_type < CHIP_POLARIS10) { 716 handle.uvd_max_handles = adev->uvd.max_handles; 717 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 718 719 return copy_to_user(out, &handle, 720 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 721 } else { 722 return -ENODATA; 723 } 724 725 break; 726 default: 727 return -EINVAL; 728 } 729 } 730 case AMDGPU_INFO_SENSOR: { 731 if (!adev->pm.dpm_enabled) 732 return -ENOENT; 733 734 switch (info->sensor_info.type) { 735 case AMDGPU_INFO_SENSOR_GFX_SCLK: 736 /* get sclk in Mhz */ 737 if (amdgpu_dpm_read_sensor(adev, 738 AMDGPU_PP_SENSOR_GFX_SCLK, 739 (void *)&ui32, &ui32_size)) { 740 return -EINVAL; 741 } 742 ui32 /= 100; 743 break; 744 case AMDGPU_INFO_SENSOR_GFX_MCLK: 745 /* get mclk in Mhz */ 746 if (amdgpu_dpm_read_sensor(adev, 747 AMDGPU_PP_SENSOR_GFX_MCLK, 748 (void *)&ui32, &ui32_size)) { 749 return -EINVAL; 750 } 751 ui32 /= 100; 752 break; 753 case AMDGPU_INFO_SENSOR_GPU_TEMP: 754 /* get temperature in millidegrees C */ 755 if (amdgpu_dpm_read_sensor(adev, 756 AMDGPU_PP_SENSOR_GPU_TEMP, 757 (void *)&ui32, &ui32_size)) { 758 return -EINVAL; 759 } 760 break; 761 case AMDGPU_INFO_SENSOR_GPU_LOAD: 762 /* get GPU load */ 763 if (amdgpu_dpm_read_sensor(adev, 764 AMDGPU_PP_SENSOR_GPU_LOAD, 765 (void *)&ui32, &ui32_size)) { 766 return -EINVAL; 767 } 768 break; 769 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 770 /* get average GPU power */ 771 if (amdgpu_dpm_read_sensor(adev, 772 AMDGPU_PP_SENSOR_GPU_POWER, 773 (void *)&ui32, &ui32_size)) { 774 return -EINVAL; 775 } 776 ui32 >>= 8; 777 break; 778 case AMDGPU_INFO_SENSOR_VDDNB: 779 /* get VDDNB in millivolts */ 780 if (amdgpu_dpm_read_sensor(adev, 781 AMDGPU_PP_SENSOR_VDDNB, 782 (void *)&ui32, &ui32_size)) { 783 return -EINVAL; 784 } 785 break; 786 case AMDGPU_INFO_SENSOR_VDDGFX: 787 /* get VDDGFX in millivolts */ 788 if (amdgpu_dpm_read_sensor(adev, 789 AMDGPU_PP_SENSOR_VDDGFX, 790 (void *)&ui32, &ui32_size)) { 791 return -EINVAL; 792 } 793 break; 794 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 795 /* get stable pstate sclk in Mhz */ 796 if (amdgpu_dpm_read_sensor(adev, 797 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 798 (void *)&ui32, &ui32_size)) { 799 return -EINVAL; 800 } 801 ui32 /= 100; 802 break; 803 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 804 /* get stable pstate mclk in Mhz */ 805 if (amdgpu_dpm_read_sensor(adev, 806 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 807 (void *)&ui32, &ui32_size)) { 808 return -EINVAL; 809 } 810 ui32 /= 100; 811 break; 812 default: 813 DRM_DEBUG_KMS("Invalid request %d\n", 814 info->sensor_info.type); 815 return -EINVAL; 816 } 817 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 818 } 819 case AMDGPU_INFO_VRAM_LOST_COUNTER: 820 ui32 = atomic_read(&adev->vram_lost_counter); 821 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 822 default: 823 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 824 return -EINVAL; 825 } 826 return 0; 827 } 828 829 830 /* 831 * Outdated mess for old drm with Xorg being in charge (void function now). 832 */ 833 /** 834 * amdgpu_driver_lastclose_kms - drm callback for last close 835 * 836 * @dev: drm dev pointer 837 * 838 * Switch vga_switcheroo state after last close (all asics). 839 */ 840 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 841 { 842 drm_fb_helper_lastclose(dev); 843 vga_switcheroo_process_delayed_switch(); 844 } 845 846 /** 847 * amdgpu_driver_open_kms - drm callback for open 848 * 849 * @dev: drm dev pointer 850 * @file_priv: drm file 851 * 852 * On device open, init vm on cayman+ (all asics). 853 * Returns 0 on success, error on failure. 854 */ 855 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 856 { 857 struct amdgpu_device *adev = dev->dev_private; 858 struct amdgpu_fpriv *fpriv; 859 int r, pasid; 860 861 file_priv->driver_priv = NULL; 862 863 r = pm_runtime_get_sync(dev->dev); 864 if (r < 0) 865 return r; 866 867 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 868 if (unlikely(!fpriv)) { 869 r = -ENOMEM; 870 goto out_suspend; 871 } 872 873 pasid = amdgpu_pasid_alloc(16); 874 if (pasid < 0) { 875 dev_warn(adev->dev, "No more PASIDs available!"); 876 pasid = 0; 877 } 878 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 879 if (r) 880 goto error_pasid; 881 882 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 883 if (!fpriv->prt_va) { 884 r = -ENOMEM; 885 goto error_vm; 886 } 887 888 if (amdgpu_sriov_vf(adev)) { 889 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); 890 if (r) 891 goto error_vm; 892 } 893 894 mutex_init(&fpriv->bo_list_lock); 895 idr_init(&fpriv->bo_list_handles); 896 897 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 898 899 file_priv->driver_priv = fpriv; 900 goto out_suspend; 901 902 error_vm: 903 amdgpu_vm_fini(adev, &fpriv->vm); 904 905 error_pasid: 906 if (pasid) 907 amdgpu_pasid_free(pasid); 908 909 kfree(fpriv); 910 911 out_suspend: 912 pm_runtime_mark_last_busy(dev->dev); 913 pm_runtime_put_autosuspend(dev->dev); 914 915 return r; 916 } 917 918 /** 919 * amdgpu_driver_postclose_kms - drm callback for post close 920 * 921 * @dev: drm dev pointer 922 * @file_priv: drm file 923 * 924 * On device post close, tear down vm on cayman+ (all asics). 925 */ 926 void amdgpu_driver_postclose_kms(struct drm_device *dev, 927 struct drm_file *file_priv) 928 { 929 struct amdgpu_device *adev = dev->dev_private; 930 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 931 struct amdgpu_bo_list *list; 932 struct amdgpu_bo *pd; 933 unsigned int pasid; 934 int handle; 935 936 if (!fpriv) 937 return; 938 939 pm_runtime_get_sync(dev->dev); 940 941 if (adev->asic_type != CHIP_RAVEN) { 942 amdgpu_uvd_free_handles(adev, file_priv); 943 amdgpu_vce_free_handles(adev, file_priv); 944 } 945 946 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 947 948 if (amdgpu_sriov_vf(adev)) { 949 /* TODO: how to handle reserve failure */ 950 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 951 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 952 fpriv->csa_va = NULL; 953 amdgpu_bo_unreserve(adev->virt.csa_obj); 954 } 955 956 pasid = fpriv->vm.pasid; 957 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 958 959 amdgpu_vm_fini(adev, &fpriv->vm); 960 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 961 962 if (pasid) 963 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); 964 amdgpu_bo_unref(&pd); 965 966 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 967 amdgpu_bo_list_free(list); 968 969 idr_destroy(&fpriv->bo_list_handles); 970 mutex_destroy(&fpriv->bo_list_lock); 971 972 kfree(fpriv); 973 file_priv->driver_priv = NULL; 974 975 pm_runtime_mark_last_busy(dev->dev); 976 pm_runtime_put_autosuspend(dev->dev); 977 } 978 979 /* 980 * VBlank related functions. 981 */ 982 /** 983 * amdgpu_get_vblank_counter_kms - get frame count 984 * 985 * @dev: drm dev pointer 986 * @pipe: crtc to get the frame count from 987 * 988 * Gets the frame count on the requested crtc (all asics). 989 * Returns frame count on success, -EINVAL on failure. 990 */ 991 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 992 { 993 struct amdgpu_device *adev = dev->dev_private; 994 int vpos, hpos, stat; 995 u32 count; 996 997 if (pipe >= adev->mode_info.num_crtc) { 998 DRM_ERROR("Invalid crtc %u\n", pipe); 999 return -EINVAL; 1000 } 1001 1002 /* The hw increments its frame counter at start of vsync, not at start 1003 * of vblank, as is required by DRM core vblank counter handling. 1004 * Cook the hw count here to make it appear to the caller as if it 1005 * incremented at start of vblank. We measure distance to start of 1006 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1007 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1008 * result by 1 to give the proper appearance to caller. 1009 */ 1010 if (adev->mode_info.crtcs[pipe]) { 1011 /* Repeat readout if needed to provide stable result if 1012 * we cross start of vsync during the queries. 1013 */ 1014 do { 1015 count = amdgpu_display_vblank_get_counter(adev, pipe); 1016 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1017 * vpos as distance to start of vblank, instead of 1018 * regular vertical scanout pos. 1019 */ 1020 stat = amdgpu_display_get_crtc_scanoutpos( 1021 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1022 &vpos, &hpos, NULL, NULL, 1023 &adev->mode_info.crtcs[pipe]->base.hwmode); 1024 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1025 1026 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1027 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1028 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1029 } else { 1030 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1031 pipe, vpos); 1032 1033 /* Bump counter if we are at >= leading edge of vblank, 1034 * but before vsync where vpos would turn negative and 1035 * the hw counter really increments. 1036 */ 1037 if (vpos >= 0) 1038 count++; 1039 } 1040 } else { 1041 /* Fallback to use value as is. */ 1042 count = amdgpu_display_vblank_get_counter(adev, pipe); 1043 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1044 } 1045 1046 return count; 1047 } 1048 1049 /** 1050 * amdgpu_enable_vblank_kms - enable vblank interrupt 1051 * 1052 * @dev: drm dev pointer 1053 * @pipe: crtc to enable vblank interrupt for 1054 * 1055 * Enable the interrupt on the requested crtc (all asics). 1056 * Returns 0 on success, -EINVAL on failure. 1057 */ 1058 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1059 { 1060 struct amdgpu_device *adev = dev->dev_private; 1061 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1062 1063 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1064 } 1065 1066 /** 1067 * amdgpu_disable_vblank_kms - disable vblank interrupt 1068 * 1069 * @dev: drm dev pointer 1070 * @pipe: crtc to disable vblank interrupt for 1071 * 1072 * Disable the interrupt on the requested crtc (all asics). 1073 */ 1074 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1075 { 1076 struct amdgpu_device *adev = dev->dev_private; 1077 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1078 1079 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1080 } 1081 1082 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1083 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1084 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1085 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1086 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1087 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1088 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1089 /* KMS */ 1090 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1091 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1092 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1093 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1094 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1095 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1096 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1097 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1098 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1099 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1100 }; 1101 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1102 1103 /* 1104 * Debugfs info 1105 */ 1106 #if defined(CONFIG_DEBUG_FS) 1107 1108 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1109 { 1110 struct drm_info_node *node = (struct drm_info_node *) m->private; 1111 struct drm_device *dev = node->minor->dev; 1112 struct amdgpu_device *adev = dev->dev_private; 1113 struct drm_amdgpu_info_firmware fw_info; 1114 struct drm_amdgpu_query_fw query_fw; 1115 struct atom_context *ctx = adev->mode_info.atom_context; 1116 int ret, i; 1117 1118 /* VCE */ 1119 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1120 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1121 if (ret) 1122 return ret; 1123 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1124 fw_info.feature, fw_info.ver); 1125 1126 /* UVD */ 1127 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1128 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1129 if (ret) 1130 return ret; 1131 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1132 fw_info.feature, fw_info.ver); 1133 1134 /* GMC */ 1135 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1136 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1137 if (ret) 1138 return ret; 1139 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1140 fw_info.feature, fw_info.ver); 1141 1142 /* ME */ 1143 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1144 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1145 if (ret) 1146 return ret; 1147 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1148 fw_info.feature, fw_info.ver); 1149 1150 /* PFP */ 1151 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1152 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1153 if (ret) 1154 return ret; 1155 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1156 fw_info.feature, fw_info.ver); 1157 1158 /* CE */ 1159 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1160 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1161 if (ret) 1162 return ret; 1163 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1164 fw_info.feature, fw_info.ver); 1165 1166 /* RLC */ 1167 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1168 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1169 if (ret) 1170 return ret; 1171 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1172 fw_info.feature, fw_info.ver); 1173 1174 /* RLC SAVE RESTORE LIST CNTL */ 1175 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1176 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1177 if (ret) 1178 return ret; 1179 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1180 fw_info.feature, fw_info.ver); 1181 1182 /* RLC SAVE RESTORE LIST GPM MEM */ 1183 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1184 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1185 if (ret) 1186 return ret; 1187 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1188 fw_info.feature, fw_info.ver); 1189 1190 /* RLC SAVE RESTORE LIST SRM MEM */ 1191 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1192 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1193 if (ret) 1194 return ret; 1195 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1196 fw_info.feature, fw_info.ver); 1197 1198 /* MEC */ 1199 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1200 query_fw.index = 0; 1201 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1202 if (ret) 1203 return ret; 1204 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1205 fw_info.feature, fw_info.ver); 1206 1207 /* MEC2 */ 1208 if (adev->asic_type == CHIP_KAVERI || 1209 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1210 query_fw.index = 1; 1211 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1212 if (ret) 1213 return ret; 1214 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1215 fw_info.feature, fw_info.ver); 1216 } 1217 1218 /* PSP SOS */ 1219 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1220 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1221 if (ret) 1222 return ret; 1223 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1224 fw_info.feature, fw_info.ver); 1225 1226 1227 /* PSP ASD */ 1228 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1229 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1230 if (ret) 1231 return ret; 1232 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1233 fw_info.feature, fw_info.ver); 1234 1235 /* SMC */ 1236 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1237 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1238 if (ret) 1239 return ret; 1240 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1241 fw_info.feature, fw_info.ver); 1242 1243 /* SDMA */ 1244 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1245 for (i = 0; i < adev->sdma.num_instances; i++) { 1246 query_fw.index = i; 1247 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1248 if (ret) 1249 return ret; 1250 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1251 i, fw_info.feature, fw_info.ver); 1252 } 1253 1254 /* VCN */ 1255 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1256 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1257 if (ret) 1258 return ret; 1259 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1260 fw_info.feature, fw_info.ver); 1261 1262 1263 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1264 1265 return 0; 1266 } 1267 1268 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1269 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1270 }; 1271 #endif 1272 1273 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1274 { 1275 #if defined(CONFIG_DEBUG_FS) 1276 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1277 ARRAY_SIZE(amdgpu_firmware_info_list)); 1278 #else 1279 return 0; 1280 #endif 1281 } 1282