1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "atom.h" 34 35 #include <linux/vga_switcheroo.h> 36 #include <linux/slab.h> 37 #include <linux/uaccess.h> 38 #include <linux/pci.h> 39 #include <linux/pm_runtime.h> 40 #include "amdgpu_amdkfd.h" 41 #include "amdgpu_gem.h" 42 #include "amdgpu_display.h" 43 #include "amdgpu_ras.h" 44 45 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 46 { 47 struct amdgpu_gpu_instance *gpu_instance; 48 int i; 49 50 mutex_lock(&mgpu_info.mutex); 51 52 for (i = 0; i < mgpu_info.num_gpu; i++) { 53 gpu_instance = &(mgpu_info.gpu_ins[i]); 54 if (gpu_instance->adev == adev) { 55 mgpu_info.gpu_ins[i] = 56 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 57 mgpu_info.num_gpu--; 58 if (adev->flags & AMD_IS_APU) 59 mgpu_info.num_apu--; 60 else 61 mgpu_info.num_dgpu--; 62 break; 63 } 64 } 65 66 mutex_unlock(&mgpu_info.mutex); 67 } 68 69 /** 70 * amdgpu_driver_unload_kms - Main unload function for KMS. 71 * 72 * @dev: drm dev pointer 73 * 74 * This is the main unload function for KMS (all asics). 75 * Returns 0 on success. 76 */ 77 void amdgpu_driver_unload_kms(struct drm_device *dev) 78 { 79 struct amdgpu_device *adev = drm_to_adev(dev); 80 81 if (adev == NULL) 82 return; 83 84 amdgpu_unregister_gpu_instance(adev); 85 86 if (adev->rmmio == NULL) 87 return; 88 89 if (adev->runpm) { 90 pm_runtime_get_sync(dev->dev); 91 pm_runtime_forbid(dev->dev); 92 } 93 94 amdgpu_acpi_fini(adev); 95 amdgpu_device_fini(adev); 96 } 97 98 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 99 { 100 struct amdgpu_gpu_instance *gpu_instance; 101 102 mutex_lock(&mgpu_info.mutex); 103 104 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 105 DRM_ERROR("Cannot register more gpu instance\n"); 106 mutex_unlock(&mgpu_info.mutex); 107 return; 108 } 109 110 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 111 gpu_instance->adev = adev; 112 gpu_instance->mgpu_fan_enabled = 0; 113 114 mgpu_info.num_gpu++; 115 if (adev->flags & AMD_IS_APU) 116 mgpu_info.num_apu++; 117 else 118 mgpu_info.num_dgpu++; 119 120 mutex_unlock(&mgpu_info.mutex); 121 } 122 123 /** 124 * amdgpu_driver_load_kms - Main load function for KMS. 125 * 126 * @adev: pointer to struct amdgpu_device 127 * @flags: device flags 128 * 129 * This is the main load function for KMS (all asics). 130 * Returns 0 on success, error on failure. 131 */ 132 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 133 { 134 struct drm_device *dev; 135 struct pci_dev *parent; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 if (amdgpu_has_atpx() && 141 (amdgpu_is_atpx_hybrid() || 142 amdgpu_has_atpx_dgpu_power_cntl()) && 143 ((flags & AMD_IS_APU) == 0) && 144 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) 145 flags |= AMD_IS_PX; 146 147 parent = pci_upstream_bridge(adev->pdev); 148 adev->has_pr3 = parent ? pci_pr3_present(parent) : false; 149 150 /* amdgpu_device_init should report only fatal error 151 * like memory allocation failure or iomapping failure, 152 * or memory manager initialization failure, it must 153 * properly initialize the GPU MC controller and permit 154 * VRAM allocation 155 */ 156 r = amdgpu_device_init(adev, flags); 157 if (r) { 158 dev_err(dev->dev, "Fatal error during GPU init\n"); 159 goto out; 160 } 161 162 if (amdgpu_device_supports_atpx(dev) && 163 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 164 adev->runpm = true; 165 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 166 } else if (amdgpu_device_supports_boco(dev) && 167 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 168 adev->runpm = true; 169 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 170 } else if (amdgpu_device_supports_baco(dev) && 171 (amdgpu_runtime_pm != 0)) { 172 switch (adev->asic_type) { 173 case CHIP_VEGA20: 174 case CHIP_ARCTURUS: 175 /* enable runpm if runpm=1 */ 176 if (amdgpu_runtime_pm > 0) 177 adev->runpm = true; 178 break; 179 case CHIP_VEGA10: 180 /* turn runpm on if noretry=0 */ 181 if (!adev->gmc.noretry) 182 adev->runpm = true; 183 break; 184 default: 185 /* enable runpm on CI+ */ 186 adev->runpm = true; 187 break; 188 } 189 if (adev->runpm) 190 dev_info(adev->dev, "Using BACO for runtime pm\n"); 191 } 192 193 /* Call ACPI methods: require modeset init 194 * but failure is not fatal 195 */ 196 197 acpi_status = amdgpu_acpi_init(adev); 198 if (acpi_status) 199 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 200 201 if (adev->runpm) { 202 /* only need to skip on ATPX */ 203 if (amdgpu_device_supports_atpx(dev) && 204 !amdgpu_is_atpx_hybrid()) 205 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 206 pm_runtime_use_autosuspend(dev->dev); 207 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 208 pm_runtime_allow(dev->dev); 209 pm_runtime_mark_last_busy(dev->dev); 210 pm_runtime_put_autosuspend(dev->dev); 211 } 212 213 out: 214 if (r) { 215 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 216 if (adev->rmmio && adev->runpm) 217 pm_runtime_put_noidle(dev->dev); 218 amdgpu_driver_unload_kms(dev); 219 } 220 221 return r; 222 } 223 224 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 225 struct drm_amdgpu_query_fw *query_fw, 226 struct amdgpu_device *adev) 227 { 228 switch (query_fw->fw_type) { 229 case AMDGPU_INFO_FW_VCE: 230 fw_info->ver = adev->vce.fw_version; 231 fw_info->feature = adev->vce.fb_version; 232 break; 233 case AMDGPU_INFO_FW_UVD: 234 fw_info->ver = adev->uvd.fw_version; 235 fw_info->feature = 0; 236 break; 237 case AMDGPU_INFO_FW_VCN: 238 fw_info->ver = adev->vcn.fw_version; 239 fw_info->feature = 0; 240 break; 241 case AMDGPU_INFO_FW_GMC: 242 fw_info->ver = adev->gmc.fw_version; 243 fw_info->feature = 0; 244 break; 245 case AMDGPU_INFO_FW_GFX_ME: 246 fw_info->ver = adev->gfx.me_fw_version; 247 fw_info->feature = adev->gfx.me_feature_version; 248 break; 249 case AMDGPU_INFO_FW_GFX_PFP: 250 fw_info->ver = adev->gfx.pfp_fw_version; 251 fw_info->feature = adev->gfx.pfp_feature_version; 252 break; 253 case AMDGPU_INFO_FW_GFX_CE: 254 fw_info->ver = adev->gfx.ce_fw_version; 255 fw_info->feature = adev->gfx.ce_feature_version; 256 break; 257 case AMDGPU_INFO_FW_GFX_RLC: 258 fw_info->ver = adev->gfx.rlc_fw_version; 259 fw_info->feature = adev->gfx.rlc_feature_version; 260 break; 261 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 262 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 263 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 264 break; 265 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 266 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 267 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 268 break; 269 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 270 fw_info->ver = adev->gfx.rlc_srls_fw_version; 271 fw_info->feature = adev->gfx.rlc_srls_feature_version; 272 break; 273 case AMDGPU_INFO_FW_GFX_MEC: 274 if (query_fw->index == 0) { 275 fw_info->ver = adev->gfx.mec_fw_version; 276 fw_info->feature = adev->gfx.mec_feature_version; 277 } else if (query_fw->index == 1) { 278 fw_info->ver = adev->gfx.mec2_fw_version; 279 fw_info->feature = adev->gfx.mec2_feature_version; 280 } else 281 return -EINVAL; 282 break; 283 case AMDGPU_INFO_FW_SMC: 284 fw_info->ver = adev->pm.fw_version; 285 fw_info->feature = 0; 286 break; 287 case AMDGPU_INFO_FW_TA: 288 switch (query_fw->index) { 289 case TA_FW_TYPE_PSP_XGMI: 290 fw_info->ver = adev->psp.ta_fw_version; 291 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 292 break; 293 case TA_FW_TYPE_PSP_RAS: 294 fw_info->ver = adev->psp.ta_fw_version; 295 fw_info->feature = adev->psp.ta_ras_ucode_version; 296 break; 297 case TA_FW_TYPE_PSP_HDCP: 298 fw_info->ver = adev->psp.ta_fw_version; 299 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 300 break; 301 case TA_FW_TYPE_PSP_DTM: 302 fw_info->ver = adev->psp.ta_fw_version; 303 fw_info->feature = adev->psp.ta_dtm_ucode_version; 304 break; 305 case TA_FW_TYPE_PSP_RAP: 306 fw_info->ver = adev->psp.ta_fw_version; 307 fw_info->feature = adev->psp.ta_rap_ucode_version; 308 break; 309 case TA_FW_TYPE_PSP_SECUREDISPLAY: 310 fw_info->ver = adev->psp.ta_fw_version; 311 fw_info->feature = adev->psp.ta_securedisplay_ucode_version; 312 break; 313 default: 314 return -EINVAL; 315 } 316 break; 317 case AMDGPU_INFO_FW_SDMA: 318 if (query_fw->index >= adev->sdma.num_instances) 319 return -EINVAL; 320 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 321 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 322 break; 323 case AMDGPU_INFO_FW_SOS: 324 fw_info->ver = adev->psp.sos_fw_version; 325 fw_info->feature = adev->psp.sos_feature_version; 326 break; 327 case AMDGPU_INFO_FW_ASD: 328 fw_info->ver = adev->psp.asd_fw_version; 329 fw_info->feature = adev->psp.asd_feature_version; 330 break; 331 case AMDGPU_INFO_FW_DMCU: 332 fw_info->ver = adev->dm.dmcu_fw_version; 333 fw_info->feature = 0; 334 break; 335 case AMDGPU_INFO_FW_DMCUB: 336 fw_info->ver = adev->dm.dmcub_fw_version; 337 fw_info->feature = 0; 338 break; 339 case AMDGPU_INFO_FW_TOC: 340 fw_info->ver = adev->psp.toc_fw_version; 341 fw_info->feature = adev->psp.toc_feature_version; 342 break; 343 default: 344 return -EINVAL; 345 } 346 return 0; 347 } 348 349 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 350 struct drm_amdgpu_info *info, 351 struct drm_amdgpu_info_hw_ip *result) 352 { 353 uint32_t ib_start_alignment = 0; 354 uint32_t ib_size_alignment = 0; 355 enum amd_ip_block_type type; 356 unsigned int num_rings = 0; 357 unsigned int i, j; 358 359 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 360 return -EINVAL; 361 362 switch (info->query_hw_ip.type) { 363 case AMDGPU_HW_IP_GFX: 364 type = AMD_IP_BLOCK_TYPE_GFX; 365 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 366 if (adev->gfx.gfx_ring[i].sched.ready) 367 ++num_rings; 368 ib_start_alignment = 32; 369 ib_size_alignment = 32; 370 break; 371 case AMDGPU_HW_IP_COMPUTE: 372 type = AMD_IP_BLOCK_TYPE_GFX; 373 for (i = 0; i < adev->gfx.num_compute_rings; i++) 374 if (adev->gfx.compute_ring[i].sched.ready) 375 ++num_rings; 376 ib_start_alignment = 32; 377 ib_size_alignment = 32; 378 break; 379 case AMDGPU_HW_IP_DMA: 380 type = AMD_IP_BLOCK_TYPE_SDMA; 381 for (i = 0; i < adev->sdma.num_instances; i++) 382 if (adev->sdma.instance[i].ring.sched.ready) 383 ++num_rings; 384 ib_start_alignment = 256; 385 ib_size_alignment = 4; 386 break; 387 case AMDGPU_HW_IP_UVD: 388 type = AMD_IP_BLOCK_TYPE_UVD; 389 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 390 if (adev->uvd.harvest_config & (1 << i)) 391 continue; 392 393 if (adev->uvd.inst[i].ring.sched.ready) 394 ++num_rings; 395 } 396 ib_start_alignment = 64; 397 ib_size_alignment = 64; 398 break; 399 case AMDGPU_HW_IP_VCE: 400 type = AMD_IP_BLOCK_TYPE_VCE; 401 for (i = 0; i < adev->vce.num_rings; i++) 402 if (adev->vce.ring[i].sched.ready) 403 ++num_rings; 404 ib_start_alignment = 4; 405 ib_size_alignment = 1; 406 break; 407 case AMDGPU_HW_IP_UVD_ENC: 408 type = AMD_IP_BLOCK_TYPE_UVD; 409 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 410 if (adev->uvd.harvest_config & (1 << i)) 411 continue; 412 413 for (j = 0; j < adev->uvd.num_enc_rings; j++) 414 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 415 ++num_rings; 416 } 417 ib_start_alignment = 64; 418 ib_size_alignment = 64; 419 break; 420 case AMDGPU_HW_IP_VCN_DEC: 421 type = AMD_IP_BLOCK_TYPE_VCN; 422 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 423 if (adev->uvd.harvest_config & (1 << i)) 424 continue; 425 426 if (adev->vcn.inst[i].ring_dec.sched.ready) 427 ++num_rings; 428 } 429 ib_start_alignment = 16; 430 ib_size_alignment = 16; 431 break; 432 case AMDGPU_HW_IP_VCN_ENC: 433 type = AMD_IP_BLOCK_TYPE_VCN; 434 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 435 if (adev->uvd.harvest_config & (1 << i)) 436 continue; 437 438 for (j = 0; j < adev->vcn.num_enc_rings; j++) 439 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 440 ++num_rings; 441 } 442 ib_start_alignment = 64; 443 ib_size_alignment = 1; 444 break; 445 case AMDGPU_HW_IP_VCN_JPEG: 446 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 447 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 448 449 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 450 if (adev->jpeg.harvest_config & (1 << i)) 451 continue; 452 453 if (adev->jpeg.inst[i].ring_dec.sched.ready) 454 ++num_rings; 455 } 456 ib_start_alignment = 16; 457 ib_size_alignment = 16; 458 break; 459 default: 460 return -EINVAL; 461 } 462 463 for (i = 0; i < adev->num_ip_blocks; i++) 464 if (adev->ip_blocks[i].version->type == type && 465 adev->ip_blocks[i].status.valid) 466 break; 467 468 if (i == adev->num_ip_blocks) 469 return 0; 470 471 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 472 num_rings); 473 474 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 475 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 476 result->capabilities_flags = 0; 477 result->available_rings = (1 << num_rings) - 1; 478 result->ib_start_alignment = ib_start_alignment; 479 result->ib_size_alignment = ib_size_alignment; 480 return 0; 481 } 482 483 /* 484 * Userspace get information ioctl 485 */ 486 /** 487 * amdgpu_info_ioctl - answer a device specific request. 488 * 489 * @dev: drm device pointer 490 * @data: request object 491 * @filp: drm filp 492 * 493 * This function is used to pass device specific parameters to the userspace 494 * drivers. Examples include: pci device id, pipeline parms, tiling params, 495 * etc. (all asics). 496 * Returns 0 on success, -EINVAL on failure. 497 */ 498 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 499 { 500 struct amdgpu_device *adev = drm_to_adev(dev); 501 struct drm_amdgpu_info *info = data; 502 struct amdgpu_mode_info *minfo = &adev->mode_info; 503 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 504 uint32_t size = info->return_size; 505 struct drm_crtc *crtc; 506 uint32_t ui32 = 0; 507 uint64_t ui64 = 0; 508 int i, found; 509 int ui32_size = sizeof(ui32); 510 511 if (!info->return_size || !info->return_pointer) 512 return -EINVAL; 513 514 switch (info->query) { 515 case AMDGPU_INFO_ACCEL_WORKING: 516 ui32 = adev->accel_working; 517 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 518 case AMDGPU_INFO_CRTC_FROM_ID: 519 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 520 crtc = (struct drm_crtc *)minfo->crtcs[i]; 521 if (crtc && crtc->base.id == info->mode_crtc.id) { 522 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 523 ui32 = amdgpu_crtc->crtc_id; 524 found = 1; 525 break; 526 } 527 } 528 if (!found) { 529 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 530 return -EINVAL; 531 } 532 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 533 case AMDGPU_INFO_HW_IP_INFO: { 534 struct drm_amdgpu_info_hw_ip ip = {}; 535 int ret; 536 537 ret = amdgpu_hw_ip_info(adev, info, &ip); 538 if (ret) 539 return ret; 540 541 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 542 return ret ? -EFAULT : 0; 543 } 544 case AMDGPU_INFO_HW_IP_COUNT: { 545 enum amd_ip_block_type type; 546 uint32_t count = 0; 547 548 switch (info->query_hw_ip.type) { 549 case AMDGPU_HW_IP_GFX: 550 type = AMD_IP_BLOCK_TYPE_GFX; 551 break; 552 case AMDGPU_HW_IP_COMPUTE: 553 type = AMD_IP_BLOCK_TYPE_GFX; 554 break; 555 case AMDGPU_HW_IP_DMA: 556 type = AMD_IP_BLOCK_TYPE_SDMA; 557 break; 558 case AMDGPU_HW_IP_UVD: 559 type = AMD_IP_BLOCK_TYPE_UVD; 560 break; 561 case AMDGPU_HW_IP_VCE: 562 type = AMD_IP_BLOCK_TYPE_VCE; 563 break; 564 case AMDGPU_HW_IP_UVD_ENC: 565 type = AMD_IP_BLOCK_TYPE_UVD; 566 break; 567 case AMDGPU_HW_IP_VCN_DEC: 568 case AMDGPU_HW_IP_VCN_ENC: 569 type = AMD_IP_BLOCK_TYPE_VCN; 570 break; 571 case AMDGPU_HW_IP_VCN_JPEG: 572 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 573 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 574 break; 575 default: 576 return -EINVAL; 577 } 578 579 for (i = 0; i < adev->num_ip_blocks; i++) 580 if (adev->ip_blocks[i].version->type == type && 581 adev->ip_blocks[i].status.valid && 582 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 583 count++; 584 585 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 586 } 587 case AMDGPU_INFO_TIMESTAMP: 588 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 589 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 590 case AMDGPU_INFO_FW_VERSION: { 591 struct drm_amdgpu_info_firmware fw_info; 592 int ret; 593 594 /* We only support one instance of each IP block right now. */ 595 if (info->query_fw.ip_instance != 0) 596 return -EINVAL; 597 598 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 599 if (ret) 600 return ret; 601 602 return copy_to_user(out, &fw_info, 603 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 604 } 605 case AMDGPU_INFO_NUM_BYTES_MOVED: 606 ui64 = atomic64_read(&adev->num_bytes_moved); 607 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 608 case AMDGPU_INFO_NUM_EVICTIONS: 609 ui64 = atomic64_read(&adev->num_evictions); 610 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 611 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 612 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 613 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 614 case AMDGPU_INFO_VRAM_USAGE: 615 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 616 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 617 case AMDGPU_INFO_VIS_VRAM_USAGE: 618 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 619 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 620 case AMDGPU_INFO_GTT_USAGE: 621 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 622 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 623 case AMDGPU_INFO_GDS_CONFIG: { 624 struct drm_amdgpu_info_gds gds_info; 625 626 memset(&gds_info, 0, sizeof(gds_info)); 627 gds_info.compute_partition_size = adev->gds.gds_size; 628 gds_info.gds_total_size = adev->gds.gds_size; 629 gds_info.gws_per_compute_partition = adev->gds.gws_size; 630 gds_info.oa_per_compute_partition = adev->gds.oa_size; 631 return copy_to_user(out, &gds_info, 632 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 633 } 634 case AMDGPU_INFO_VRAM_GTT: { 635 struct drm_amdgpu_info_vram_gtt vram_gtt; 636 637 vram_gtt.vram_size = adev->gmc.real_vram_size - 638 atomic64_read(&adev->vram_pin_size) - 639 AMDGPU_VM_RESERVED_VRAM; 640 vram_gtt.vram_cpu_accessible_size = 641 min(adev->gmc.visible_vram_size - 642 atomic64_read(&adev->visible_pin_size), 643 vram_gtt.vram_size); 644 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 645 vram_gtt.gtt_size *= PAGE_SIZE; 646 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 647 return copy_to_user(out, &vram_gtt, 648 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 649 } 650 case AMDGPU_INFO_MEMORY: { 651 struct drm_amdgpu_memory_info mem; 652 struct ttm_resource_manager *vram_man = 653 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 654 struct ttm_resource_manager *gtt_man = 655 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 656 memset(&mem, 0, sizeof(mem)); 657 mem.vram.total_heap_size = adev->gmc.real_vram_size; 658 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 659 atomic64_read(&adev->vram_pin_size) - 660 AMDGPU_VM_RESERVED_VRAM; 661 mem.vram.heap_usage = 662 amdgpu_vram_mgr_usage(vram_man); 663 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 664 665 mem.cpu_accessible_vram.total_heap_size = 666 adev->gmc.visible_vram_size; 667 mem.cpu_accessible_vram.usable_heap_size = 668 min(adev->gmc.visible_vram_size - 669 atomic64_read(&adev->visible_pin_size), 670 mem.vram.usable_heap_size); 671 mem.cpu_accessible_vram.heap_usage = 672 amdgpu_vram_mgr_vis_usage(vram_man); 673 mem.cpu_accessible_vram.max_allocation = 674 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 675 676 mem.gtt.total_heap_size = gtt_man->size; 677 mem.gtt.total_heap_size *= PAGE_SIZE; 678 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 679 atomic64_read(&adev->gart_pin_size); 680 mem.gtt.heap_usage = 681 amdgpu_gtt_mgr_usage(gtt_man); 682 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 683 684 return copy_to_user(out, &mem, 685 min((size_t)size, sizeof(mem))) 686 ? -EFAULT : 0; 687 } 688 case AMDGPU_INFO_READ_MMR_REG: { 689 unsigned n, alloc_size; 690 uint32_t *regs; 691 unsigned se_num = (info->read_mmr_reg.instance >> 692 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 693 AMDGPU_INFO_MMR_SE_INDEX_MASK; 694 unsigned sh_num = (info->read_mmr_reg.instance >> 695 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 696 AMDGPU_INFO_MMR_SH_INDEX_MASK; 697 698 /* set full masks if the userspace set all bits 699 * in the bitfields */ 700 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 701 se_num = 0xffffffff; 702 else if (se_num >= AMDGPU_GFX_MAX_SE) 703 return -EINVAL; 704 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 705 sh_num = 0xffffffff; 706 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 707 return -EINVAL; 708 709 if (info->read_mmr_reg.count > 128) 710 return -EINVAL; 711 712 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 713 if (!regs) 714 return -ENOMEM; 715 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 716 717 amdgpu_gfx_off_ctrl(adev, false); 718 for (i = 0; i < info->read_mmr_reg.count; i++) { 719 if (amdgpu_asic_read_register(adev, se_num, sh_num, 720 info->read_mmr_reg.dword_offset + i, 721 ®s[i])) { 722 DRM_DEBUG_KMS("unallowed offset %#x\n", 723 info->read_mmr_reg.dword_offset + i); 724 kfree(regs); 725 amdgpu_gfx_off_ctrl(adev, true); 726 return -EFAULT; 727 } 728 } 729 amdgpu_gfx_off_ctrl(adev, true); 730 n = copy_to_user(out, regs, min(size, alloc_size)); 731 kfree(regs); 732 return n ? -EFAULT : 0; 733 } 734 case AMDGPU_INFO_DEV_INFO: { 735 struct drm_amdgpu_info_device *dev_info; 736 uint64_t vm_size; 737 int ret; 738 739 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 740 if (!dev_info) 741 return -ENOMEM; 742 743 dev_info->device_id = adev->pdev->device; 744 dev_info->chip_rev = adev->rev_id; 745 dev_info->external_rev = adev->external_rev_id; 746 dev_info->pci_rev = adev->pdev->revision; 747 dev_info->family = adev->family; 748 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 749 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 750 /* return all clocks in KHz */ 751 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 752 if (adev->pm.dpm_enabled) { 753 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 754 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 755 } else { 756 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 757 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 758 } 759 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 760 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 761 adev->gfx.config.max_shader_engines; 762 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 763 dev_info->_pad = 0; 764 dev_info->ids_flags = 0; 765 if (adev->flags & AMD_IS_APU) 766 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 767 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 768 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 769 if (amdgpu_is_tmz(adev)) 770 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 771 772 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 773 vm_size -= AMDGPU_VA_RESERVED_SIZE; 774 775 /* Older VCE FW versions are buggy and can handle only 40bits */ 776 if (adev->vce.fw_version && 777 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 778 vm_size = min(vm_size, 1ULL << 40); 779 780 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 781 dev_info->virtual_address_max = 782 min(vm_size, AMDGPU_GMC_HOLE_START); 783 784 if (vm_size > AMDGPU_GMC_HOLE_START) { 785 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 786 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 787 } 788 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 789 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 790 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE; 791 dev_info->cu_active_number = adev->gfx.cu_info.number; 792 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 793 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 794 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 795 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 796 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 797 sizeof(adev->gfx.cu_info.bitmap)); 798 dev_info->vram_type = adev->gmc.vram_type; 799 dev_info->vram_bit_width = adev->gmc.vram_width; 800 dev_info->vce_harvest_config = adev->vce.harvest_config; 801 dev_info->gc_double_offchip_lds_buf = 802 adev->gfx.config.double_offchip_lds_buf; 803 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 804 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 805 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 806 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 807 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 808 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 809 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 810 811 if (adev->family >= AMDGPU_FAMILY_NV) 812 dev_info->pa_sc_tile_steering_override = 813 adev->gfx.config.pa_sc_tile_steering_override; 814 815 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 816 817 ret = copy_to_user(out, dev_info, 818 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 819 kfree(dev_info); 820 return ret; 821 } 822 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 823 unsigned i; 824 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 825 struct amd_vce_state *vce_state; 826 827 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 828 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 829 if (vce_state) { 830 vce_clk_table.entries[i].sclk = vce_state->sclk; 831 vce_clk_table.entries[i].mclk = vce_state->mclk; 832 vce_clk_table.entries[i].eclk = vce_state->evclk; 833 vce_clk_table.num_valid_entries++; 834 } 835 } 836 837 return copy_to_user(out, &vce_clk_table, 838 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 839 } 840 case AMDGPU_INFO_VBIOS: { 841 uint32_t bios_size = adev->bios_size; 842 843 switch (info->vbios_info.type) { 844 case AMDGPU_INFO_VBIOS_SIZE: 845 return copy_to_user(out, &bios_size, 846 min((size_t)size, sizeof(bios_size))) 847 ? -EFAULT : 0; 848 case AMDGPU_INFO_VBIOS_IMAGE: { 849 uint8_t *bios; 850 uint32_t bios_offset = info->vbios_info.offset; 851 852 if (bios_offset >= bios_size) 853 return -EINVAL; 854 855 bios = adev->bios + bios_offset; 856 return copy_to_user(out, bios, 857 min((size_t)size, (size_t)(bios_size - bios_offset))) 858 ? -EFAULT : 0; 859 } 860 default: 861 DRM_DEBUG_KMS("Invalid request %d\n", 862 info->vbios_info.type); 863 return -EINVAL; 864 } 865 } 866 case AMDGPU_INFO_NUM_HANDLES: { 867 struct drm_amdgpu_info_num_handles handle; 868 869 switch (info->query_hw_ip.type) { 870 case AMDGPU_HW_IP_UVD: 871 /* Starting Polaris, we support unlimited UVD handles */ 872 if (adev->asic_type < CHIP_POLARIS10) { 873 handle.uvd_max_handles = adev->uvd.max_handles; 874 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 875 876 return copy_to_user(out, &handle, 877 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 878 } else { 879 return -ENODATA; 880 } 881 882 break; 883 default: 884 return -EINVAL; 885 } 886 } 887 case AMDGPU_INFO_SENSOR: { 888 if (!adev->pm.dpm_enabled) 889 return -ENOENT; 890 891 switch (info->sensor_info.type) { 892 case AMDGPU_INFO_SENSOR_GFX_SCLK: 893 /* get sclk in Mhz */ 894 if (amdgpu_dpm_read_sensor(adev, 895 AMDGPU_PP_SENSOR_GFX_SCLK, 896 (void *)&ui32, &ui32_size)) { 897 return -EINVAL; 898 } 899 ui32 /= 100; 900 break; 901 case AMDGPU_INFO_SENSOR_GFX_MCLK: 902 /* get mclk in Mhz */ 903 if (amdgpu_dpm_read_sensor(adev, 904 AMDGPU_PP_SENSOR_GFX_MCLK, 905 (void *)&ui32, &ui32_size)) { 906 return -EINVAL; 907 } 908 ui32 /= 100; 909 break; 910 case AMDGPU_INFO_SENSOR_GPU_TEMP: 911 /* get temperature in millidegrees C */ 912 if (amdgpu_dpm_read_sensor(adev, 913 AMDGPU_PP_SENSOR_GPU_TEMP, 914 (void *)&ui32, &ui32_size)) { 915 return -EINVAL; 916 } 917 break; 918 case AMDGPU_INFO_SENSOR_GPU_LOAD: 919 /* get GPU load */ 920 if (amdgpu_dpm_read_sensor(adev, 921 AMDGPU_PP_SENSOR_GPU_LOAD, 922 (void *)&ui32, &ui32_size)) { 923 return -EINVAL; 924 } 925 break; 926 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 927 /* get average GPU power */ 928 if (amdgpu_dpm_read_sensor(adev, 929 AMDGPU_PP_SENSOR_GPU_POWER, 930 (void *)&ui32, &ui32_size)) { 931 return -EINVAL; 932 } 933 ui32 >>= 8; 934 break; 935 case AMDGPU_INFO_SENSOR_VDDNB: 936 /* get VDDNB in millivolts */ 937 if (amdgpu_dpm_read_sensor(adev, 938 AMDGPU_PP_SENSOR_VDDNB, 939 (void *)&ui32, &ui32_size)) { 940 return -EINVAL; 941 } 942 break; 943 case AMDGPU_INFO_SENSOR_VDDGFX: 944 /* get VDDGFX in millivolts */ 945 if (amdgpu_dpm_read_sensor(adev, 946 AMDGPU_PP_SENSOR_VDDGFX, 947 (void *)&ui32, &ui32_size)) { 948 return -EINVAL; 949 } 950 break; 951 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 952 /* get stable pstate sclk in Mhz */ 953 if (amdgpu_dpm_read_sensor(adev, 954 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 955 (void *)&ui32, &ui32_size)) { 956 return -EINVAL; 957 } 958 ui32 /= 100; 959 break; 960 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 961 /* get stable pstate mclk in Mhz */ 962 if (amdgpu_dpm_read_sensor(adev, 963 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 964 (void *)&ui32, &ui32_size)) { 965 return -EINVAL; 966 } 967 ui32 /= 100; 968 break; 969 default: 970 DRM_DEBUG_KMS("Invalid request %d\n", 971 info->sensor_info.type); 972 return -EINVAL; 973 } 974 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 975 } 976 case AMDGPU_INFO_VRAM_LOST_COUNTER: 977 ui32 = atomic_read(&adev->vram_lost_counter); 978 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 979 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 980 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 981 uint64_t ras_mask; 982 983 if (!ras) 984 return -EINVAL; 985 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 986 987 return copy_to_user(out, &ras_mask, 988 min_t(u64, size, sizeof(ras_mask))) ? 989 -EFAULT : 0; 990 } 991 case AMDGPU_INFO_VIDEO_CAPS: { 992 const struct amdgpu_video_codecs *codecs; 993 struct drm_amdgpu_info_video_caps *caps; 994 int r; 995 996 switch (info->video_cap.type) { 997 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 998 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 999 if (r) 1000 return -EINVAL; 1001 break; 1002 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1003 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1004 if (r) 1005 return -EINVAL; 1006 break; 1007 default: 1008 DRM_DEBUG_KMS("Invalid request %d\n", 1009 info->video_cap.type); 1010 return -EINVAL; 1011 } 1012 1013 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1014 if (!caps) 1015 return -ENOMEM; 1016 1017 for (i = 0; i < codecs->codec_count; i++) { 1018 int idx = codecs->codec_array[i].codec_type; 1019 1020 switch (idx) { 1021 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1022 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1023 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1024 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1025 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1026 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1027 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1028 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1029 caps->codec_info[idx].valid = 1; 1030 caps->codec_info[idx].max_width = 1031 codecs->codec_array[i].max_width; 1032 caps->codec_info[idx].max_height = 1033 codecs->codec_array[i].max_height; 1034 caps->codec_info[idx].max_pixels_per_frame = 1035 codecs->codec_array[i].max_pixels_per_frame; 1036 caps->codec_info[idx].max_level = 1037 codecs->codec_array[i].max_level; 1038 break; 1039 default: 1040 break; 1041 } 1042 } 1043 r = copy_to_user(out, caps, 1044 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1045 kfree(caps); 1046 return r; 1047 } 1048 default: 1049 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1050 return -EINVAL; 1051 } 1052 return 0; 1053 } 1054 1055 1056 /* 1057 * Outdated mess for old drm with Xorg being in charge (void function now). 1058 */ 1059 /** 1060 * amdgpu_driver_lastclose_kms - drm callback for last close 1061 * 1062 * @dev: drm dev pointer 1063 * 1064 * Switch vga_switcheroo state after last close (all asics). 1065 */ 1066 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1067 { 1068 drm_fb_helper_lastclose(dev); 1069 vga_switcheroo_process_delayed_switch(); 1070 } 1071 1072 /** 1073 * amdgpu_driver_open_kms - drm callback for open 1074 * 1075 * @dev: drm dev pointer 1076 * @file_priv: drm file 1077 * 1078 * On device open, init vm on cayman+ (all asics). 1079 * Returns 0 on success, error on failure. 1080 */ 1081 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1082 { 1083 struct amdgpu_device *adev = drm_to_adev(dev); 1084 struct amdgpu_fpriv *fpriv; 1085 int r, pasid; 1086 1087 /* Ensure IB tests are run on ring */ 1088 flush_delayed_work(&adev->delayed_init_work); 1089 1090 1091 if (amdgpu_ras_intr_triggered()) { 1092 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1093 return -EHWPOISON; 1094 } 1095 1096 file_priv->driver_priv = NULL; 1097 1098 r = pm_runtime_get_sync(dev->dev); 1099 if (r < 0) 1100 goto pm_put; 1101 1102 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1103 if (unlikely(!fpriv)) { 1104 r = -ENOMEM; 1105 goto out_suspend; 1106 } 1107 1108 pasid = amdgpu_pasid_alloc(16); 1109 if (pasid < 0) { 1110 dev_warn(adev->dev, "No more PASIDs available!"); 1111 pasid = 0; 1112 } 1113 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1114 if (r) 1115 goto error_pasid; 1116 1117 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1118 if (!fpriv->prt_va) { 1119 r = -ENOMEM; 1120 goto error_vm; 1121 } 1122 1123 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1124 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1125 1126 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1127 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1128 if (r) 1129 goto error_vm; 1130 } 1131 1132 mutex_init(&fpriv->bo_list_lock); 1133 idr_init(&fpriv->bo_list_handles); 1134 1135 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1136 1137 file_priv->driver_priv = fpriv; 1138 goto out_suspend; 1139 1140 error_vm: 1141 amdgpu_vm_fini(adev, &fpriv->vm); 1142 1143 error_pasid: 1144 if (pasid) 1145 amdgpu_pasid_free(pasid); 1146 1147 kfree(fpriv); 1148 1149 out_suspend: 1150 pm_runtime_mark_last_busy(dev->dev); 1151 pm_put: 1152 pm_runtime_put_autosuspend(dev->dev); 1153 1154 return r; 1155 } 1156 1157 /** 1158 * amdgpu_driver_postclose_kms - drm callback for post close 1159 * 1160 * @dev: drm dev pointer 1161 * @file_priv: drm file 1162 * 1163 * On device post close, tear down vm on cayman+ (all asics). 1164 */ 1165 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1166 struct drm_file *file_priv) 1167 { 1168 struct amdgpu_device *adev = drm_to_adev(dev); 1169 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1170 struct amdgpu_bo_list *list; 1171 struct amdgpu_bo *pd; 1172 u32 pasid; 1173 int handle; 1174 1175 if (!fpriv) 1176 return; 1177 1178 pm_runtime_get_sync(dev->dev); 1179 1180 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1181 amdgpu_uvd_free_handles(adev, file_priv); 1182 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1183 amdgpu_vce_free_handles(adev, file_priv); 1184 1185 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1186 1187 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1188 /* TODO: how to handle reserve failure */ 1189 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1190 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1191 fpriv->csa_va = NULL; 1192 amdgpu_bo_unreserve(adev->virt.csa_obj); 1193 } 1194 1195 pasid = fpriv->vm.pasid; 1196 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1197 1198 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1199 amdgpu_vm_fini(adev, &fpriv->vm); 1200 1201 if (pasid) 1202 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1203 amdgpu_bo_unref(&pd); 1204 1205 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1206 amdgpu_bo_list_put(list); 1207 1208 idr_destroy(&fpriv->bo_list_handles); 1209 mutex_destroy(&fpriv->bo_list_lock); 1210 1211 kfree(fpriv); 1212 file_priv->driver_priv = NULL; 1213 1214 pm_runtime_mark_last_busy(dev->dev); 1215 pm_runtime_put_autosuspend(dev->dev); 1216 } 1217 1218 /* 1219 * VBlank related functions. 1220 */ 1221 /** 1222 * amdgpu_get_vblank_counter_kms - get frame count 1223 * 1224 * @crtc: crtc to get the frame count from 1225 * 1226 * Gets the frame count on the requested crtc (all asics). 1227 * Returns frame count on success, -EINVAL on failure. 1228 */ 1229 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1230 { 1231 struct drm_device *dev = crtc->dev; 1232 unsigned int pipe = crtc->index; 1233 struct amdgpu_device *adev = drm_to_adev(dev); 1234 int vpos, hpos, stat; 1235 u32 count; 1236 1237 if (pipe >= adev->mode_info.num_crtc) { 1238 DRM_ERROR("Invalid crtc %u\n", pipe); 1239 return -EINVAL; 1240 } 1241 1242 /* The hw increments its frame counter at start of vsync, not at start 1243 * of vblank, as is required by DRM core vblank counter handling. 1244 * Cook the hw count here to make it appear to the caller as if it 1245 * incremented at start of vblank. We measure distance to start of 1246 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1247 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1248 * result by 1 to give the proper appearance to caller. 1249 */ 1250 if (adev->mode_info.crtcs[pipe]) { 1251 /* Repeat readout if needed to provide stable result if 1252 * we cross start of vsync during the queries. 1253 */ 1254 do { 1255 count = amdgpu_display_vblank_get_counter(adev, pipe); 1256 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1257 * vpos as distance to start of vblank, instead of 1258 * regular vertical scanout pos. 1259 */ 1260 stat = amdgpu_display_get_crtc_scanoutpos( 1261 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1262 &vpos, &hpos, NULL, NULL, 1263 &adev->mode_info.crtcs[pipe]->base.hwmode); 1264 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1265 1266 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1267 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1268 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1269 } else { 1270 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1271 pipe, vpos); 1272 1273 /* Bump counter if we are at >= leading edge of vblank, 1274 * but before vsync where vpos would turn negative and 1275 * the hw counter really increments. 1276 */ 1277 if (vpos >= 0) 1278 count++; 1279 } 1280 } else { 1281 /* Fallback to use value as is. */ 1282 count = amdgpu_display_vblank_get_counter(adev, pipe); 1283 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1284 } 1285 1286 return count; 1287 } 1288 1289 /** 1290 * amdgpu_enable_vblank_kms - enable vblank interrupt 1291 * 1292 * @crtc: crtc to enable vblank interrupt for 1293 * 1294 * Enable the interrupt on the requested crtc (all asics). 1295 * Returns 0 on success, -EINVAL on failure. 1296 */ 1297 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1298 { 1299 struct drm_device *dev = crtc->dev; 1300 unsigned int pipe = crtc->index; 1301 struct amdgpu_device *adev = drm_to_adev(dev); 1302 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1303 1304 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1305 } 1306 1307 /** 1308 * amdgpu_disable_vblank_kms - disable vblank interrupt 1309 * 1310 * @crtc: crtc to disable vblank interrupt for 1311 * 1312 * Disable the interrupt on the requested crtc (all asics). 1313 */ 1314 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1315 { 1316 struct drm_device *dev = crtc->dev; 1317 unsigned int pipe = crtc->index; 1318 struct amdgpu_device *adev = drm_to_adev(dev); 1319 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1320 1321 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1322 } 1323 1324 /* 1325 * Debugfs info 1326 */ 1327 #if defined(CONFIG_DEBUG_FS) 1328 1329 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1332 struct drm_amdgpu_info_firmware fw_info; 1333 struct drm_amdgpu_query_fw query_fw; 1334 struct atom_context *ctx = adev->mode_info.atom_context; 1335 int ret, i; 1336 1337 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1338 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1339 TA_FW_NAME(XGMI), 1340 TA_FW_NAME(RAS), 1341 TA_FW_NAME(HDCP), 1342 TA_FW_NAME(DTM), 1343 TA_FW_NAME(RAP), 1344 TA_FW_NAME(SECUREDISPLAY), 1345 #undef TA_FW_NAME 1346 }; 1347 1348 /* VCE */ 1349 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1350 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1351 if (ret) 1352 return ret; 1353 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1354 fw_info.feature, fw_info.ver); 1355 1356 /* UVD */ 1357 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1358 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1359 if (ret) 1360 return ret; 1361 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1362 fw_info.feature, fw_info.ver); 1363 1364 /* GMC */ 1365 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1366 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1367 if (ret) 1368 return ret; 1369 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1370 fw_info.feature, fw_info.ver); 1371 1372 /* ME */ 1373 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1374 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1375 if (ret) 1376 return ret; 1377 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1378 fw_info.feature, fw_info.ver); 1379 1380 /* PFP */ 1381 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1382 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1383 if (ret) 1384 return ret; 1385 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1386 fw_info.feature, fw_info.ver); 1387 1388 /* CE */ 1389 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1390 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1391 if (ret) 1392 return ret; 1393 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1394 fw_info.feature, fw_info.ver); 1395 1396 /* RLC */ 1397 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1398 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1399 if (ret) 1400 return ret; 1401 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1402 fw_info.feature, fw_info.ver); 1403 1404 /* RLC SAVE RESTORE LIST CNTL */ 1405 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1406 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1407 if (ret) 1408 return ret; 1409 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1410 fw_info.feature, fw_info.ver); 1411 1412 /* RLC SAVE RESTORE LIST GPM MEM */ 1413 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1414 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1415 if (ret) 1416 return ret; 1417 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1418 fw_info.feature, fw_info.ver); 1419 1420 /* RLC SAVE RESTORE LIST SRM MEM */ 1421 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1422 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1423 if (ret) 1424 return ret; 1425 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1426 fw_info.feature, fw_info.ver); 1427 1428 /* MEC */ 1429 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1430 query_fw.index = 0; 1431 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1432 if (ret) 1433 return ret; 1434 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1435 fw_info.feature, fw_info.ver); 1436 1437 /* MEC2 */ 1438 if (adev->gfx.mec2_fw) { 1439 query_fw.index = 1; 1440 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1441 if (ret) 1442 return ret; 1443 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1444 fw_info.feature, fw_info.ver); 1445 } 1446 1447 /* PSP SOS */ 1448 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1449 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1450 if (ret) 1451 return ret; 1452 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1453 fw_info.feature, fw_info.ver); 1454 1455 1456 /* PSP ASD */ 1457 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1458 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1459 if (ret) 1460 return ret; 1461 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1462 fw_info.feature, fw_info.ver); 1463 1464 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1465 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1466 query_fw.index = i; 1467 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1468 if (ret) 1469 continue; 1470 1471 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1472 ta_fw_name[i], fw_info.feature, fw_info.ver); 1473 } 1474 1475 /* SMC */ 1476 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1477 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1478 if (ret) 1479 return ret; 1480 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1481 fw_info.feature, fw_info.ver); 1482 1483 /* SDMA */ 1484 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1485 for (i = 0; i < adev->sdma.num_instances; i++) { 1486 query_fw.index = i; 1487 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1488 if (ret) 1489 return ret; 1490 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1491 i, fw_info.feature, fw_info.ver); 1492 } 1493 1494 /* VCN */ 1495 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1496 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1497 if (ret) 1498 return ret; 1499 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1500 fw_info.feature, fw_info.ver); 1501 1502 /* DMCU */ 1503 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1504 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1505 if (ret) 1506 return ret; 1507 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1508 fw_info.feature, fw_info.ver); 1509 1510 /* DMCUB */ 1511 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1512 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1513 if (ret) 1514 return ret; 1515 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1516 fw_info.feature, fw_info.ver); 1517 1518 /* TOC */ 1519 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1520 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1521 if (ret) 1522 return ret; 1523 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1524 fw_info.feature, fw_info.ver); 1525 1526 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1527 1528 return 0; 1529 } 1530 1531 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1532 1533 #endif 1534 1535 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1536 { 1537 #if defined(CONFIG_DEBUG_FS) 1538 struct drm_minor *minor = adev_to_drm(adev)->primary; 1539 struct dentry *root = minor->debugfs_root; 1540 1541 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1542 adev, &amdgpu_debugfs_firmware_info_fops); 1543 1544 #endif 1545 } 1546