1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 91 DRM_WARN("smart shift update failed\n"); 92 93 amdgpu_acpi_fini(adev); 94 amdgpu_device_fini_hw(adev); 95 } 96 97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 98 { 99 struct amdgpu_gpu_instance *gpu_instance; 100 101 mutex_lock(&mgpu_info.mutex); 102 103 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 104 DRM_ERROR("Cannot register more gpu instance\n"); 105 mutex_unlock(&mgpu_info.mutex); 106 return; 107 } 108 109 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 110 gpu_instance->adev = adev; 111 gpu_instance->mgpu_fan_enabled = 0; 112 113 mgpu_info.num_gpu++; 114 if (adev->flags & AMD_IS_APU) 115 mgpu_info.num_apu++; 116 else 117 mgpu_info.num_dgpu++; 118 119 mutex_unlock(&mgpu_info.mutex); 120 } 121 122 /** 123 * amdgpu_driver_load_kms - Main load function for KMS. 124 * 125 * @adev: pointer to struct amdgpu_device 126 * @flags: device flags 127 * 128 * This is the main load function for KMS (all asics). 129 * Returns 0 on success, error on failure. 130 */ 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 132 { 133 struct drm_device *dev; 134 int r, acpi_status; 135 136 dev = adev_to_drm(adev); 137 138 /* amdgpu_device_init should report only fatal error 139 * like memory allocation failure or iomapping failure, 140 * or memory manager initialization failure, it must 141 * properly initialize the GPU MC controller and permit 142 * VRAM allocation 143 */ 144 r = amdgpu_device_init(adev, flags); 145 if (r) { 146 dev_err(dev->dev, "Fatal error during GPU init\n"); 147 goto out; 148 } 149 150 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 151 if (amdgpu_device_supports_px(dev) && 152 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 153 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 154 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 155 } else if (amdgpu_device_supports_boco(dev) && 156 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 157 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 158 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 159 } else if (amdgpu_device_supports_baco(dev) && 160 (amdgpu_runtime_pm != 0)) { 161 switch (adev->asic_type) { 162 case CHIP_VEGA20: 163 case CHIP_ARCTURUS: 164 /* enable BACO as runpm mode if runpm=1 */ 165 if (amdgpu_runtime_pm > 0) 166 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 167 break; 168 case CHIP_VEGA10: 169 /* enable BACO as runpm mode if noretry=0 */ 170 if (!adev->gmc.noretry) 171 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 172 break; 173 default: 174 /* enable BACO as runpm mode on CI+ */ 175 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 176 break; 177 } 178 179 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 180 dev_info(adev->dev, "Using BACO for runtime pm\n"); 181 } 182 183 /* Call ACPI methods: require modeset init 184 * but failure is not fatal 185 */ 186 187 acpi_status = amdgpu_acpi_init(adev); 188 if (acpi_status) 189 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 190 191 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 192 DRM_WARN("smart shift update failed\n"); 193 194 out: 195 if (r) 196 amdgpu_driver_unload_kms(dev); 197 198 return r; 199 } 200 201 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 202 struct drm_amdgpu_query_fw *query_fw, 203 struct amdgpu_device *adev) 204 { 205 switch (query_fw->fw_type) { 206 case AMDGPU_INFO_FW_VCE: 207 fw_info->ver = adev->vce.fw_version; 208 fw_info->feature = adev->vce.fb_version; 209 break; 210 case AMDGPU_INFO_FW_UVD: 211 fw_info->ver = adev->uvd.fw_version; 212 fw_info->feature = 0; 213 break; 214 case AMDGPU_INFO_FW_VCN: 215 fw_info->ver = adev->vcn.fw_version; 216 fw_info->feature = 0; 217 break; 218 case AMDGPU_INFO_FW_GMC: 219 fw_info->ver = adev->gmc.fw_version; 220 fw_info->feature = 0; 221 break; 222 case AMDGPU_INFO_FW_GFX_ME: 223 fw_info->ver = adev->gfx.me_fw_version; 224 fw_info->feature = adev->gfx.me_feature_version; 225 break; 226 case AMDGPU_INFO_FW_GFX_PFP: 227 fw_info->ver = adev->gfx.pfp_fw_version; 228 fw_info->feature = adev->gfx.pfp_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_CE: 231 fw_info->ver = adev->gfx.ce_fw_version; 232 fw_info->feature = adev->gfx.ce_feature_version; 233 break; 234 case AMDGPU_INFO_FW_GFX_RLC: 235 fw_info->ver = adev->gfx.rlc_fw_version; 236 fw_info->feature = adev->gfx.rlc_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 239 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 240 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 243 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 244 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 247 fw_info->ver = adev->gfx.rlc_srls_fw_version; 248 fw_info->feature = adev->gfx.rlc_srls_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLCP: 251 fw_info->ver = adev->gfx.rlcp_ucode_version; 252 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLCV: 255 fw_info->ver = adev->gfx.rlcv_ucode_version; 256 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_MEC: 259 if (query_fw->index == 0) { 260 fw_info->ver = adev->gfx.mec_fw_version; 261 fw_info->feature = adev->gfx.mec_feature_version; 262 } else if (query_fw->index == 1) { 263 fw_info->ver = adev->gfx.mec2_fw_version; 264 fw_info->feature = adev->gfx.mec2_feature_version; 265 } else 266 return -EINVAL; 267 break; 268 case AMDGPU_INFO_FW_SMC: 269 fw_info->ver = adev->pm.fw_version; 270 fw_info->feature = 0; 271 break; 272 case AMDGPU_INFO_FW_TA: 273 switch (query_fw->index) { 274 case TA_FW_TYPE_PSP_XGMI: 275 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 276 fw_info->feature = adev->psp.xgmi_context.context 277 .bin_desc.feature_version; 278 break; 279 case TA_FW_TYPE_PSP_RAS: 280 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 281 fw_info->feature = adev->psp.ras_context.context 282 .bin_desc.feature_version; 283 break; 284 case TA_FW_TYPE_PSP_HDCP: 285 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 286 fw_info->feature = adev->psp.hdcp_context.context 287 .bin_desc.feature_version; 288 break; 289 case TA_FW_TYPE_PSP_DTM: 290 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 291 fw_info->feature = adev->psp.dtm_context.context 292 .bin_desc.feature_version; 293 break; 294 case TA_FW_TYPE_PSP_RAP: 295 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 296 fw_info->feature = adev->psp.rap_context.context 297 .bin_desc.feature_version; 298 break; 299 case TA_FW_TYPE_PSP_SECUREDISPLAY: 300 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 301 fw_info->feature = 302 adev->psp.securedisplay_context.context.bin_desc 303 .feature_version; 304 break; 305 default: 306 return -EINVAL; 307 } 308 break; 309 case AMDGPU_INFO_FW_SDMA: 310 if (query_fw->index >= adev->sdma.num_instances) 311 return -EINVAL; 312 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 313 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 314 break; 315 case AMDGPU_INFO_FW_SOS: 316 fw_info->ver = adev->psp.sos.fw_version; 317 fw_info->feature = adev->psp.sos.feature_version; 318 break; 319 case AMDGPU_INFO_FW_ASD: 320 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 321 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 322 break; 323 case AMDGPU_INFO_FW_DMCU: 324 fw_info->ver = adev->dm.dmcu_fw_version; 325 fw_info->feature = 0; 326 break; 327 case AMDGPU_INFO_FW_DMCUB: 328 fw_info->ver = adev->dm.dmcub_fw_version; 329 fw_info->feature = 0; 330 break; 331 case AMDGPU_INFO_FW_TOC: 332 fw_info->ver = adev->psp.toc.fw_version; 333 fw_info->feature = adev->psp.toc.feature_version; 334 break; 335 case AMDGPU_INFO_FW_CAP: 336 fw_info->ver = adev->psp.cap_fw_version; 337 fw_info->feature = adev->psp.cap_feature_version; 338 break; 339 case AMDGPU_INFO_FW_MES_KIQ: 340 fw_info->ver = adev->mes.ucode_fw_version[0]; 341 fw_info->feature = 0; 342 break; 343 case AMDGPU_INFO_FW_MES: 344 fw_info->ver = adev->mes.ucode_fw_version[1]; 345 fw_info->feature = 0; 346 break; 347 case AMDGPU_INFO_FW_IMU: 348 fw_info->ver = adev->gfx.imu_fw_version; 349 fw_info->feature = 0; 350 break; 351 default: 352 return -EINVAL; 353 } 354 return 0; 355 } 356 357 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 358 struct drm_amdgpu_info *info, 359 struct drm_amdgpu_info_hw_ip *result) 360 { 361 uint32_t ib_start_alignment = 0; 362 uint32_t ib_size_alignment = 0; 363 enum amd_ip_block_type type; 364 unsigned int num_rings = 0; 365 unsigned int i, j; 366 367 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 368 return -EINVAL; 369 370 switch (info->query_hw_ip.type) { 371 case AMDGPU_HW_IP_GFX: 372 type = AMD_IP_BLOCK_TYPE_GFX; 373 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 374 if (adev->gfx.gfx_ring[i].sched.ready) 375 ++num_rings; 376 ib_start_alignment = 32; 377 ib_size_alignment = 32; 378 break; 379 case AMDGPU_HW_IP_COMPUTE: 380 type = AMD_IP_BLOCK_TYPE_GFX; 381 for (i = 0; i < adev->gfx.num_compute_rings; i++) 382 if (adev->gfx.compute_ring[i].sched.ready) 383 ++num_rings; 384 ib_start_alignment = 32; 385 ib_size_alignment = 32; 386 break; 387 case AMDGPU_HW_IP_DMA: 388 type = AMD_IP_BLOCK_TYPE_SDMA; 389 for (i = 0; i < adev->sdma.num_instances; i++) 390 if (adev->sdma.instance[i].ring.sched.ready) 391 ++num_rings; 392 ib_start_alignment = 256; 393 ib_size_alignment = 4; 394 break; 395 case AMDGPU_HW_IP_UVD: 396 type = AMD_IP_BLOCK_TYPE_UVD; 397 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 398 if (adev->uvd.harvest_config & (1 << i)) 399 continue; 400 401 if (adev->uvd.inst[i].ring.sched.ready) 402 ++num_rings; 403 } 404 ib_start_alignment = 64; 405 ib_size_alignment = 64; 406 break; 407 case AMDGPU_HW_IP_VCE: 408 type = AMD_IP_BLOCK_TYPE_VCE; 409 for (i = 0; i < adev->vce.num_rings; i++) 410 if (adev->vce.ring[i].sched.ready) 411 ++num_rings; 412 ib_start_alignment = 4; 413 ib_size_alignment = 1; 414 break; 415 case AMDGPU_HW_IP_UVD_ENC: 416 type = AMD_IP_BLOCK_TYPE_UVD; 417 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 418 if (adev->uvd.harvest_config & (1 << i)) 419 continue; 420 421 for (j = 0; j < adev->uvd.num_enc_rings; j++) 422 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 423 ++num_rings; 424 } 425 ib_start_alignment = 64; 426 ib_size_alignment = 64; 427 break; 428 case AMDGPU_HW_IP_VCN_DEC: 429 type = AMD_IP_BLOCK_TYPE_VCN; 430 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 431 if (adev->uvd.harvest_config & (1 << i)) 432 continue; 433 434 if (adev->vcn.inst[i].ring_dec.sched.ready) 435 ++num_rings; 436 } 437 ib_start_alignment = 16; 438 ib_size_alignment = 16; 439 break; 440 case AMDGPU_HW_IP_VCN_ENC: 441 type = AMD_IP_BLOCK_TYPE_VCN; 442 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 443 if (adev->uvd.harvest_config & (1 << i)) 444 continue; 445 446 for (j = 0; j < adev->vcn.num_enc_rings; j++) 447 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 448 ++num_rings; 449 } 450 ib_start_alignment = 64; 451 ib_size_alignment = 1; 452 break; 453 case AMDGPU_HW_IP_VCN_JPEG: 454 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 455 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 456 457 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 458 if (adev->jpeg.harvest_config & (1 << i)) 459 continue; 460 461 if (adev->jpeg.inst[i].ring_dec.sched.ready) 462 ++num_rings; 463 } 464 ib_start_alignment = 16; 465 ib_size_alignment = 16; 466 break; 467 default: 468 return -EINVAL; 469 } 470 471 for (i = 0; i < adev->num_ip_blocks; i++) 472 if (adev->ip_blocks[i].version->type == type && 473 adev->ip_blocks[i].status.valid) 474 break; 475 476 if (i == adev->num_ip_blocks) 477 return 0; 478 479 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 480 num_rings); 481 482 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 483 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 484 485 if (adev->asic_type >= CHIP_VEGA10) { 486 switch (type) { 487 case AMD_IP_BLOCK_TYPE_GFX: 488 result->ip_discovery_version = adev->ip_versions[GC_HWIP][0]; 489 break; 490 case AMD_IP_BLOCK_TYPE_SDMA: 491 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0]; 492 break; 493 case AMD_IP_BLOCK_TYPE_UVD: 494 case AMD_IP_BLOCK_TYPE_VCN: 495 case AMD_IP_BLOCK_TYPE_JPEG: 496 result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0]; 497 break; 498 case AMD_IP_BLOCK_TYPE_VCE: 499 result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0]; 500 break; 501 default: 502 result->ip_discovery_version = 0; 503 break; 504 } 505 } else { 506 result->ip_discovery_version = 0; 507 } 508 result->capabilities_flags = 0; 509 result->available_rings = (1 << num_rings) - 1; 510 result->ib_start_alignment = ib_start_alignment; 511 result->ib_size_alignment = ib_size_alignment; 512 return 0; 513 } 514 515 /* 516 * Userspace get information ioctl 517 */ 518 /** 519 * amdgpu_info_ioctl - answer a device specific request. 520 * 521 * @dev: drm device pointer 522 * @data: request object 523 * @filp: drm filp 524 * 525 * This function is used to pass device specific parameters to the userspace 526 * drivers. Examples include: pci device id, pipeline parms, tiling params, 527 * etc. (all asics). 528 * Returns 0 on success, -EINVAL on failure. 529 */ 530 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 531 { 532 struct amdgpu_device *adev = drm_to_adev(dev); 533 struct drm_amdgpu_info *info = data; 534 struct amdgpu_mode_info *minfo = &adev->mode_info; 535 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 536 uint32_t size = info->return_size; 537 struct drm_crtc *crtc; 538 uint32_t ui32 = 0; 539 uint64_t ui64 = 0; 540 int i, found; 541 int ui32_size = sizeof(ui32); 542 543 if (!info->return_size || !info->return_pointer) 544 return -EINVAL; 545 546 switch (info->query) { 547 case AMDGPU_INFO_ACCEL_WORKING: 548 ui32 = adev->accel_working; 549 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 550 case AMDGPU_INFO_CRTC_FROM_ID: 551 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 552 crtc = (struct drm_crtc *)minfo->crtcs[i]; 553 if (crtc && crtc->base.id == info->mode_crtc.id) { 554 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 555 ui32 = amdgpu_crtc->crtc_id; 556 found = 1; 557 break; 558 } 559 } 560 if (!found) { 561 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 562 return -EINVAL; 563 } 564 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 565 case AMDGPU_INFO_HW_IP_INFO: { 566 struct drm_amdgpu_info_hw_ip ip = {}; 567 int ret; 568 569 ret = amdgpu_hw_ip_info(adev, info, &ip); 570 if (ret) 571 return ret; 572 573 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 574 return ret ? -EFAULT : 0; 575 } 576 case AMDGPU_INFO_HW_IP_COUNT: { 577 enum amd_ip_block_type type; 578 uint32_t count = 0; 579 580 switch (info->query_hw_ip.type) { 581 case AMDGPU_HW_IP_GFX: 582 type = AMD_IP_BLOCK_TYPE_GFX; 583 break; 584 case AMDGPU_HW_IP_COMPUTE: 585 type = AMD_IP_BLOCK_TYPE_GFX; 586 break; 587 case AMDGPU_HW_IP_DMA: 588 type = AMD_IP_BLOCK_TYPE_SDMA; 589 break; 590 case AMDGPU_HW_IP_UVD: 591 type = AMD_IP_BLOCK_TYPE_UVD; 592 break; 593 case AMDGPU_HW_IP_VCE: 594 type = AMD_IP_BLOCK_TYPE_VCE; 595 break; 596 case AMDGPU_HW_IP_UVD_ENC: 597 type = AMD_IP_BLOCK_TYPE_UVD; 598 break; 599 case AMDGPU_HW_IP_VCN_DEC: 600 case AMDGPU_HW_IP_VCN_ENC: 601 type = AMD_IP_BLOCK_TYPE_VCN; 602 break; 603 case AMDGPU_HW_IP_VCN_JPEG: 604 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 605 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 606 break; 607 default: 608 return -EINVAL; 609 } 610 611 for (i = 0; i < adev->num_ip_blocks; i++) 612 if (adev->ip_blocks[i].version->type == type && 613 adev->ip_blocks[i].status.valid && 614 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 615 count++; 616 617 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 618 } 619 case AMDGPU_INFO_TIMESTAMP: 620 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 621 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 622 case AMDGPU_INFO_FW_VERSION: { 623 struct drm_amdgpu_info_firmware fw_info; 624 int ret; 625 626 /* We only support one instance of each IP block right now. */ 627 if (info->query_fw.ip_instance != 0) 628 return -EINVAL; 629 630 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 631 if (ret) 632 return ret; 633 634 return copy_to_user(out, &fw_info, 635 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 636 } 637 case AMDGPU_INFO_NUM_BYTES_MOVED: 638 ui64 = atomic64_read(&adev->num_bytes_moved); 639 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 640 case AMDGPU_INFO_NUM_EVICTIONS: 641 ui64 = atomic64_read(&adev->num_evictions); 642 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 643 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 644 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 645 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 646 case AMDGPU_INFO_VRAM_USAGE: 647 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 648 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 649 case AMDGPU_INFO_VIS_VRAM_USAGE: 650 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 651 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 652 case AMDGPU_INFO_GTT_USAGE: 653 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 654 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 655 case AMDGPU_INFO_GDS_CONFIG: { 656 struct drm_amdgpu_info_gds gds_info; 657 658 memset(&gds_info, 0, sizeof(gds_info)); 659 gds_info.compute_partition_size = adev->gds.gds_size; 660 gds_info.gds_total_size = adev->gds.gds_size; 661 gds_info.gws_per_compute_partition = adev->gds.gws_size; 662 gds_info.oa_per_compute_partition = adev->gds.oa_size; 663 return copy_to_user(out, &gds_info, 664 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 665 } 666 case AMDGPU_INFO_VRAM_GTT: { 667 struct drm_amdgpu_info_vram_gtt vram_gtt; 668 669 vram_gtt.vram_size = adev->gmc.real_vram_size - 670 atomic64_read(&adev->vram_pin_size) - 671 AMDGPU_VM_RESERVED_VRAM; 672 vram_gtt.vram_cpu_accessible_size = 673 min(adev->gmc.visible_vram_size - 674 atomic64_read(&adev->visible_pin_size), 675 vram_gtt.vram_size); 676 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 677 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 678 return copy_to_user(out, &vram_gtt, 679 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 680 } 681 case AMDGPU_INFO_MEMORY: { 682 struct drm_amdgpu_memory_info mem; 683 struct ttm_resource_manager *gtt_man = 684 &adev->mman.gtt_mgr.manager; 685 struct ttm_resource_manager *vram_man = 686 &adev->mman.vram_mgr.manager; 687 688 memset(&mem, 0, sizeof(mem)); 689 mem.vram.total_heap_size = adev->gmc.real_vram_size; 690 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 691 atomic64_read(&adev->vram_pin_size) - 692 AMDGPU_VM_RESERVED_VRAM; 693 mem.vram.heap_usage = 694 ttm_resource_manager_usage(vram_man); 695 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 696 697 mem.cpu_accessible_vram.total_heap_size = 698 adev->gmc.visible_vram_size; 699 mem.cpu_accessible_vram.usable_heap_size = 700 min(adev->gmc.visible_vram_size - 701 atomic64_read(&adev->visible_pin_size), 702 mem.vram.usable_heap_size); 703 mem.cpu_accessible_vram.heap_usage = 704 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 705 mem.cpu_accessible_vram.max_allocation = 706 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 707 708 mem.gtt.total_heap_size = gtt_man->size; 709 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 710 atomic64_read(&adev->gart_pin_size); 711 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 712 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 713 714 return copy_to_user(out, &mem, 715 min((size_t)size, sizeof(mem))) 716 ? -EFAULT : 0; 717 } 718 case AMDGPU_INFO_READ_MMR_REG: { 719 unsigned n, alloc_size; 720 uint32_t *regs; 721 unsigned se_num = (info->read_mmr_reg.instance >> 722 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 723 AMDGPU_INFO_MMR_SE_INDEX_MASK; 724 unsigned sh_num = (info->read_mmr_reg.instance >> 725 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 726 AMDGPU_INFO_MMR_SH_INDEX_MASK; 727 728 /* set full masks if the userspace set all bits 729 * in the bitfields */ 730 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 731 se_num = 0xffffffff; 732 else if (se_num >= AMDGPU_GFX_MAX_SE) 733 return -EINVAL; 734 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 735 sh_num = 0xffffffff; 736 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 737 return -EINVAL; 738 739 if (info->read_mmr_reg.count > 128) 740 return -EINVAL; 741 742 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 743 if (!regs) 744 return -ENOMEM; 745 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 746 747 amdgpu_gfx_off_ctrl(adev, false); 748 for (i = 0; i < info->read_mmr_reg.count; i++) { 749 if (amdgpu_asic_read_register(adev, se_num, sh_num, 750 info->read_mmr_reg.dword_offset + i, 751 ®s[i])) { 752 DRM_DEBUG_KMS("unallowed offset %#x\n", 753 info->read_mmr_reg.dword_offset + i); 754 kfree(regs); 755 amdgpu_gfx_off_ctrl(adev, true); 756 return -EFAULT; 757 } 758 } 759 amdgpu_gfx_off_ctrl(adev, true); 760 n = copy_to_user(out, regs, min(size, alloc_size)); 761 kfree(regs); 762 return n ? -EFAULT : 0; 763 } 764 case AMDGPU_INFO_DEV_INFO: { 765 struct drm_amdgpu_info_device *dev_info; 766 uint64_t vm_size; 767 int ret; 768 769 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 770 if (!dev_info) 771 return -ENOMEM; 772 773 dev_info->device_id = adev->pdev->device; 774 dev_info->chip_rev = adev->rev_id; 775 dev_info->external_rev = adev->external_rev_id; 776 dev_info->pci_rev = adev->pdev->revision; 777 dev_info->family = adev->family; 778 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 779 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 780 /* return all clocks in KHz */ 781 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 782 if (adev->pm.dpm_enabled) { 783 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 784 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 785 } else { 786 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 787 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 788 } 789 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 790 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 791 adev->gfx.config.max_shader_engines; 792 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 793 dev_info->_pad = 0; 794 dev_info->ids_flags = 0; 795 if (adev->flags & AMD_IS_APU) 796 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 797 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 798 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 799 if (amdgpu_is_tmz(adev)) 800 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 801 802 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 803 vm_size -= AMDGPU_VA_RESERVED_SIZE; 804 805 /* Older VCE FW versions are buggy and can handle only 40bits */ 806 if (adev->vce.fw_version && 807 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 808 vm_size = min(vm_size, 1ULL << 40); 809 810 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 811 dev_info->virtual_address_max = 812 min(vm_size, AMDGPU_GMC_HOLE_START); 813 814 if (vm_size > AMDGPU_GMC_HOLE_START) { 815 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 816 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 817 } 818 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 819 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 820 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 821 dev_info->cu_active_number = adev->gfx.cu_info.number; 822 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 823 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 824 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 825 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 826 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 827 sizeof(adev->gfx.cu_info.bitmap)); 828 dev_info->vram_type = adev->gmc.vram_type; 829 dev_info->vram_bit_width = adev->gmc.vram_width; 830 dev_info->vce_harvest_config = adev->vce.harvest_config; 831 dev_info->gc_double_offchip_lds_buf = 832 adev->gfx.config.double_offchip_lds_buf; 833 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 834 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 835 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 836 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 837 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 838 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 839 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 840 841 if (adev->family >= AMDGPU_FAMILY_NV) 842 dev_info->pa_sc_tile_steering_override = 843 adev->gfx.config.pa_sc_tile_steering_override; 844 845 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 846 847 ret = copy_to_user(out, dev_info, 848 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 849 kfree(dev_info); 850 return ret; 851 } 852 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 853 unsigned i; 854 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 855 struct amd_vce_state *vce_state; 856 857 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 858 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 859 if (vce_state) { 860 vce_clk_table.entries[i].sclk = vce_state->sclk; 861 vce_clk_table.entries[i].mclk = vce_state->mclk; 862 vce_clk_table.entries[i].eclk = vce_state->evclk; 863 vce_clk_table.num_valid_entries++; 864 } 865 } 866 867 return copy_to_user(out, &vce_clk_table, 868 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 869 } 870 case AMDGPU_INFO_VBIOS: { 871 uint32_t bios_size = adev->bios_size; 872 873 switch (info->vbios_info.type) { 874 case AMDGPU_INFO_VBIOS_SIZE: 875 return copy_to_user(out, &bios_size, 876 min((size_t)size, sizeof(bios_size))) 877 ? -EFAULT : 0; 878 case AMDGPU_INFO_VBIOS_IMAGE: { 879 uint8_t *bios; 880 uint32_t bios_offset = info->vbios_info.offset; 881 882 if (bios_offset >= bios_size) 883 return -EINVAL; 884 885 bios = adev->bios + bios_offset; 886 return copy_to_user(out, bios, 887 min((size_t)size, (size_t)(bios_size - bios_offset))) 888 ? -EFAULT : 0; 889 } 890 case AMDGPU_INFO_VBIOS_INFO: { 891 struct drm_amdgpu_info_vbios vbios_info = {}; 892 struct atom_context *atom_context; 893 894 atom_context = adev->mode_info.atom_context; 895 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 896 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 897 vbios_info.version = atom_context->version; 898 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 899 sizeof(atom_context->vbios_ver_str)); 900 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 901 902 return copy_to_user(out, &vbios_info, 903 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 904 } 905 default: 906 DRM_DEBUG_KMS("Invalid request %d\n", 907 info->vbios_info.type); 908 return -EINVAL; 909 } 910 } 911 case AMDGPU_INFO_NUM_HANDLES: { 912 struct drm_amdgpu_info_num_handles handle; 913 914 switch (info->query_hw_ip.type) { 915 case AMDGPU_HW_IP_UVD: 916 /* Starting Polaris, we support unlimited UVD handles */ 917 if (adev->asic_type < CHIP_POLARIS10) { 918 handle.uvd_max_handles = adev->uvd.max_handles; 919 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 920 921 return copy_to_user(out, &handle, 922 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 923 } else { 924 return -ENODATA; 925 } 926 927 break; 928 default: 929 return -EINVAL; 930 } 931 } 932 case AMDGPU_INFO_SENSOR: { 933 if (!adev->pm.dpm_enabled) 934 return -ENOENT; 935 936 switch (info->sensor_info.type) { 937 case AMDGPU_INFO_SENSOR_GFX_SCLK: 938 /* get sclk in Mhz */ 939 if (amdgpu_dpm_read_sensor(adev, 940 AMDGPU_PP_SENSOR_GFX_SCLK, 941 (void *)&ui32, &ui32_size)) { 942 return -EINVAL; 943 } 944 ui32 /= 100; 945 break; 946 case AMDGPU_INFO_SENSOR_GFX_MCLK: 947 /* get mclk in Mhz */ 948 if (amdgpu_dpm_read_sensor(adev, 949 AMDGPU_PP_SENSOR_GFX_MCLK, 950 (void *)&ui32, &ui32_size)) { 951 return -EINVAL; 952 } 953 ui32 /= 100; 954 break; 955 case AMDGPU_INFO_SENSOR_GPU_TEMP: 956 /* get temperature in millidegrees C */ 957 if (amdgpu_dpm_read_sensor(adev, 958 AMDGPU_PP_SENSOR_GPU_TEMP, 959 (void *)&ui32, &ui32_size)) { 960 return -EINVAL; 961 } 962 break; 963 case AMDGPU_INFO_SENSOR_GPU_LOAD: 964 /* get GPU load */ 965 if (amdgpu_dpm_read_sensor(adev, 966 AMDGPU_PP_SENSOR_GPU_LOAD, 967 (void *)&ui32, &ui32_size)) { 968 return -EINVAL; 969 } 970 break; 971 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 972 /* get average GPU power */ 973 if (amdgpu_dpm_read_sensor(adev, 974 AMDGPU_PP_SENSOR_GPU_POWER, 975 (void *)&ui32, &ui32_size)) { 976 return -EINVAL; 977 } 978 ui32 >>= 8; 979 break; 980 case AMDGPU_INFO_SENSOR_VDDNB: 981 /* get VDDNB in millivolts */ 982 if (amdgpu_dpm_read_sensor(adev, 983 AMDGPU_PP_SENSOR_VDDNB, 984 (void *)&ui32, &ui32_size)) { 985 return -EINVAL; 986 } 987 break; 988 case AMDGPU_INFO_SENSOR_VDDGFX: 989 /* get VDDGFX in millivolts */ 990 if (amdgpu_dpm_read_sensor(adev, 991 AMDGPU_PP_SENSOR_VDDGFX, 992 (void *)&ui32, &ui32_size)) { 993 return -EINVAL; 994 } 995 break; 996 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 997 /* get stable pstate sclk in Mhz */ 998 if (amdgpu_dpm_read_sensor(adev, 999 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1000 (void *)&ui32, &ui32_size)) { 1001 return -EINVAL; 1002 } 1003 ui32 /= 100; 1004 break; 1005 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1006 /* get stable pstate mclk in Mhz */ 1007 if (amdgpu_dpm_read_sensor(adev, 1008 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1009 (void *)&ui32, &ui32_size)) { 1010 return -EINVAL; 1011 } 1012 ui32 /= 100; 1013 break; 1014 default: 1015 DRM_DEBUG_KMS("Invalid request %d\n", 1016 info->sensor_info.type); 1017 return -EINVAL; 1018 } 1019 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1020 } 1021 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1022 ui32 = atomic_read(&adev->vram_lost_counter); 1023 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1024 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1025 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1026 uint64_t ras_mask; 1027 1028 if (!ras) 1029 return -EINVAL; 1030 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1031 1032 return copy_to_user(out, &ras_mask, 1033 min_t(u64, size, sizeof(ras_mask))) ? 1034 -EFAULT : 0; 1035 } 1036 case AMDGPU_INFO_VIDEO_CAPS: { 1037 const struct amdgpu_video_codecs *codecs; 1038 struct drm_amdgpu_info_video_caps *caps; 1039 int r; 1040 1041 switch (info->video_cap.type) { 1042 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1043 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1044 if (r) 1045 return -EINVAL; 1046 break; 1047 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1048 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1049 if (r) 1050 return -EINVAL; 1051 break; 1052 default: 1053 DRM_DEBUG_KMS("Invalid request %d\n", 1054 info->video_cap.type); 1055 return -EINVAL; 1056 } 1057 1058 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1059 if (!caps) 1060 return -ENOMEM; 1061 1062 for (i = 0; i < codecs->codec_count; i++) { 1063 int idx = codecs->codec_array[i].codec_type; 1064 1065 switch (idx) { 1066 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1067 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1068 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1069 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1070 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1071 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1072 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1073 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1074 caps->codec_info[idx].valid = 1; 1075 caps->codec_info[idx].max_width = 1076 codecs->codec_array[i].max_width; 1077 caps->codec_info[idx].max_height = 1078 codecs->codec_array[i].max_height; 1079 caps->codec_info[idx].max_pixels_per_frame = 1080 codecs->codec_array[i].max_pixels_per_frame; 1081 caps->codec_info[idx].max_level = 1082 codecs->codec_array[i].max_level; 1083 break; 1084 default: 1085 break; 1086 } 1087 } 1088 r = copy_to_user(out, caps, 1089 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1090 kfree(caps); 1091 return r; 1092 } 1093 default: 1094 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1095 return -EINVAL; 1096 } 1097 return 0; 1098 } 1099 1100 1101 /* 1102 * Outdated mess for old drm with Xorg being in charge (void function now). 1103 */ 1104 /** 1105 * amdgpu_driver_lastclose_kms - drm callback for last close 1106 * 1107 * @dev: drm dev pointer 1108 * 1109 * Switch vga_switcheroo state after last close (all asics). 1110 */ 1111 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1112 { 1113 drm_fb_helper_lastclose(dev); 1114 vga_switcheroo_process_delayed_switch(); 1115 } 1116 1117 /** 1118 * amdgpu_driver_open_kms - drm callback for open 1119 * 1120 * @dev: drm dev pointer 1121 * @file_priv: drm file 1122 * 1123 * On device open, init vm on cayman+ (all asics). 1124 * Returns 0 on success, error on failure. 1125 */ 1126 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1127 { 1128 struct amdgpu_device *adev = drm_to_adev(dev); 1129 struct amdgpu_fpriv *fpriv; 1130 int r, pasid; 1131 1132 /* Ensure IB tests are run on ring */ 1133 flush_delayed_work(&adev->delayed_init_work); 1134 1135 1136 if (amdgpu_ras_intr_triggered()) { 1137 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1138 return -EHWPOISON; 1139 } 1140 1141 file_priv->driver_priv = NULL; 1142 1143 r = pm_runtime_get_sync(dev->dev); 1144 if (r < 0) 1145 goto pm_put; 1146 1147 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1148 if (unlikely(!fpriv)) { 1149 r = -ENOMEM; 1150 goto out_suspend; 1151 } 1152 1153 pasid = amdgpu_pasid_alloc(16); 1154 if (pasid < 0) { 1155 dev_warn(adev->dev, "No more PASIDs available!"); 1156 pasid = 0; 1157 } 1158 1159 r = amdgpu_vm_init(adev, &fpriv->vm); 1160 if (r) 1161 goto error_pasid; 1162 1163 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1164 if (r) 1165 goto error_vm; 1166 1167 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1168 if (!fpriv->prt_va) { 1169 r = -ENOMEM; 1170 goto error_vm; 1171 } 1172 1173 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1174 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1175 1176 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1177 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1178 if (r) 1179 goto error_vm; 1180 } 1181 1182 mutex_init(&fpriv->bo_list_lock); 1183 idr_init_base(&fpriv->bo_list_handles, 1); 1184 1185 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1186 1187 file_priv->driver_priv = fpriv; 1188 goto out_suspend; 1189 1190 error_vm: 1191 amdgpu_vm_fini(adev, &fpriv->vm); 1192 1193 error_pasid: 1194 if (pasid) { 1195 amdgpu_pasid_free(pasid); 1196 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1197 } 1198 1199 kfree(fpriv); 1200 1201 out_suspend: 1202 pm_runtime_mark_last_busy(dev->dev); 1203 pm_put: 1204 pm_runtime_put_autosuspend(dev->dev); 1205 1206 return r; 1207 } 1208 1209 /** 1210 * amdgpu_driver_postclose_kms - drm callback for post close 1211 * 1212 * @dev: drm dev pointer 1213 * @file_priv: drm file 1214 * 1215 * On device post close, tear down vm on cayman+ (all asics). 1216 */ 1217 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1218 struct drm_file *file_priv) 1219 { 1220 struct amdgpu_device *adev = drm_to_adev(dev); 1221 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1222 struct amdgpu_bo_list *list; 1223 struct amdgpu_bo *pd; 1224 u32 pasid; 1225 int handle; 1226 1227 if (!fpriv) 1228 return; 1229 1230 pm_runtime_get_sync(dev->dev); 1231 1232 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1233 amdgpu_uvd_free_handles(adev, file_priv); 1234 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1235 amdgpu_vce_free_handles(adev, file_priv); 1236 1237 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1238 /* TODO: how to handle reserve failure */ 1239 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1240 amdgpu_vm_bo_del(adev, fpriv->csa_va); 1241 fpriv->csa_va = NULL; 1242 amdgpu_bo_unreserve(adev->virt.csa_obj); 1243 } 1244 1245 pasid = fpriv->vm.pasid; 1246 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1247 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1248 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1249 amdgpu_bo_unreserve(pd); 1250 } 1251 1252 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1253 amdgpu_vm_fini(adev, &fpriv->vm); 1254 1255 if (pasid) 1256 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1257 amdgpu_bo_unref(&pd); 1258 1259 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1260 amdgpu_bo_list_put(list); 1261 1262 idr_destroy(&fpriv->bo_list_handles); 1263 mutex_destroy(&fpriv->bo_list_lock); 1264 1265 kfree(fpriv); 1266 file_priv->driver_priv = NULL; 1267 1268 pm_runtime_mark_last_busy(dev->dev); 1269 pm_runtime_put_autosuspend(dev->dev); 1270 } 1271 1272 1273 void amdgpu_driver_release_kms(struct drm_device *dev) 1274 { 1275 struct amdgpu_device *adev = drm_to_adev(dev); 1276 1277 amdgpu_device_fini_sw(adev); 1278 pci_set_drvdata(adev->pdev, NULL); 1279 } 1280 1281 /* 1282 * VBlank related functions. 1283 */ 1284 /** 1285 * amdgpu_get_vblank_counter_kms - get frame count 1286 * 1287 * @crtc: crtc to get the frame count from 1288 * 1289 * Gets the frame count on the requested crtc (all asics). 1290 * Returns frame count on success, -EINVAL on failure. 1291 */ 1292 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1293 { 1294 struct drm_device *dev = crtc->dev; 1295 unsigned int pipe = crtc->index; 1296 struct amdgpu_device *adev = drm_to_adev(dev); 1297 int vpos, hpos, stat; 1298 u32 count; 1299 1300 if (pipe >= adev->mode_info.num_crtc) { 1301 DRM_ERROR("Invalid crtc %u\n", pipe); 1302 return -EINVAL; 1303 } 1304 1305 /* The hw increments its frame counter at start of vsync, not at start 1306 * of vblank, as is required by DRM core vblank counter handling. 1307 * Cook the hw count here to make it appear to the caller as if it 1308 * incremented at start of vblank. We measure distance to start of 1309 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1310 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1311 * result by 1 to give the proper appearance to caller. 1312 */ 1313 if (adev->mode_info.crtcs[pipe]) { 1314 /* Repeat readout if needed to provide stable result if 1315 * we cross start of vsync during the queries. 1316 */ 1317 do { 1318 count = amdgpu_display_vblank_get_counter(adev, pipe); 1319 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1320 * vpos as distance to start of vblank, instead of 1321 * regular vertical scanout pos. 1322 */ 1323 stat = amdgpu_display_get_crtc_scanoutpos( 1324 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1325 &vpos, &hpos, NULL, NULL, 1326 &adev->mode_info.crtcs[pipe]->base.hwmode); 1327 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1328 1329 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1330 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1331 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1332 } else { 1333 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1334 pipe, vpos); 1335 1336 /* Bump counter if we are at >= leading edge of vblank, 1337 * but before vsync where vpos would turn negative and 1338 * the hw counter really increments. 1339 */ 1340 if (vpos >= 0) 1341 count++; 1342 } 1343 } else { 1344 /* Fallback to use value as is. */ 1345 count = amdgpu_display_vblank_get_counter(adev, pipe); 1346 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1347 } 1348 1349 return count; 1350 } 1351 1352 /** 1353 * amdgpu_enable_vblank_kms - enable vblank interrupt 1354 * 1355 * @crtc: crtc to enable vblank interrupt for 1356 * 1357 * Enable the interrupt on the requested crtc (all asics). 1358 * Returns 0 on success, -EINVAL on failure. 1359 */ 1360 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1361 { 1362 struct drm_device *dev = crtc->dev; 1363 unsigned int pipe = crtc->index; 1364 struct amdgpu_device *adev = drm_to_adev(dev); 1365 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1366 1367 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1368 } 1369 1370 /** 1371 * amdgpu_disable_vblank_kms - disable vblank interrupt 1372 * 1373 * @crtc: crtc to disable vblank interrupt for 1374 * 1375 * Disable the interrupt on the requested crtc (all asics). 1376 */ 1377 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1378 { 1379 struct drm_device *dev = crtc->dev; 1380 unsigned int pipe = crtc->index; 1381 struct amdgpu_device *adev = drm_to_adev(dev); 1382 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1383 1384 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1385 } 1386 1387 /* 1388 * Debugfs info 1389 */ 1390 #if defined(CONFIG_DEBUG_FS) 1391 1392 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1393 { 1394 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1395 struct drm_amdgpu_info_firmware fw_info; 1396 struct drm_amdgpu_query_fw query_fw; 1397 struct atom_context *ctx = adev->mode_info.atom_context; 1398 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1399 int ret, i; 1400 1401 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1402 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1403 TA_FW_NAME(XGMI), 1404 TA_FW_NAME(RAS), 1405 TA_FW_NAME(HDCP), 1406 TA_FW_NAME(DTM), 1407 TA_FW_NAME(RAP), 1408 TA_FW_NAME(SECUREDISPLAY), 1409 #undef TA_FW_NAME 1410 }; 1411 1412 /* VCE */ 1413 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1414 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1415 if (ret) 1416 return ret; 1417 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1418 fw_info.feature, fw_info.ver); 1419 1420 /* UVD */ 1421 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1422 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1423 if (ret) 1424 return ret; 1425 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1426 fw_info.feature, fw_info.ver); 1427 1428 /* GMC */ 1429 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1430 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1431 if (ret) 1432 return ret; 1433 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1434 fw_info.feature, fw_info.ver); 1435 1436 /* ME */ 1437 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1438 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1439 if (ret) 1440 return ret; 1441 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1442 fw_info.feature, fw_info.ver); 1443 1444 /* PFP */ 1445 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1446 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1447 if (ret) 1448 return ret; 1449 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1450 fw_info.feature, fw_info.ver); 1451 1452 /* CE */ 1453 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1454 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1455 if (ret) 1456 return ret; 1457 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1458 fw_info.feature, fw_info.ver); 1459 1460 /* RLC */ 1461 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1462 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1463 if (ret) 1464 return ret; 1465 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1466 fw_info.feature, fw_info.ver); 1467 1468 /* RLC SAVE RESTORE LIST CNTL */ 1469 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1470 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1471 if (ret) 1472 return ret; 1473 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1474 fw_info.feature, fw_info.ver); 1475 1476 /* RLC SAVE RESTORE LIST GPM MEM */ 1477 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1478 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1479 if (ret) 1480 return ret; 1481 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1482 fw_info.feature, fw_info.ver); 1483 1484 /* RLC SAVE RESTORE LIST SRM MEM */ 1485 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1486 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1487 if (ret) 1488 return ret; 1489 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1490 fw_info.feature, fw_info.ver); 1491 1492 /* RLCP */ 1493 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1494 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1495 if (ret) 1496 return ret; 1497 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1498 fw_info.feature, fw_info.ver); 1499 1500 /* RLCV */ 1501 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1502 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1503 if (ret) 1504 return ret; 1505 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1506 fw_info.feature, fw_info.ver); 1507 1508 /* MEC */ 1509 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1510 query_fw.index = 0; 1511 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1512 if (ret) 1513 return ret; 1514 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1515 fw_info.feature, fw_info.ver); 1516 1517 /* MEC2 */ 1518 if (adev->gfx.mec2_fw) { 1519 query_fw.index = 1; 1520 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1521 if (ret) 1522 return ret; 1523 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1524 fw_info.feature, fw_info.ver); 1525 } 1526 1527 /* IMU */ 1528 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1529 query_fw.index = 0; 1530 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1531 if (ret) 1532 return ret; 1533 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1534 fw_info.feature, fw_info.ver); 1535 1536 /* PSP SOS */ 1537 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1538 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1539 if (ret) 1540 return ret; 1541 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1542 fw_info.feature, fw_info.ver); 1543 1544 1545 /* PSP ASD */ 1546 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1547 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1548 if (ret) 1549 return ret; 1550 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1551 fw_info.feature, fw_info.ver); 1552 1553 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1554 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1555 query_fw.index = i; 1556 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1557 if (ret) 1558 continue; 1559 1560 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1561 ta_fw_name[i], fw_info.feature, fw_info.ver); 1562 } 1563 1564 /* SMC */ 1565 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1566 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1567 if (ret) 1568 return ret; 1569 smu_program = (fw_info.ver >> 24) & 0xff; 1570 smu_major = (fw_info.ver >> 16) & 0xff; 1571 smu_minor = (fw_info.ver >> 8) & 0xff; 1572 smu_debug = (fw_info.ver >> 0) & 0xff; 1573 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1574 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1575 1576 /* SDMA */ 1577 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1578 for (i = 0; i < adev->sdma.num_instances; i++) { 1579 query_fw.index = i; 1580 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1581 if (ret) 1582 return ret; 1583 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1584 i, fw_info.feature, fw_info.ver); 1585 } 1586 1587 /* VCN */ 1588 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1589 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1590 if (ret) 1591 return ret; 1592 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1593 fw_info.feature, fw_info.ver); 1594 1595 /* DMCU */ 1596 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1597 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1598 if (ret) 1599 return ret; 1600 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1601 fw_info.feature, fw_info.ver); 1602 1603 /* DMCUB */ 1604 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1605 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1606 if (ret) 1607 return ret; 1608 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1609 fw_info.feature, fw_info.ver); 1610 1611 /* TOC */ 1612 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1613 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1614 if (ret) 1615 return ret; 1616 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1617 fw_info.feature, fw_info.ver); 1618 1619 /* CAP */ 1620 if (adev->psp.cap_fw) { 1621 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1622 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1623 if (ret) 1624 return ret; 1625 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1626 fw_info.feature, fw_info.ver); 1627 } 1628 1629 /* MES_KIQ */ 1630 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1631 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1632 if (ret) 1633 return ret; 1634 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1635 fw_info.feature, fw_info.ver); 1636 1637 /* MES */ 1638 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1639 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1640 if (ret) 1641 return ret; 1642 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1643 fw_info.feature, fw_info.ver); 1644 1645 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1646 1647 return 0; 1648 } 1649 1650 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1651 1652 #endif 1653 1654 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1655 { 1656 #if defined(CONFIG_DEBUG_FS) 1657 struct drm_minor *minor = adev_to_drm(adev)->primary; 1658 struct dentry *root = minor->debugfs_root; 1659 1660 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1661 adev, &amdgpu_debugfs_firmware_info_fops); 1662 1663 #endif 1664 } 1665