1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (adev->runpm) { 91 pm_runtime_get_sync(dev->dev); 92 pm_runtime_forbid(dev->dev); 93 } 94 95 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 96 DRM_WARN("smart shift update failed\n"); 97 98 amdgpu_acpi_fini(adev); 99 amdgpu_device_fini_hw(adev); 100 } 101 102 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 103 { 104 struct amdgpu_gpu_instance *gpu_instance; 105 106 mutex_lock(&mgpu_info.mutex); 107 108 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 109 DRM_ERROR("Cannot register more gpu instance\n"); 110 mutex_unlock(&mgpu_info.mutex); 111 return; 112 } 113 114 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 115 gpu_instance->adev = adev; 116 gpu_instance->mgpu_fan_enabled = 0; 117 118 mgpu_info.num_gpu++; 119 if (adev->flags & AMD_IS_APU) 120 mgpu_info.num_apu++; 121 else 122 mgpu_info.num_dgpu++; 123 124 mutex_unlock(&mgpu_info.mutex); 125 } 126 127 static void amdgpu_get_audio_func(struct amdgpu_device *adev) 128 { 129 struct pci_dev *p = NULL; 130 131 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 132 adev->pdev->bus->number, 1); 133 if (p) { 134 pm_runtime_get_sync(&p->dev); 135 136 pm_runtime_mark_last_busy(&p->dev); 137 pm_runtime_put_autosuspend(&p->dev); 138 139 pci_dev_put(p); 140 } 141 } 142 143 /** 144 * amdgpu_driver_load_kms - Main load function for KMS. 145 * 146 * @adev: pointer to struct amdgpu_device 147 * @flags: device flags 148 * 149 * This is the main load function for KMS (all asics). 150 * Returns 0 on success, error on failure. 151 */ 152 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 153 { 154 struct drm_device *dev; 155 struct pci_dev *parent; 156 int r, acpi_status; 157 158 dev = adev_to_drm(adev); 159 160 if (amdgpu_has_atpx() && 161 (amdgpu_is_atpx_hybrid() || 162 amdgpu_has_atpx_dgpu_power_cntl()) && 163 ((flags & AMD_IS_APU) == 0) && 164 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) 165 flags |= AMD_IS_PX; 166 167 parent = pci_upstream_bridge(adev->pdev); 168 adev->has_pr3 = parent ? pci_pr3_present(parent) : false; 169 170 /* amdgpu_device_init should report only fatal error 171 * like memory allocation failure or iomapping failure, 172 * or memory manager initialization failure, it must 173 * properly initialize the GPU MC controller and permit 174 * VRAM allocation 175 */ 176 r = amdgpu_device_init(adev, flags); 177 if (r) { 178 dev_err(dev->dev, "Fatal error during GPU init\n"); 179 goto out; 180 } 181 182 if (amdgpu_device_supports_px(dev) && 183 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 184 adev->runpm = true; 185 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 186 } else if (amdgpu_device_supports_boco(dev) && 187 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 188 adev->runpm = true; 189 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 190 } else if (amdgpu_device_supports_baco(dev) && 191 (amdgpu_runtime_pm != 0)) { 192 switch (adev->asic_type) { 193 case CHIP_VEGA20: 194 case CHIP_ARCTURUS: 195 /* enable runpm if runpm=1 */ 196 if (amdgpu_runtime_pm > 0) 197 adev->runpm = true; 198 break; 199 case CHIP_VEGA10: 200 /* turn runpm on if noretry=0 */ 201 if (!adev->gmc.noretry) 202 adev->runpm = true; 203 break; 204 default: 205 /* enable runpm on CI+ */ 206 adev->runpm = true; 207 break; 208 } 209 /* XXX: disable runtime pm if we are the primary adapter 210 * to avoid displays being re-enabled after DPMS. 211 * This needs to be sorted out and fixed properly. 212 */ 213 if (adev->is_fw_fb) 214 adev->runpm = false; 215 if (adev->runpm) 216 dev_info(adev->dev, "Using BACO for runtime pm\n"); 217 } 218 219 /* Call ACPI methods: require modeset init 220 * but failure is not fatal 221 */ 222 223 acpi_status = amdgpu_acpi_init(adev); 224 if (acpi_status) 225 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 226 227 if (adev->runpm) { 228 /* only need to skip on ATPX */ 229 if (amdgpu_device_supports_px(dev)) 230 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 231 /* we want direct complete for BOCO */ 232 if (amdgpu_device_supports_boco(dev)) 233 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE | 234 DPM_FLAG_SMART_SUSPEND | 235 DPM_FLAG_MAY_SKIP_RESUME); 236 pm_runtime_use_autosuspend(dev->dev); 237 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 238 239 pm_runtime_allow(dev->dev); 240 241 pm_runtime_mark_last_busy(dev->dev); 242 pm_runtime_put_autosuspend(dev->dev); 243 244 /* 245 * For runpm implemented via BACO, PMFW will handle the 246 * timing for BACO in and out: 247 * - put ASIC into BACO state only when both video and 248 * audio functions are in D3 state. 249 * - pull ASIC out of BACO state when either video or 250 * audio function is in D0 state. 251 * Also, at startup, PMFW assumes both functions are in 252 * D0 state. 253 * 254 * So if snd driver was loaded prior to amdgpu driver 255 * and audio function was put into D3 state, there will 256 * be no PMFW-aware D-state transition(D0->D3) on runpm 257 * suspend. Thus the BACO will be not correctly kicked in. 258 * 259 * Via amdgpu_get_audio_func(), the audio dev is put 260 * into D0 state. Then there will be a PMFW-aware D-state 261 * transition(D0->D3) on runpm suspend. 262 */ 263 if (amdgpu_device_supports_baco(dev) && 264 !(adev->flags & AMD_IS_APU) && 265 (adev->asic_type >= CHIP_NAVI10)) 266 amdgpu_get_audio_func(adev); 267 } 268 269 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 270 DRM_WARN("smart shift update failed\n"); 271 272 out: 273 if (r) { 274 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 275 if (adev->rmmio && adev->runpm) 276 pm_runtime_put_noidle(dev->dev); 277 amdgpu_driver_unload_kms(dev); 278 } 279 280 return r; 281 } 282 283 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 284 struct drm_amdgpu_query_fw *query_fw, 285 struct amdgpu_device *adev) 286 { 287 switch (query_fw->fw_type) { 288 case AMDGPU_INFO_FW_VCE: 289 fw_info->ver = adev->vce.fw_version; 290 fw_info->feature = adev->vce.fb_version; 291 break; 292 case AMDGPU_INFO_FW_UVD: 293 fw_info->ver = adev->uvd.fw_version; 294 fw_info->feature = 0; 295 break; 296 case AMDGPU_INFO_FW_VCN: 297 fw_info->ver = adev->vcn.fw_version; 298 fw_info->feature = 0; 299 break; 300 case AMDGPU_INFO_FW_GMC: 301 fw_info->ver = adev->gmc.fw_version; 302 fw_info->feature = 0; 303 break; 304 case AMDGPU_INFO_FW_GFX_ME: 305 fw_info->ver = adev->gfx.me_fw_version; 306 fw_info->feature = adev->gfx.me_feature_version; 307 break; 308 case AMDGPU_INFO_FW_GFX_PFP: 309 fw_info->ver = adev->gfx.pfp_fw_version; 310 fw_info->feature = adev->gfx.pfp_feature_version; 311 break; 312 case AMDGPU_INFO_FW_GFX_CE: 313 fw_info->ver = adev->gfx.ce_fw_version; 314 fw_info->feature = adev->gfx.ce_feature_version; 315 break; 316 case AMDGPU_INFO_FW_GFX_RLC: 317 fw_info->ver = adev->gfx.rlc_fw_version; 318 fw_info->feature = adev->gfx.rlc_feature_version; 319 break; 320 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 321 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 322 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 323 break; 324 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 325 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 326 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 327 break; 328 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 329 fw_info->ver = adev->gfx.rlc_srls_fw_version; 330 fw_info->feature = adev->gfx.rlc_srls_feature_version; 331 break; 332 case AMDGPU_INFO_FW_GFX_MEC: 333 if (query_fw->index == 0) { 334 fw_info->ver = adev->gfx.mec_fw_version; 335 fw_info->feature = adev->gfx.mec_feature_version; 336 } else if (query_fw->index == 1) { 337 fw_info->ver = adev->gfx.mec2_fw_version; 338 fw_info->feature = adev->gfx.mec2_feature_version; 339 } else 340 return -EINVAL; 341 break; 342 case AMDGPU_INFO_FW_SMC: 343 fw_info->ver = adev->pm.fw_version; 344 fw_info->feature = 0; 345 break; 346 case AMDGPU_INFO_FW_TA: 347 switch (query_fw->index) { 348 case TA_FW_TYPE_PSP_XGMI: 349 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 350 fw_info->feature = adev->psp.xgmi_context.context 351 .bin_desc.feature_version; 352 break; 353 case TA_FW_TYPE_PSP_RAS: 354 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 355 fw_info->feature = adev->psp.ras_context.context 356 .bin_desc.feature_version; 357 break; 358 case TA_FW_TYPE_PSP_HDCP: 359 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 360 fw_info->feature = adev->psp.hdcp_context.context 361 .bin_desc.feature_version; 362 break; 363 case TA_FW_TYPE_PSP_DTM: 364 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 365 fw_info->feature = adev->psp.dtm_context.context 366 .bin_desc.feature_version; 367 break; 368 case TA_FW_TYPE_PSP_RAP: 369 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 370 fw_info->feature = adev->psp.rap_context.context 371 .bin_desc.feature_version; 372 break; 373 case TA_FW_TYPE_PSP_SECUREDISPLAY: 374 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 375 fw_info->feature = 376 adev->psp.securedisplay_context.context.bin_desc 377 .feature_version; 378 break; 379 default: 380 return -EINVAL; 381 } 382 break; 383 case AMDGPU_INFO_FW_SDMA: 384 if (query_fw->index >= adev->sdma.num_instances) 385 return -EINVAL; 386 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 387 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 388 break; 389 case AMDGPU_INFO_FW_SOS: 390 fw_info->ver = adev->psp.sos.fw_version; 391 fw_info->feature = adev->psp.sos.feature_version; 392 break; 393 case AMDGPU_INFO_FW_ASD: 394 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 395 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 396 break; 397 case AMDGPU_INFO_FW_DMCU: 398 fw_info->ver = adev->dm.dmcu_fw_version; 399 fw_info->feature = 0; 400 break; 401 case AMDGPU_INFO_FW_DMCUB: 402 fw_info->ver = adev->dm.dmcub_fw_version; 403 fw_info->feature = 0; 404 break; 405 case AMDGPU_INFO_FW_TOC: 406 fw_info->ver = adev->psp.toc.fw_version; 407 fw_info->feature = adev->psp.toc.feature_version; 408 break; 409 default: 410 return -EINVAL; 411 } 412 return 0; 413 } 414 415 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 416 struct drm_amdgpu_info *info, 417 struct drm_amdgpu_info_hw_ip *result) 418 { 419 uint32_t ib_start_alignment = 0; 420 uint32_t ib_size_alignment = 0; 421 enum amd_ip_block_type type; 422 unsigned int num_rings = 0; 423 unsigned int i, j; 424 425 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 426 return -EINVAL; 427 428 switch (info->query_hw_ip.type) { 429 case AMDGPU_HW_IP_GFX: 430 type = AMD_IP_BLOCK_TYPE_GFX; 431 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 432 if (adev->gfx.gfx_ring[i].sched.ready) 433 ++num_rings; 434 ib_start_alignment = 32; 435 ib_size_alignment = 32; 436 break; 437 case AMDGPU_HW_IP_COMPUTE: 438 type = AMD_IP_BLOCK_TYPE_GFX; 439 for (i = 0; i < adev->gfx.num_compute_rings; i++) 440 if (adev->gfx.compute_ring[i].sched.ready) 441 ++num_rings; 442 ib_start_alignment = 32; 443 ib_size_alignment = 32; 444 break; 445 case AMDGPU_HW_IP_DMA: 446 type = AMD_IP_BLOCK_TYPE_SDMA; 447 for (i = 0; i < adev->sdma.num_instances; i++) 448 if (adev->sdma.instance[i].ring.sched.ready) 449 ++num_rings; 450 ib_start_alignment = 256; 451 ib_size_alignment = 4; 452 break; 453 case AMDGPU_HW_IP_UVD: 454 type = AMD_IP_BLOCK_TYPE_UVD; 455 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 456 if (adev->uvd.harvest_config & (1 << i)) 457 continue; 458 459 if (adev->uvd.inst[i].ring.sched.ready) 460 ++num_rings; 461 } 462 ib_start_alignment = 64; 463 ib_size_alignment = 64; 464 break; 465 case AMDGPU_HW_IP_VCE: 466 type = AMD_IP_BLOCK_TYPE_VCE; 467 for (i = 0; i < adev->vce.num_rings; i++) 468 if (adev->vce.ring[i].sched.ready) 469 ++num_rings; 470 ib_start_alignment = 4; 471 ib_size_alignment = 1; 472 break; 473 case AMDGPU_HW_IP_UVD_ENC: 474 type = AMD_IP_BLOCK_TYPE_UVD; 475 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 476 if (adev->uvd.harvest_config & (1 << i)) 477 continue; 478 479 for (j = 0; j < adev->uvd.num_enc_rings; j++) 480 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 481 ++num_rings; 482 } 483 ib_start_alignment = 64; 484 ib_size_alignment = 64; 485 break; 486 case AMDGPU_HW_IP_VCN_DEC: 487 type = AMD_IP_BLOCK_TYPE_VCN; 488 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 489 if (adev->uvd.harvest_config & (1 << i)) 490 continue; 491 492 if (adev->vcn.inst[i].ring_dec.sched.ready) 493 ++num_rings; 494 } 495 ib_start_alignment = 16; 496 ib_size_alignment = 16; 497 break; 498 case AMDGPU_HW_IP_VCN_ENC: 499 type = AMD_IP_BLOCK_TYPE_VCN; 500 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 501 if (adev->uvd.harvest_config & (1 << i)) 502 continue; 503 504 for (j = 0; j < adev->vcn.num_enc_rings; j++) 505 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 506 ++num_rings; 507 } 508 ib_start_alignment = 64; 509 ib_size_alignment = 1; 510 break; 511 case AMDGPU_HW_IP_VCN_JPEG: 512 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 513 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 514 515 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 516 if (adev->jpeg.harvest_config & (1 << i)) 517 continue; 518 519 if (adev->jpeg.inst[i].ring_dec.sched.ready) 520 ++num_rings; 521 } 522 ib_start_alignment = 16; 523 ib_size_alignment = 16; 524 break; 525 default: 526 return -EINVAL; 527 } 528 529 for (i = 0; i < adev->num_ip_blocks; i++) 530 if (adev->ip_blocks[i].version->type == type && 531 adev->ip_blocks[i].status.valid) 532 break; 533 534 if (i == adev->num_ip_blocks) 535 return 0; 536 537 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 538 num_rings); 539 540 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 541 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 542 result->capabilities_flags = 0; 543 result->available_rings = (1 << num_rings) - 1; 544 result->ib_start_alignment = ib_start_alignment; 545 result->ib_size_alignment = ib_size_alignment; 546 return 0; 547 } 548 549 /* 550 * Userspace get information ioctl 551 */ 552 /** 553 * amdgpu_info_ioctl - answer a device specific request. 554 * 555 * @dev: drm device pointer 556 * @data: request object 557 * @filp: drm filp 558 * 559 * This function is used to pass device specific parameters to the userspace 560 * drivers. Examples include: pci device id, pipeline parms, tiling params, 561 * etc. (all asics). 562 * Returns 0 on success, -EINVAL on failure. 563 */ 564 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 565 { 566 struct amdgpu_device *adev = drm_to_adev(dev); 567 struct drm_amdgpu_info *info = data; 568 struct amdgpu_mode_info *minfo = &adev->mode_info; 569 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 570 uint32_t size = info->return_size; 571 struct drm_crtc *crtc; 572 uint32_t ui32 = 0; 573 uint64_t ui64 = 0; 574 int i, found; 575 int ui32_size = sizeof(ui32); 576 577 if (!info->return_size || !info->return_pointer) 578 return -EINVAL; 579 580 switch (info->query) { 581 case AMDGPU_INFO_ACCEL_WORKING: 582 ui32 = adev->accel_working; 583 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 584 case AMDGPU_INFO_CRTC_FROM_ID: 585 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 586 crtc = (struct drm_crtc *)minfo->crtcs[i]; 587 if (crtc && crtc->base.id == info->mode_crtc.id) { 588 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 589 ui32 = amdgpu_crtc->crtc_id; 590 found = 1; 591 break; 592 } 593 } 594 if (!found) { 595 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 596 return -EINVAL; 597 } 598 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 599 case AMDGPU_INFO_HW_IP_INFO: { 600 struct drm_amdgpu_info_hw_ip ip = {}; 601 int ret; 602 603 ret = amdgpu_hw_ip_info(adev, info, &ip); 604 if (ret) 605 return ret; 606 607 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 608 return ret ? -EFAULT : 0; 609 } 610 case AMDGPU_INFO_HW_IP_COUNT: { 611 enum amd_ip_block_type type; 612 uint32_t count = 0; 613 614 switch (info->query_hw_ip.type) { 615 case AMDGPU_HW_IP_GFX: 616 type = AMD_IP_BLOCK_TYPE_GFX; 617 break; 618 case AMDGPU_HW_IP_COMPUTE: 619 type = AMD_IP_BLOCK_TYPE_GFX; 620 break; 621 case AMDGPU_HW_IP_DMA: 622 type = AMD_IP_BLOCK_TYPE_SDMA; 623 break; 624 case AMDGPU_HW_IP_UVD: 625 type = AMD_IP_BLOCK_TYPE_UVD; 626 break; 627 case AMDGPU_HW_IP_VCE: 628 type = AMD_IP_BLOCK_TYPE_VCE; 629 break; 630 case AMDGPU_HW_IP_UVD_ENC: 631 type = AMD_IP_BLOCK_TYPE_UVD; 632 break; 633 case AMDGPU_HW_IP_VCN_DEC: 634 case AMDGPU_HW_IP_VCN_ENC: 635 type = AMD_IP_BLOCK_TYPE_VCN; 636 break; 637 case AMDGPU_HW_IP_VCN_JPEG: 638 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 639 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 for (i = 0; i < adev->num_ip_blocks; i++) 646 if (adev->ip_blocks[i].version->type == type && 647 adev->ip_blocks[i].status.valid && 648 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 649 count++; 650 651 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 652 } 653 case AMDGPU_INFO_TIMESTAMP: 654 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 655 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 656 case AMDGPU_INFO_FW_VERSION: { 657 struct drm_amdgpu_info_firmware fw_info; 658 int ret; 659 660 /* We only support one instance of each IP block right now. */ 661 if (info->query_fw.ip_instance != 0) 662 return -EINVAL; 663 664 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 665 if (ret) 666 return ret; 667 668 return copy_to_user(out, &fw_info, 669 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 670 } 671 case AMDGPU_INFO_NUM_BYTES_MOVED: 672 ui64 = atomic64_read(&adev->num_bytes_moved); 673 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 674 case AMDGPU_INFO_NUM_EVICTIONS: 675 ui64 = atomic64_read(&adev->num_evictions); 676 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 677 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 678 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 679 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 680 case AMDGPU_INFO_VRAM_USAGE: 681 ui64 = amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); 682 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 683 case AMDGPU_INFO_VIS_VRAM_USAGE: 684 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 685 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 686 case AMDGPU_INFO_GTT_USAGE: 687 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr); 688 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 689 case AMDGPU_INFO_GDS_CONFIG: { 690 struct drm_amdgpu_info_gds gds_info; 691 692 memset(&gds_info, 0, sizeof(gds_info)); 693 gds_info.compute_partition_size = adev->gds.gds_size; 694 gds_info.gds_total_size = adev->gds.gds_size; 695 gds_info.gws_per_compute_partition = adev->gds.gws_size; 696 gds_info.oa_per_compute_partition = adev->gds.oa_size; 697 return copy_to_user(out, &gds_info, 698 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 699 } 700 case AMDGPU_INFO_VRAM_GTT: { 701 struct drm_amdgpu_info_vram_gtt vram_gtt; 702 703 vram_gtt.vram_size = adev->gmc.real_vram_size - 704 atomic64_read(&adev->vram_pin_size) - 705 AMDGPU_VM_RESERVED_VRAM; 706 vram_gtt.vram_cpu_accessible_size = 707 min(adev->gmc.visible_vram_size - 708 atomic64_read(&adev->visible_pin_size), 709 vram_gtt.vram_size); 710 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 711 vram_gtt.gtt_size *= PAGE_SIZE; 712 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 713 return copy_to_user(out, &vram_gtt, 714 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 715 } 716 case AMDGPU_INFO_MEMORY: { 717 struct drm_amdgpu_memory_info mem; 718 struct ttm_resource_manager *gtt_man = 719 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 720 memset(&mem, 0, sizeof(mem)); 721 mem.vram.total_heap_size = adev->gmc.real_vram_size; 722 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 723 atomic64_read(&adev->vram_pin_size) - 724 AMDGPU_VM_RESERVED_VRAM; 725 mem.vram.heap_usage = 726 amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); 727 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 728 729 mem.cpu_accessible_vram.total_heap_size = 730 adev->gmc.visible_vram_size; 731 mem.cpu_accessible_vram.usable_heap_size = 732 min(adev->gmc.visible_vram_size - 733 atomic64_read(&adev->visible_pin_size), 734 mem.vram.usable_heap_size); 735 mem.cpu_accessible_vram.heap_usage = 736 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 737 mem.cpu_accessible_vram.max_allocation = 738 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 739 740 mem.gtt.total_heap_size = gtt_man->size; 741 mem.gtt.total_heap_size *= PAGE_SIZE; 742 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 743 atomic64_read(&adev->gart_pin_size); 744 mem.gtt.heap_usage = 745 amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr); 746 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 747 748 return copy_to_user(out, &mem, 749 min((size_t)size, sizeof(mem))) 750 ? -EFAULT : 0; 751 } 752 case AMDGPU_INFO_READ_MMR_REG: { 753 unsigned n, alloc_size; 754 uint32_t *regs; 755 unsigned se_num = (info->read_mmr_reg.instance >> 756 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 757 AMDGPU_INFO_MMR_SE_INDEX_MASK; 758 unsigned sh_num = (info->read_mmr_reg.instance >> 759 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 760 AMDGPU_INFO_MMR_SH_INDEX_MASK; 761 762 /* set full masks if the userspace set all bits 763 * in the bitfields */ 764 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 765 se_num = 0xffffffff; 766 else if (se_num >= AMDGPU_GFX_MAX_SE) 767 return -EINVAL; 768 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 769 sh_num = 0xffffffff; 770 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 771 return -EINVAL; 772 773 if (info->read_mmr_reg.count > 128) 774 return -EINVAL; 775 776 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 777 if (!regs) 778 return -ENOMEM; 779 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 780 781 amdgpu_gfx_off_ctrl(adev, false); 782 for (i = 0; i < info->read_mmr_reg.count; i++) { 783 if (amdgpu_asic_read_register(adev, se_num, sh_num, 784 info->read_mmr_reg.dword_offset + i, 785 ®s[i])) { 786 DRM_DEBUG_KMS("unallowed offset %#x\n", 787 info->read_mmr_reg.dword_offset + i); 788 kfree(regs); 789 amdgpu_gfx_off_ctrl(adev, true); 790 return -EFAULT; 791 } 792 } 793 amdgpu_gfx_off_ctrl(adev, true); 794 n = copy_to_user(out, regs, min(size, alloc_size)); 795 kfree(regs); 796 return n ? -EFAULT : 0; 797 } 798 case AMDGPU_INFO_DEV_INFO: { 799 struct drm_amdgpu_info_device *dev_info; 800 uint64_t vm_size; 801 int ret; 802 803 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 804 if (!dev_info) 805 return -ENOMEM; 806 807 dev_info->device_id = adev->pdev->device; 808 dev_info->chip_rev = adev->rev_id; 809 dev_info->external_rev = adev->external_rev_id; 810 dev_info->pci_rev = adev->pdev->revision; 811 dev_info->family = adev->family; 812 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 813 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 814 /* return all clocks in KHz */ 815 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 816 if (adev->pm.dpm_enabled) { 817 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 818 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 819 } else { 820 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 821 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 822 } 823 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 824 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 825 adev->gfx.config.max_shader_engines; 826 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 827 dev_info->_pad = 0; 828 dev_info->ids_flags = 0; 829 if (adev->flags & AMD_IS_APU) 830 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 831 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 832 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 833 if (amdgpu_is_tmz(adev)) 834 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 835 836 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 837 vm_size -= AMDGPU_VA_RESERVED_SIZE; 838 839 /* Older VCE FW versions are buggy and can handle only 40bits */ 840 if (adev->vce.fw_version && 841 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 842 vm_size = min(vm_size, 1ULL << 40); 843 844 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 845 dev_info->virtual_address_max = 846 min(vm_size, AMDGPU_GMC_HOLE_START); 847 848 if (vm_size > AMDGPU_GMC_HOLE_START) { 849 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 850 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 851 } 852 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 853 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 854 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 855 dev_info->cu_active_number = adev->gfx.cu_info.number; 856 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 857 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 858 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 859 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 860 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 861 sizeof(adev->gfx.cu_info.bitmap)); 862 dev_info->vram_type = adev->gmc.vram_type; 863 dev_info->vram_bit_width = adev->gmc.vram_width; 864 dev_info->vce_harvest_config = adev->vce.harvest_config; 865 dev_info->gc_double_offchip_lds_buf = 866 adev->gfx.config.double_offchip_lds_buf; 867 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 868 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 869 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 870 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 871 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 872 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 873 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 874 875 if (adev->family >= AMDGPU_FAMILY_NV) 876 dev_info->pa_sc_tile_steering_override = 877 adev->gfx.config.pa_sc_tile_steering_override; 878 879 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 880 881 ret = copy_to_user(out, dev_info, 882 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 883 kfree(dev_info); 884 return ret; 885 } 886 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 887 unsigned i; 888 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 889 struct amd_vce_state *vce_state; 890 891 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 892 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 893 if (vce_state) { 894 vce_clk_table.entries[i].sclk = vce_state->sclk; 895 vce_clk_table.entries[i].mclk = vce_state->mclk; 896 vce_clk_table.entries[i].eclk = vce_state->evclk; 897 vce_clk_table.num_valid_entries++; 898 } 899 } 900 901 return copy_to_user(out, &vce_clk_table, 902 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 903 } 904 case AMDGPU_INFO_VBIOS: { 905 uint32_t bios_size = adev->bios_size; 906 907 switch (info->vbios_info.type) { 908 case AMDGPU_INFO_VBIOS_SIZE: 909 return copy_to_user(out, &bios_size, 910 min((size_t)size, sizeof(bios_size))) 911 ? -EFAULT : 0; 912 case AMDGPU_INFO_VBIOS_IMAGE: { 913 uint8_t *bios; 914 uint32_t bios_offset = info->vbios_info.offset; 915 916 if (bios_offset >= bios_size) 917 return -EINVAL; 918 919 bios = adev->bios + bios_offset; 920 return copy_to_user(out, bios, 921 min((size_t)size, (size_t)(bios_size - bios_offset))) 922 ? -EFAULT : 0; 923 } 924 case AMDGPU_INFO_VBIOS_INFO: { 925 struct drm_amdgpu_info_vbios vbios_info = {}; 926 struct atom_context *atom_context; 927 928 atom_context = adev->mode_info.atom_context; 929 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 930 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 931 vbios_info.version = atom_context->version; 932 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 933 sizeof(atom_context->vbios_ver_str)); 934 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 935 936 return copy_to_user(out, &vbios_info, 937 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 938 } 939 default: 940 DRM_DEBUG_KMS("Invalid request %d\n", 941 info->vbios_info.type); 942 return -EINVAL; 943 } 944 } 945 case AMDGPU_INFO_NUM_HANDLES: { 946 struct drm_amdgpu_info_num_handles handle; 947 948 switch (info->query_hw_ip.type) { 949 case AMDGPU_HW_IP_UVD: 950 /* Starting Polaris, we support unlimited UVD handles */ 951 if (adev->asic_type < CHIP_POLARIS10) { 952 handle.uvd_max_handles = adev->uvd.max_handles; 953 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 954 955 return copy_to_user(out, &handle, 956 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 957 } else { 958 return -ENODATA; 959 } 960 961 break; 962 default: 963 return -EINVAL; 964 } 965 } 966 case AMDGPU_INFO_SENSOR: { 967 if (!adev->pm.dpm_enabled) 968 return -ENOENT; 969 970 switch (info->sensor_info.type) { 971 case AMDGPU_INFO_SENSOR_GFX_SCLK: 972 /* get sclk in Mhz */ 973 if (amdgpu_dpm_read_sensor(adev, 974 AMDGPU_PP_SENSOR_GFX_SCLK, 975 (void *)&ui32, &ui32_size)) { 976 return -EINVAL; 977 } 978 ui32 /= 100; 979 break; 980 case AMDGPU_INFO_SENSOR_GFX_MCLK: 981 /* get mclk in Mhz */ 982 if (amdgpu_dpm_read_sensor(adev, 983 AMDGPU_PP_SENSOR_GFX_MCLK, 984 (void *)&ui32, &ui32_size)) { 985 return -EINVAL; 986 } 987 ui32 /= 100; 988 break; 989 case AMDGPU_INFO_SENSOR_GPU_TEMP: 990 /* get temperature in millidegrees C */ 991 if (amdgpu_dpm_read_sensor(adev, 992 AMDGPU_PP_SENSOR_GPU_TEMP, 993 (void *)&ui32, &ui32_size)) { 994 return -EINVAL; 995 } 996 break; 997 case AMDGPU_INFO_SENSOR_GPU_LOAD: 998 /* get GPU load */ 999 if (amdgpu_dpm_read_sensor(adev, 1000 AMDGPU_PP_SENSOR_GPU_LOAD, 1001 (void *)&ui32, &ui32_size)) { 1002 return -EINVAL; 1003 } 1004 break; 1005 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1006 /* get average GPU power */ 1007 if (amdgpu_dpm_read_sensor(adev, 1008 AMDGPU_PP_SENSOR_GPU_POWER, 1009 (void *)&ui32, &ui32_size)) { 1010 return -EINVAL; 1011 } 1012 ui32 >>= 8; 1013 break; 1014 case AMDGPU_INFO_SENSOR_VDDNB: 1015 /* get VDDNB in millivolts */ 1016 if (amdgpu_dpm_read_sensor(adev, 1017 AMDGPU_PP_SENSOR_VDDNB, 1018 (void *)&ui32, &ui32_size)) { 1019 return -EINVAL; 1020 } 1021 break; 1022 case AMDGPU_INFO_SENSOR_VDDGFX: 1023 /* get VDDGFX in millivolts */ 1024 if (amdgpu_dpm_read_sensor(adev, 1025 AMDGPU_PP_SENSOR_VDDGFX, 1026 (void *)&ui32, &ui32_size)) { 1027 return -EINVAL; 1028 } 1029 break; 1030 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1031 /* get stable pstate sclk in Mhz */ 1032 if (amdgpu_dpm_read_sensor(adev, 1033 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1034 (void *)&ui32, &ui32_size)) { 1035 return -EINVAL; 1036 } 1037 ui32 /= 100; 1038 break; 1039 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1040 /* get stable pstate mclk in Mhz */ 1041 if (amdgpu_dpm_read_sensor(adev, 1042 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1043 (void *)&ui32, &ui32_size)) { 1044 return -EINVAL; 1045 } 1046 ui32 /= 100; 1047 break; 1048 default: 1049 DRM_DEBUG_KMS("Invalid request %d\n", 1050 info->sensor_info.type); 1051 return -EINVAL; 1052 } 1053 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1054 } 1055 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1056 ui32 = atomic_read(&adev->vram_lost_counter); 1057 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1058 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1059 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1060 uint64_t ras_mask; 1061 1062 if (!ras) 1063 return -EINVAL; 1064 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1065 1066 return copy_to_user(out, &ras_mask, 1067 min_t(u64, size, sizeof(ras_mask))) ? 1068 -EFAULT : 0; 1069 } 1070 case AMDGPU_INFO_VIDEO_CAPS: { 1071 const struct amdgpu_video_codecs *codecs; 1072 struct drm_amdgpu_info_video_caps *caps; 1073 int r; 1074 1075 switch (info->video_cap.type) { 1076 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1077 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1078 if (r) 1079 return -EINVAL; 1080 break; 1081 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1082 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1083 if (r) 1084 return -EINVAL; 1085 break; 1086 default: 1087 DRM_DEBUG_KMS("Invalid request %d\n", 1088 info->video_cap.type); 1089 return -EINVAL; 1090 } 1091 1092 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1093 if (!caps) 1094 return -ENOMEM; 1095 1096 for (i = 0; i < codecs->codec_count; i++) { 1097 int idx = codecs->codec_array[i].codec_type; 1098 1099 switch (idx) { 1100 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1101 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1102 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1103 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1104 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1105 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1106 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1107 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1108 caps->codec_info[idx].valid = 1; 1109 caps->codec_info[idx].max_width = 1110 codecs->codec_array[i].max_width; 1111 caps->codec_info[idx].max_height = 1112 codecs->codec_array[i].max_height; 1113 caps->codec_info[idx].max_pixels_per_frame = 1114 codecs->codec_array[i].max_pixels_per_frame; 1115 caps->codec_info[idx].max_level = 1116 codecs->codec_array[i].max_level; 1117 break; 1118 default: 1119 break; 1120 } 1121 } 1122 r = copy_to_user(out, caps, 1123 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1124 kfree(caps); 1125 return r; 1126 } 1127 default: 1128 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1129 return -EINVAL; 1130 } 1131 return 0; 1132 } 1133 1134 1135 /* 1136 * Outdated mess for old drm with Xorg being in charge (void function now). 1137 */ 1138 /** 1139 * amdgpu_driver_lastclose_kms - drm callback for last close 1140 * 1141 * @dev: drm dev pointer 1142 * 1143 * Switch vga_switcheroo state after last close (all asics). 1144 */ 1145 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1146 { 1147 drm_fb_helper_lastclose(dev); 1148 vga_switcheroo_process_delayed_switch(); 1149 } 1150 1151 /** 1152 * amdgpu_driver_open_kms - drm callback for open 1153 * 1154 * @dev: drm dev pointer 1155 * @file_priv: drm file 1156 * 1157 * On device open, init vm on cayman+ (all asics). 1158 * Returns 0 on success, error on failure. 1159 */ 1160 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1161 { 1162 struct amdgpu_device *adev = drm_to_adev(dev); 1163 struct amdgpu_fpriv *fpriv; 1164 int r, pasid; 1165 1166 /* Ensure IB tests are run on ring */ 1167 flush_delayed_work(&adev->delayed_init_work); 1168 1169 1170 if (amdgpu_ras_intr_triggered()) { 1171 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1172 return -EHWPOISON; 1173 } 1174 1175 file_priv->driver_priv = NULL; 1176 1177 r = pm_runtime_get_sync(dev->dev); 1178 if (r < 0) 1179 goto pm_put; 1180 1181 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1182 if (unlikely(!fpriv)) { 1183 r = -ENOMEM; 1184 goto out_suspend; 1185 } 1186 1187 pasid = amdgpu_pasid_alloc(16); 1188 if (pasid < 0) { 1189 dev_warn(adev->dev, "No more PASIDs available!"); 1190 pasid = 0; 1191 } 1192 1193 r = amdgpu_vm_init(adev, &fpriv->vm); 1194 if (r) 1195 goto error_pasid; 1196 1197 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1198 if (r) 1199 goto error_vm; 1200 1201 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1202 if (!fpriv->prt_va) { 1203 r = -ENOMEM; 1204 goto error_vm; 1205 } 1206 1207 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1208 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1209 1210 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1211 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1212 if (r) 1213 goto error_vm; 1214 } 1215 1216 mutex_init(&fpriv->bo_list_lock); 1217 idr_init(&fpriv->bo_list_handles); 1218 1219 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1220 1221 file_priv->driver_priv = fpriv; 1222 goto out_suspend; 1223 1224 error_vm: 1225 amdgpu_vm_fini(adev, &fpriv->vm); 1226 1227 error_pasid: 1228 if (pasid) { 1229 amdgpu_pasid_free(pasid); 1230 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1231 } 1232 1233 kfree(fpriv); 1234 1235 out_suspend: 1236 pm_runtime_mark_last_busy(dev->dev); 1237 pm_put: 1238 pm_runtime_put_autosuspend(dev->dev); 1239 1240 return r; 1241 } 1242 1243 /** 1244 * amdgpu_driver_postclose_kms - drm callback for post close 1245 * 1246 * @dev: drm dev pointer 1247 * @file_priv: drm file 1248 * 1249 * On device post close, tear down vm on cayman+ (all asics). 1250 */ 1251 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1252 struct drm_file *file_priv) 1253 { 1254 struct amdgpu_device *adev = drm_to_adev(dev); 1255 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1256 struct amdgpu_bo_list *list; 1257 struct amdgpu_bo *pd; 1258 u32 pasid; 1259 int handle; 1260 1261 if (!fpriv) 1262 return; 1263 1264 pm_runtime_get_sync(dev->dev); 1265 1266 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1267 amdgpu_uvd_free_handles(adev, file_priv); 1268 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1269 amdgpu_vce_free_handles(adev, file_priv); 1270 1271 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1272 1273 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1274 /* TODO: how to handle reserve failure */ 1275 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1276 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1277 fpriv->csa_va = NULL; 1278 amdgpu_bo_unreserve(adev->virt.csa_obj); 1279 } 1280 1281 pasid = fpriv->vm.pasid; 1282 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1283 1284 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1285 amdgpu_vm_fini(adev, &fpriv->vm); 1286 1287 if (pasid) 1288 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1289 amdgpu_bo_unref(&pd); 1290 1291 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1292 amdgpu_bo_list_put(list); 1293 1294 idr_destroy(&fpriv->bo_list_handles); 1295 mutex_destroy(&fpriv->bo_list_lock); 1296 1297 kfree(fpriv); 1298 file_priv->driver_priv = NULL; 1299 1300 pm_runtime_mark_last_busy(dev->dev); 1301 pm_runtime_put_autosuspend(dev->dev); 1302 } 1303 1304 1305 void amdgpu_driver_release_kms(struct drm_device *dev) 1306 { 1307 struct amdgpu_device *adev = drm_to_adev(dev); 1308 1309 amdgpu_device_fini_sw(adev); 1310 pci_set_drvdata(adev->pdev, NULL); 1311 } 1312 1313 /* 1314 * VBlank related functions. 1315 */ 1316 /** 1317 * amdgpu_get_vblank_counter_kms - get frame count 1318 * 1319 * @crtc: crtc to get the frame count from 1320 * 1321 * Gets the frame count on the requested crtc (all asics). 1322 * Returns frame count on success, -EINVAL on failure. 1323 */ 1324 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1325 { 1326 struct drm_device *dev = crtc->dev; 1327 unsigned int pipe = crtc->index; 1328 struct amdgpu_device *adev = drm_to_adev(dev); 1329 int vpos, hpos, stat; 1330 u32 count; 1331 1332 if (pipe >= adev->mode_info.num_crtc) { 1333 DRM_ERROR("Invalid crtc %u\n", pipe); 1334 return -EINVAL; 1335 } 1336 1337 /* The hw increments its frame counter at start of vsync, not at start 1338 * of vblank, as is required by DRM core vblank counter handling. 1339 * Cook the hw count here to make it appear to the caller as if it 1340 * incremented at start of vblank. We measure distance to start of 1341 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1342 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1343 * result by 1 to give the proper appearance to caller. 1344 */ 1345 if (adev->mode_info.crtcs[pipe]) { 1346 /* Repeat readout if needed to provide stable result if 1347 * we cross start of vsync during the queries. 1348 */ 1349 do { 1350 count = amdgpu_display_vblank_get_counter(adev, pipe); 1351 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1352 * vpos as distance to start of vblank, instead of 1353 * regular vertical scanout pos. 1354 */ 1355 stat = amdgpu_display_get_crtc_scanoutpos( 1356 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1357 &vpos, &hpos, NULL, NULL, 1358 &adev->mode_info.crtcs[pipe]->base.hwmode); 1359 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1360 1361 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1362 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1363 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1364 } else { 1365 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1366 pipe, vpos); 1367 1368 /* Bump counter if we are at >= leading edge of vblank, 1369 * but before vsync where vpos would turn negative and 1370 * the hw counter really increments. 1371 */ 1372 if (vpos >= 0) 1373 count++; 1374 } 1375 } else { 1376 /* Fallback to use value as is. */ 1377 count = amdgpu_display_vblank_get_counter(adev, pipe); 1378 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1379 } 1380 1381 return count; 1382 } 1383 1384 /** 1385 * amdgpu_enable_vblank_kms - enable vblank interrupt 1386 * 1387 * @crtc: crtc to enable vblank interrupt for 1388 * 1389 * Enable the interrupt on the requested crtc (all asics). 1390 * Returns 0 on success, -EINVAL on failure. 1391 */ 1392 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1393 { 1394 struct drm_device *dev = crtc->dev; 1395 unsigned int pipe = crtc->index; 1396 struct amdgpu_device *adev = drm_to_adev(dev); 1397 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1398 1399 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1400 } 1401 1402 /** 1403 * amdgpu_disable_vblank_kms - disable vblank interrupt 1404 * 1405 * @crtc: crtc to disable vblank interrupt for 1406 * 1407 * Disable the interrupt on the requested crtc (all asics). 1408 */ 1409 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1410 { 1411 struct drm_device *dev = crtc->dev; 1412 unsigned int pipe = crtc->index; 1413 struct amdgpu_device *adev = drm_to_adev(dev); 1414 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1415 1416 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1417 } 1418 1419 /* 1420 * Debugfs info 1421 */ 1422 #if defined(CONFIG_DEBUG_FS) 1423 1424 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1425 { 1426 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1427 struct drm_amdgpu_info_firmware fw_info; 1428 struct drm_amdgpu_query_fw query_fw; 1429 struct atom_context *ctx = adev->mode_info.atom_context; 1430 uint8_t smu_minor, smu_debug; 1431 uint16_t smu_major; 1432 int ret, i; 1433 1434 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1435 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1436 TA_FW_NAME(XGMI), 1437 TA_FW_NAME(RAS), 1438 TA_FW_NAME(HDCP), 1439 TA_FW_NAME(DTM), 1440 TA_FW_NAME(RAP), 1441 TA_FW_NAME(SECUREDISPLAY), 1442 #undef TA_FW_NAME 1443 }; 1444 1445 /* VCE */ 1446 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1447 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1448 if (ret) 1449 return ret; 1450 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1451 fw_info.feature, fw_info.ver); 1452 1453 /* UVD */ 1454 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1455 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1456 if (ret) 1457 return ret; 1458 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1459 fw_info.feature, fw_info.ver); 1460 1461 /* GMC */ 1462 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1463 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1464 if (ret) 1465 return ret; 1466 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1467 fw_info.feature, fw_info.ver); 1468 1469 /* ME */ 1470 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1471 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1472 if (ret) 1473 return ret; 1474 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1475 fw_info.feature, fw_info.ver); 1476 1477 /* PFP */ 1478 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1479 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1480 if (ret) 1481 return ret; 1482 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1483 fw_info.feature, fw_info.ver); 1484 1485 /* CE */ 1486 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1487 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1488 if (ret) 1489 return ret; 1490 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1491 fw_info.feature, fw_info.ver); 1492 1493 /* RLC */ 1494 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1495 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1496 if (ret) 1497 return ret; 1498 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1499 fw_info.feature, fw_info.ver); 1500 1501 /* RLC SAVE RESTORE LIST CNTL */ 1502 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1503 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1504 if (ret) 1505 return ret; 1506 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1507 fw_info.feature, fw_info.ver); 1508 1509 /* RLC SAVE RESTORE LIST GPM MEM */ 1510 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1511 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1512 if (ret) 1513 return ret; 1514 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1515 fw_info.feature, fw_info.ver); 1516 1517 /* RLC SAVE RESTORE LIST SRM MEM */ 1518 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1519 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1520 if (ret) 1521 return ret; 1522 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1523 fw_info.feature, fw_info.ver); 1524 1525 /* MEC */ 1526 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1527 query_fw.index = 0; 1528 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1529 if (ret) 1530 return ret; 1531 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1532 fw_info.feature, fw_info.ver); 1533 1534 /* MEC2 */ 1535 if (adev->gfx.mec2_fw) { 1536 query_fw.index = 1; 1537 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1538 if (ret) 1539 return ret; 1540 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1541 fw_info.feature, fw_info.ver); 1542 } 1543 1544 /* PSP SOS */ 1545 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1546 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1547 if (ret) 1548 return ret; 1549 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1550 fw_info.feature, fw_info.ver); 1551 1552 1553 /* PSP ASD */ 1554 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1555 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1556 if (ret) 1557 return ret; 1558 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1559 fw_info.feature, fw_info.ver); 1560 1561 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1562 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1563 query_fw.index = i; 1564 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1565 if (ret) 1566 continue; 1567 1568 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1569 ta_fw_name[i], fw_info.feature, fw_info.ver); 1570 } 1571 1572 /* SMC */ 1573 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1574 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1575 if (ret) 1576 return ret; 1577 smu_major = (fw_info.ver >> 16) & 0xffff; 1578 smu_minor = (fw_info.ver >> 8) & 0xff; 1579 smu_debug = (fw_info.ver >> 0) & 0xff; 1580 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x (%d.%d.%d)\n", 1581 fw_info.feature, fw_info.ver, smu_major, smu_minor, smu_debug); 1582 1583 /* SDMA */ 1584 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1585 for (i = 0; i < adev->sdma.num_instances; i++) { 1586 query_fw.index = i; 1587 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1588 if (ret) 1589 return ret; 1590 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1591 i, fw_info.feature, fw_info.ver); 1592 } 1593 1594 /* VCN */ 1595 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1596 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1597 if (ret) 1598 return ret; 1599 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1600 fw_info.feature, fw_info.ver); 1601 1602 /* DMCU */ 1603 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1604 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1605 if (ret) 1606 return ret; 1607 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1608 fw_info.feature, fw_info.ver); 1609 1610 /* DMCUB */ 1611 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1612 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1613 if (ret) 1614 return ret; 1615 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1616 fw_info.feature, fw_info.ver); 1617 1618 /* TOC */ 1619 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1620 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1621 if (ret) 1622 return ret; 1623 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1624 fw_info.feature, fw_info.ver); 1625 1626 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1627 1628 return 0; 1629 } 1630 1631 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1632 1633 #endif 1634 1635 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1636 { 1637 #if defined(CONFIG_DEBUG_FS) 1638 struct drm_minor *minor = adev_to_drm(adev)->primary; 1639 struct dentry *root = minor->debugfs_root; 1640 1641 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1642 adev, &amdgpu_debugfs_firmware_info_fops); 1643 1644 #endif 1645 } 1646