1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 34 #include <linux/vga_switcheroo.h> 35 #include <linux/slab.h> 36 #include <linux/pm_runtime.h> 37 #include "amdgpu_amdkfd.h" 38 39 /** 40 * amdgpu_driver_unload_kms - Main unload function for KMS. 41 * 42 * @dev: drm dev pointer 43 * 44 * This is the main unload function for KMS (all asics). 45 * Returns 0 on success. 46 */ 47 void amdgpu_driver_unload_kms(struct drm_device *dev) 48 { 49 struct amdgpu_device *adev = dev->dev_private; 50 51 if (adev == NULL) 52 return; 53 54 if (adev->rmmio == NULL) 55 goto done_free; 56 57 if (amdgpu_sriov_vf(adev)) 58 amdgpu_virt_request_full_gpu(adev, false); 59 60 if (amdgpu_device_is_px(dev)) { 61 pm_runtime_get_sync(dev->dev); 62 pm_runtime_forbid(dev->dev); 63 } 64 65 amdgpu_amdkfd_device_fini(adev); 66 67 amdgpu_acpi_fini(adev); 68 69 amdgpu_device_fini(adev); 70 71 done_free: 72 kfree(adev); 73 dev->dev_private = NULL; 74 } 75 76 /** 77 * amdgpu_driver_load_kms - Main load function for KMS. 78 * 79 * @dev: drm dev pointer 80 * @flags: device flags 81 * 82 * This is the main load function for KMS (all asics). 83 * Returns 0 on success, error on failure. 84 */ 85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 86 { 87 struct amdgpu_device *adev; 88 int r, acpi_status; 89 90 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 91 if (adev == NULL) { 92 return -ENOMEM; 93 } 94 dev->dev_private = (void *)adev; 95 96 if ((amdgpu_runtime_pm != 0) && 97 amdgpu_has_atpx() && 98 (amdgpu_is_atpx_hybrid() || 99 amdgpu_has_atpx_dgpu_power_cntl()) && 100 ((flags & AMD_IS_APU) == 0) && 101 !pci_is_thunderbolt_attached(dev->pdev)) 102 flags |= AMD_IS_PX; 103 104 /* amdgpu_device_init should report only fatal error 105 * like memory allocation failure or iomapping failure, 106 * or memory manager initialization failure, it must 107 * properly initialize the GPU MC controller and permit 108 * VRAM allocation 109 */ 110 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 111 if (r) { 112 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 113 goto out; 114 } 115 116 /* Call ACPI methods: require modeset init 117 * but failure is not fatal 118 */ 119 if (!r) { 120 acpi_status = amdgpu_acpi_init(adev); 121 if (acpi_status) 122 dev_dbg(&dev->pdev->dev, 123 "Error during ACPI methods call\n"); 124 } 125 126 amdgpu_amdkfd_load_interface(adev); 127 amdgpu_amdkfd_device_probe(adev); 128 amdgpu_amdkfd_device_init(adev); 129 130 if (amdgpu_device_is_px(dev)) { 131 pm_runtime_use_autosuspend(dev->dev); 132 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 133 pm_runtime_set_active(dev->dev); 134 pm_runtime_allow(dev->dev); 135 pm_runtime_mark_last_busy(dev->dev); 136 pm_runtime_put_autosuspend(dev->dev); 137 } 138 139 if (amdgpu_sriov_vf(adev)) 140 amdgpu_virt_release_full_gpu(adev, true); 141 142 out: 143 if (r) { 144 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 145 if (adev->rmmio && amdgpu_device_is_px(dev)) 146 pm_runtime_put_noidle(dev->dev); 147 amdgpu_driver_unload_kms(dev); 148 } 149 150 return r; 151 } 152 153 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 154 struct drm_amdgpu_query_fw *query_fw, 155 struct amdgpu_device *adev) 156 { 157 switch (query_fw->fw_type) { 158 case AMDGPU_INFO_FW_VCE: 159 fw_info->ver = adev->vce.fw_version; 160 fw_info->feature = adev->vce.fb_version; 161 break; 162 case AMDGPU_INFO_FW_UVD: 163 fw_info->ver = adev->uvd.fw_version; 164 fw_info->feature = 0; 165 break; 166 case AMDGPU_INFO_FW_GMC: 167 fw_info->ver = adev->mc.fw_version; 168 fw_info->feature = 0; 169 break; 170 case AMDGPU_INFO_FW_GFX_ME: 171 fw_info->ver = adev->gfx.me_fw_version; 172 fw_info->feature = adev->gfx.me_feature_version; 173 break; 174 case AMDGPU_INFO_FW_GFX_PFP: 175 fw_info->ver = adev->gfx.pfp_fw_version; 176 fw_info->feature = adev->gfx.pfp_feature_version; 177 break; 178 case AMDGPU_INFO_FW_GFX_CE: 179 fw_info->ver = adev->gfx.ce_fw_version; 180 fw_info->feature = adev->gfx.ce_feature_version; 181 break; 182 case AMDGPU_INFO_FW_GFX_RLC: 183 fw_info->ver = adev->gfx.rlc_fw_version; 184 fw_info->feature = adev->gfx.rlc_feature_version; 185 break; 186 case AMDGPU_INFO_FW_GFX_MEC: 187 if (query_fw->index == 0) { 188 fw_info->ver = adev->gfx.mec_fw_version; 189 fw_info->feature = adev->gfx.mec_feature_version; 190 } else if (query_fw->index == 1) { 191 fw_info->ver = adev->gfx.mec2_fw_version; 192 fw_info->feature = adev->gfx.mec2_feature_version; 193 } else 194 return -EINVAL; 195 break; 196 case AMDGPU_INFO_FW_SMC: 197 fw_info->ver = adev->pm.fw_version; 198 fw_info->feature = 0; 199 break; 200 case AMDGPU_INFO_FW_SDMA: 201 if (query_fw->index >= adev->sdma.num_instances) 202 return -EINVAL; 203 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 204 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 205 break; 206 case AMDGPU_INFO_FW_SOS: 207 fw_info->ver = adev->psp.sos_fw_version; 208 fw_info->feature = adev->psp.sos_feature_version; 209 break; 210 case AMDGPU_INFO_FW_ASD: 211 fw_info->ver = adev->psp.asd_fw_version; 212 fw_info->feature = adev->psp.asd_feature_version; 213 break; 214 default: 215 return -EINVAL; 216 } 217 return 0; 218 } 219 220 /* 221 * Userspace get information ioctl 222 */ 223 /** 224 * amdgpu_info_ioctl - answer a device specific request. 225 * 226 * @adev: amdgpu device pointer 227 * @data: request object 228 * @filp: drm filp 229 * 230 * This function is used to pass device specific parameters to the userspace 231 * drivers. Examples include: pci device id, pipeline parms, tiling params, 232 * etc. (all asics). 233 * Returns 0 on success, -EINVAL on failure. 234 */ 235 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 236 { 237 struct amdgpu_device *adev = dev->dev_private; 238 struct drm_amdgpu_info *info = data; 239 struct amdgpu_mode_info *minfo = &adev->mode_info; 240 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 241 uint32_t size = info->return_size; 242 struct drm_crtc *crtc; 243 uint32_t ui32 = 0; 244 uint64_t ui64 = 0; 245 int i, found; 246 int ui32_size = sizeof(ui32); 247 248 if (!info->return_size || !info->return_pointer) 249 return -EINVAL; 250 251 switch (info->query) { 252 case AMDGPU_INFO_ACCEL_WORKING: 253 ui32 = adev->accel_working; 254 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 255 case AMDGPU_INFO_CRTC_FROM_ID: 256 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 257 crtc = (struct drm_crtc *)minfo->crtcs[i]; 258 if (crtc && crtc->base.id == info->mode_crtc.id) { 259 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 260 ui32 = amdgpu_crtc->crtc_id; 261 found = 1; 262 break; 263 } 264 } 265 if (!found) { 266 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 267 return -EINVAL; 268 } 269 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 270 case AMDGPU_INFO_HW_IP_INFO: { 271 struct drm_amdgpu_info_hw_ip ip = {}; 272 enum amd_ip_block_type type; 273 uint32_t ring_mask = 0; 274 uint32_t ib_start_alignment = 0; 275 uint32_t ib_size_alignment = 0; 276 277 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 278 return -EINVAL; 279 280 switch (info->query_hw_ip.type) { 281 case AMDGPU_HW_IP_GFX: 282 type = AMD_IP_BLOCK_TYPE_GFX; 283 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 284 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 285 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 286 ib_size_alignment = 8; 287 break; 288 case AMDGPU_HW_IP_COMPUTE: 289 type = AMD_IP_BLOCK_TYPE_GFX; 290 for (i = 0; i < adev->gfx.num_compute_rings; i++) 291 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 292 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 293 ib_size_alignment = 8; 294 break; 295 case AMDGPU_HW_IP_DMA: 296 type = AMD_IP_BLOCK_TYPE_SDMA; 297 for (i = 0; i < adev->sdma.num_instances; i++) 298 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 299 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 300 ib_size_alignment = 1; 301 break; 302 case AMDGPU_HW_IP_UVD: 303 type = AMD_IP_BLOCK_TYPE_UVD; 304 ring_mask = adev->uvd.ring.ready ? 1 : 0; 305 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 306 ib_size_alignment = 16; 307 break; 308 case AMDGPU_HW_IP_VCE: 309 type = AMD_IP_BLOCK_TYPE_VCE; 310 for (i = 0; i < adev->vce.num_rings; i++) 311 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 312 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 313 ib_size_alignment = 1; 314 break; 315 case AMDGPU_HW_IP_UVD_ENC: 316 type = AMD_IP_BLOCK_TYPE_UVD; 317 for (i = 0; i < adev->uvd.num_enc_rings; i++) 318 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); 319 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 320 ib_size_alignment = 1; 321 break; 322 case AMDGPU_HW_IP_VCN_DEC: 323 type = AMD_IP_BLOCK_TYPE_VCN; 324 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; 325 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 326 ib_size_alignment = 16; 327 break; 328 case AMDGPU_HW_IP_VCN_ENC: 329 type = AMD_IP_BLOCK_TYPE_VCN; 330 for (i = 0; i < adev->vcn.num_enc_rings; i++) 331 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); 332 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 333 ib_size_alignment = 1; 334 break; 335 default: 336 return -EINVAL; 337 } 338 339 for (i = 0; i < adev->num_ip_blocks; i++) { 340 if (adev->ip_blocks[i].version->type == type && 341 adev->ip_blocks[i].status.valid) { 342 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 343 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 344 ip.capabilities_flags = 0; 345 ip.available_rings = ring_mask; 346 ip.ib_start_alignment = ib_start_alignment; 347 ip.ib_size_alignment = ib_size_alignment; 348 break; 349 } 350 } 351 return copy_to_user(out, &ip, 352 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 353 } 354 case AMDGPU_INFO_HW_IP_COUNT: { 355 enum amd_ip_block_type type; 356 uint32_t count = 0; 357 358 switch (info->query_hw_ip.type) { 359 case AMDGPU_HW_IP_GFX: 360 type = AMD_IP_BLOCK_TYPE_GFX; 361 break; 362 case AMDGPU_HW_IP_COMPUTE: 363 type = AMD_IP_BLOCK_TYPE_GFX; 364 break; 365 case AMDGPU_HW_IP_DMA: 366 type = AMD_IP_BLOCK_TYPE_SDMA; 367 break; 368 case AMDGPU_HW_IP_UVD: 369 type = AMD_IP_BLOCK_TYPE_UVD; 370 break; 371 case AMDGPU_HW_IP_VCE: 372 type = AMD_IP_BLOCK_TYPE_VCE; 373 break; 374 case AMDGPU_HW_IP_UVD_ENC: 375 type = AMD_IP_BLOCK_TYPE_UVD; 376 break; 377 case AMDGPU_HW_IP_VCN_DEC: 378 case AMDGPU_HW_IP_VCN_ENC: 379 type = AMD_IP_BLOCK_TYPE_VCN; 380 break; 381 default: 382 return -EINVAL; 383 } 384 385 for (i = 0; i < adev->num_ip_blocks; i++) 386 if (adev->ip_blocks[i].version->type == type && 387 adev->ip_blocks[i].status.valid && 388 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 389 count++; 390 391 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 392 } 393 case AMDGPU_INFO_TIMESTAMP: 394 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 395 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 396 case AMDGPU_INFO_FW_VERSION: { 397 struct drm_amdgpu_info_firmware fw_info; 398 int ret; 399 400 /* We only support one instance of each IP block right now. */ 401 if (info->query_fw.ip_instance != 0) 402 return -EINVAL; 403 404 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 405 if (ret) 406 return ret; 407 408 return copy_to_user(out, &fw_info, 409 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 410 } 411 case AMDGPU_INFO_NUM_BYTES_MOVED: 412 ui64 = atomic64_read(&adev->num_bytes_moved); 413 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 414 case AMDGPU_INFO_NUM_EVICTIONS: 415 ui64 = atomic64_read(&adev->num_evictions); 416 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 417 case AMDGPU_INFO_VRAM_USAGE: 418 ui64 = atomic64_read(&adev->vram_usage); 419 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 420 case AMDGPU_INFO_VIS_VRAM_USAGE: 421 ui64 = atomic64_read(&adev->vram_vis_usage); 422 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 423 case AMDGPU_INFO_GTT_USAGE: 424 ui64 = atomic64_read(&adev->gtt_usage); 425 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 426 case AMDGPU_INFO_GDS_CONFIG: { 427 struct drm_amdgpu_info_gds gds_info; 428 429 memset(&gds_info, 0, sizeof(gds_info)); 430 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 431 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 432 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 433 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 434 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 435 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 436 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 437 return copy_to_user(out, &gds_info, 438 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 439 } 440 case AMDGPU_INFO_VRAM_GTT: { 441 struct drm_amdgpu_info_vram_gtt vram_gtt; 442 443 vram_gtt.vram_size = adev->mc.real_vram_size; 444 vram_gtt.vram_size -= adev->vram_pin_size; 445 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 446 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 447 vram_gtt.gtt_size = adev->mc.gtt_size; 448 vram_gtt.gtt_size -= adev->gart_pin_size; 449 return copy_to_user(out, &vram_gtt, 450 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 451 } 452 case AMDGPU_INFO_MEMORY: { 453 struct drm_amdgpu_memory_info mem; 454 455 memset(&mem, 0, sizeof(mem)); 456 mem.vram.total_heap_size = adev->mc.real_vram_size; 457 mem.vram.usable_heap_size = 458 adev->mc.real_vram_size - adev->vram_pin_size; 459 mem.vram.heap_usage = atomic64_read(&adev->vram_usage); 460 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 461 462 mem.cpu_accessible_vram.total_heap_size = 463 adev->mc.visible_vram_size; 464 mem.cpu_accessible_vram.usable_heap_size = 465 adev->mc.visible_vram_size - 466 (adev->vram_pin_size - adev->invisible_pin_size); 467 mem.cpu_accessible_vram.heap_usage = 468 atomic64_read(&adev->vram_vis_usage); 469 mem.cpu_accessible_vram.max_allocation = 470 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 471 472 mem.gtt.total_heap_size = adev->mc.gtt_size; 473 mem.gtt.usable_heap_size = 474 adev->mc.gtt_size - adev->gart_pin_size; 475 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); 476 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 477 478 return copy_to_user(out, &mem, 479 min((size_t)size, sizeof(mem))) 480 ? -EFAULT : 0; 481 } 482 case AMDGPU_INFO_READ_MMR_REG: { 483 unsigned n, alloc_size; 484 uint32_t *regs; 485 unsigned se_num = (info->read_mmr_reg.instance >> 486 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 487 AMDGPU_INFO_MMR_SE_INDEX_MASK; 488 unsigned sh_num = (info->read_mmr_reg.instance >> 489 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 490 AMDGPU_INFO_MMR_SH_INDEX_MASK; 491 492 /* set full masks if the userspace set all bits 493 * in the bitfields */ 494 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 495 se_num = 0xffffffff; 496 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 497 sh_num = 0xffffffff; 498 499 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 500 if (!regs) 501 return -ENOMEM; 502 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 503 504 for (i = 0; i < info->read_mmr_reg.count; i++) 505 if (amdgpu_asic_read_register(adev, se_num, sh_num, 506 info->read_mmr_reg.dword_offset + i, 507 ®s[i])) { 508 DRM_DEBUG_KMS("unallowed offset %#x\n", 509 info->read_mmr_reg.dword_offset + i); 510 kfree(regs); 511 return -EFAULT; 512 } 513 n = copy_to_user(out, regs, min(size, alloc_size)); 514 kfree(regs); 515 return n ? -EFAULT : 0; 516 } 517 case AMDGPU_INFO_DEV_INFO: { 518 struct drm_amdgpu_info_device dev_info = {}; 519 520 dev_info.device_id = dev->pdev->device; 521 dev_info.chip_rev = adev->rev_id; 522 dev_info.external_rev = adev->external_rev_id; 523 dev_info.pci_rev = dev->pdev->revision; 524 dev_info.family = adev->family; 525 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 526 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 527 /* return all clocks in KHz */ 528 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 529 if (adev->pm.dpm_enabled) { 530 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 531 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 532 } else { 533 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 534 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 535 } 536 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 537 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 538 adev->gfx.config.max_shader_engines; 539 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 540 dev_info._pad = 0; 541 dev_info.ids_flags = 0; 542 if (adev->flags & AMD_IS_APU) 543 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 544 if (amdgpu_sriov_vf(adev)) 545 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 546 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 547 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 548 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 549 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * 550 AMDGPU_GPU_PAGE_SIZE; 551 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 552 553 dev_info.cu_active_number = adev->gfx.cu_info.number; 554 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 555 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 556 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 557 sizeof(adev->gfx.cu_info.bitmap)); 558 dev_info.vram_type = adev->mc.vram_type; 559 dev_info.vram_bit_width = adev->mc.vram_width; 560 dev_info.vce_harvest_config = adev->vce.harvest_config; 561 dev_info.gc_double_offchip_lds_buf = 562 adev->gfx.config.double_offchip_lds_buf; 563 564 if (amdgpu_ngg) { 565 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 566 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 567 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 568 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 569 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 570 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 571 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 572 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 573 } 574 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 575 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 576 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 577 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 578 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 579 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 580 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 581 582 return copy_to_user(out, &dev_info, 583 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 584 } 585 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 586 unsigned i; 587 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 588 struct amd_vce_state *vce_state; 589 590 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 591 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 592 if (vce_state) { 593 vce_clk_table.entries[i].sclk = vce_state->sclk; 594 vce_clk_table.entries[i].mclk = vce_state->mclk; 595 vce_clk_table.entries[i].eclk = vce_state->evclk; 596 vce_clk_table.num_valid_entries++; 597 } 598 } 599 600 return copy_to_user(out, &vce_clk_table, 601 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 602 } 603 case AMDGPU_INFO_VBIOS: { 604 uint32_t bios_size = adev->bios_size; 605 606 switch (info->vbios_info.type) { 607 case AMDGPU_INFO_VBIOS_SIZE: 608 return copy_to_user(out, &bios_size, 609 min((size_t)size, sizeof(bios_size))) 610 ? -EFAULT : 0; 611 case AMDGPU_INFO_VBIOS_IMAGE: { 612 uint8_t *bios; 613 uint32_t bios_offset = info->vbios_info.offset; 614 615 if (bios_offset >= bios_size) 616 return -EINVAL; 617 618 bios = adev->bios + bios_offset; 619 return copy_to_user(out, bios, 620 min((size_t)size, (size_t)(bios_size - bios_offset))) 621 ? -EFAULT : 0; 622 } 623 default: 624 DRM_DEBUG_KMS("Invalid request %d\n", 625 info->vbios_info.type); 626 return -EINVAL; 627 } 628 } 629 case AMDGPU_INFO_NUM_HANDLES: { 630 struct drm_amdgpu_info_num_handles handle; 631 632 switch (info->query_hw_ip.type) { 633 case AMDGPU_HW_IP_UVD: 634 /* Starting Polaris, we support unlimited UVD handles */ 635 if (adev->asic_type < CHIP_POLARIS10) { 636 handle.uvd_max_handles = adev->uvd.max_handles; 637 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 638 639 return copy_to_user(out, &handle, 640 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 641 } else { 642 return -ENODATA; 643 } 644 645 break; 646 default: 647 return -EINVAL; 648 } 649 } 650 case AMDGPU_INFO_SENSOR: { 651 struct pp_gpu_power query = {0}; 652 int query_size = sizeof(query); 653 654 if (amdgpu_dpm == 0) 655 return -ENOENT; 656 657 switch (info->sensor_info.type) { 658 case AMDGPU_INFO_SENSOR_GFX_SCLK: 659 /* get sclk in Mhz */ 660 if (amdgpu_dpm_read_sensor(adev, 661 AMDGPU_PP_SENSOR_GFX_SCLK, 662 (void *)&ui32, &ui32_size)) { 663 return -EINVAL; 664 } 665 ui32 /= 100; 666 break; 667 case AMDGPU_INFO_SENSOR_GFX_MCLK: 668 /* get mclk in Mhz */ 669 if (amdgpu_dpm_read_sensor(adev, 670 AMDGPU_PP_SENSOR_GFX_MCLK, 671 (void *)&ui32, &ui32_size)) { 672 return -EINVAL; 673 } 674 ui32 /= 100; 675 break; 676 case AMDGPU_INFO_SENSOR_GPU_TEMP: 677 /* get temperature in millidegrees C */ 678 if (amdgpu_dpm_read_sensor(adev, 679 AMDGPU_PP_SENSOR_GPU_TEMP, 680 (void *)&ui32, &ui32_size)) { 681 return -EINVAL; 682 } 683 break; 684 case AMDGPU_INFO_SENSOR_GPU_LOAD: 685 /* get GPU load */ 686 if (amdgpu_dpm_read_sensor(adev, 687 AMDGPU_PP_SENSOR_GPU_LOAD, 688 (void *)&ui32, &ui32_size)) { 689 return -EINVAL; 690 } 691 break; 692 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 693 /* get average GPU power */ 694 if (amdgpu_dpm_read_sensor(adev, 695 AMDGPU_PP_SENSOR_GPU_POWER, 696 (void *)&query, &query_size)) { 697 return -EINVAL; 698 } 699 ui32 = query.average_gpu_power >> 8; 700 break; 701 case AMDGPU_INFO_SENSOR_VDDNB: 702 /* get VDDNB in millivolts */ 703 if (amdgpu_dpm_read_sensor(adev, 704 AMDGPU_PP_SENSOR_VDDNB, 705 (void *)&ui32, &ui32_size)) { 706 return -EINVAL; 707 } 708 break; 709 case AMDGPU_INFO_SENSOR_VDDGFX: 710 /* get VDDGFX in millivolts */ 711 if (amdgpu_dpm_read_sensor(adev, 712 AMDGPU_PP_SENSOR_VDDGFX, 713 (void *)&ui32, &ui32_size)) { 714 return -EINVAL; 715 } 716 break; 717 default: 718 DRM_DEBUG_KMS("Invalid request %d\n", 719 info->sensor_info.type); 720 return -EINVAL; 721 } 722 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 723 } 724 default: 725 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 726 return -EINVAL; 727 } 728 return 0; 729 } 730 731 732 /* 733 * Outdated mess for old drm with Xorg being in charge (void function now). 734 */ 735 /** 736 * amdgpu_driver_lastclose_kms - drm callback for last close 737 * 738 * @dev: drm dev pointer 739 * 740 * Switch vga_switcheroo state after last close (all asics). 741 */ 742 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 743 { 744 struct amdgpu_device *adev = dev->dev_private; 745 746 amdgpu_fbdev_restore_mode(adev); 747 vga_switcheroo_process_delayed_switch(); 748 } 749 750 /** 751 * amdgpu_driver_open_kms - drm callback for open 752 * 753 * @dev: drm dev pointer 754 * @file_priv: drm file 755 * 756 * On device open, init vm on cayman+ (all asics). 757 * Returns 0 on success, error on failure. 758 */ 759 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 760 { 761 struct amdgpu_device *adev = dev->dev_private; 762 struct amdgpu_fpriv *fpriv; 763 int r; 764 765 file_priv->driver_priv = NULL; 766 767 r = pm_runtime_get_sync(dev->dev); 768 if (r < 0) 769 return r; 770 771 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 772 if (unlikely(!fpriv)) { 773 r = -ENOMEM; 774 goto out_suspend; 775 } 776 777 r = amdgpu_vm_init(adev, &fpriv->vm); 778 if (r) { 779 kfree(fpriv); 780 goto out_suspend; 781 } 782 783 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 784 if (!fpriv->prt_va) { 785 r = -ENOMEM; 786 amdgpu_vm_fini(adev, &fpriv->vm); 787 kfree(fpriv); 788 goto out_suspend; 789 } 790 791 if (amdgpu_sriov_vf(adev)) { 792 r = amdgpu_map_static_csa(adev, &fpriv->vm); 793 if (r) 794 goto out_suspend; 795 } 796 797 mutex_init(&fpriv->bo_list_lock); 798 idr_init(&fpriv->bo_list_handles); 799 800 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 801 802 file_priv->driver_priv = fpriv; 803 804 out_suspend: 805 pm_runtime_mark_last_busy(dev->dev); 806 pm_runtime_put_autosuspend(dev->dev); 807 808 return r; 809 } 810 811 /** 812 * amdgpu_driver_postclose_kms - drm callback for post close 813 * 814 * @dev: drm dev pointer 815 * @file_priv: drm file 816 * 817 * On device post close, tear down vm on cayman+ (all asics). 818 */ 819 void amdgpu_driver_postclose_kms(struct drm_device *dev, 820 struct drm_file *file_priv) 821 { 822 struct amdgpu_device *adev = dev->dev_private; 823 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 824 struct amdgpu_bo_list *list; 825 int handle; 826 827 if (!fpriv) 828 return; 829 830 pm_runtime_get_sync(dev->dev); 831 832 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 833 834 if (adev->asic_type != CHIP_RAVEN) { 835 amdgpu_uvd_free_handles(adev, file_priv); 836 amdgpu_vce_free_handles(adev, file_priv); 837 } 838 839 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 840 841 if (amdgpu_sriov_vf(adev)) { 842 /* TODO: how to handle reserve failure */ 843 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 844 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va); 845 fpriv->vm.csa_bo_va = NULL; 846 amdgpu_bo_unreserve(adev->virt.csa_obj); 847 } 848 849 amdgpu_vm_fini(adev, &fpriv->vm); 850 851 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 852 amdgpu_bo_list_free(list); 853 854 idr_destroy(&fpriv->bo_list_handles); 855 mutex_destroy(&fpriv->bo_list_lock); 856 857 kfree(fpriv); 858 file_priv->driver_priv = NULL; 859 860 pm_runtime_mark_last_busy(dev->dev); 861 pm_runtime_put_autosuspend(dev->dev); 862 } 863 864 /* 865 * VBlank related functions. 866 */ 867 /** 868 * amdgpu_get_vblank_counter_kms - get frame count 869 * 870 * @dev: drm dev pointer 871 * @pipe: crtc to get the frame count from 872 * 873 * Gets the frame count on the requested crtc (all asics). 874 * Returns frame count on success, -EINVAL on failure. 875 */ 876 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 877 { 878 struct amdgpu_device *adev = dev->dev_private; 879 int vpos, hpos, stat; 880 u32 count; 881 882 if (pipe >= adev->mode_info.num_crtc) { 883 DRM_ERROR("Invalid crtc %u\n", pipe); 884 return -EINVAL; 885 } 886 887 /* The hw increments its frame counter at start of vsync, not at start 888 * of vblank, as is required by DRM core vblank counter handling. 889 * Cook the hw count here to make it appear to the caller as if it 890 * incremented at start of vblank. We measure distance to start of 891 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 892 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 893 * result by 1 to give the proper appearance to caller. 894 */ 895 if (adev->mode_info.crtcs[pipe]) { 896 /* Repeat readout if needed to provide stable result if 897 * we cross start of vsync during the queries. 898 */ 899 do { 900 count = amdgpu_display_vblank_get_counter(adev, pipe); 901 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 902 * distance to start of vblank, instead of regular 903 * vertical scanout pos. 904 */ 905 stat = amdgpu_get_crtc_scanoutpos( 906 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 907 &vpos, &hpos, NULL, NULL, 908 &adev->mode_info.crtcs[pipe]->base.hwmode); 909 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 910 911 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 912 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 913 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 914 } else { 915 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 916 pipe, vpos); 917 918 /* Bump counter if we are at >= leading edge of vblank, 919 * but before vsync where vpos would turn negative and 920 * the hw counter really increments. 921 */ 922 if (vpos >= 0) 923 count++; 924 } 925 } else { 926 /* Fallback to use value as is. */ 927 count = amdgpu_display_vblank_get_counter(adev, pipe); 928 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 929 } 930 931 return count; 932 } 933 934 /** 935 * amdgpu_enable_vblank_kms - enable vblank interrupt 936 * 937 * @dev: drm dev pointer 938 * @pipe: crtc to enable vblank interrupt for 939 * 940 * Enable the interrupt on the requested crtc (all asics). 941 * Returns 0 on success, -EINVAL on failure. 942 */ 943 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 944 { 945 struct amdgpu_device *adev = dev->dev_private; 946 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 947 948 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 949 } 950 951 /** 952 * amdgpu_disable_vblank_kms - disable vblank interrupt 953 * 954 * @dev: drm dev pointer 955 * @pipe: crtc to disable vblank interrupt for 956 * 957 * Disable the interrupt on the requested crtc (all asics). 958 */ 959 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 960 { 961 struct amdgpu_device *adev = dev->dev_private; 962 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 963 964 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 965 } 966 967 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 968 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 969 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 970 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 971 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 972 /* KMS */ 973 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 974 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 975 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 976 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 977 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 978 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 979 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 980 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 981 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 982 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 983 }; 984 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 985 986 /* 987 * Debugfs info 988 */ 989 #if defined(CONFIG_DEBUG_FS) 990 991 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 992 { 993 struct drm_info_node *node = (struct drm_info_node *) m->private; 994 struct drm_device *dev = node->minor->dev; 995 struct amdgpu_device *adev = dev->dev_private; 996 struct drm_amdgpu_info_firmware fw_info; 997 struct drm_amdgpu_query_fw query_fw; 998 int ret, i; 999 1000 /* VCE */ 1001 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1002 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1003 if (ret) 1004 return ret; 1005 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1006 fw_info.feature, fw_info.ver); 1007 1008 /* UVD */ 1009 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1010 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1011 if (ret) 1012 return ret; 1013 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1014 fw_info.feature, fw_info.ver); 1015 1016 /* GMC */ 1017 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1018 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1019 if (ret) 1020 return ret; 1021 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1022 fw_info.feature, fw_info.ver); 1023 1024 /* ME */ 1025 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1026 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1027 if (ret) 1028 return ret; 1029 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1030 fw_info.feature, fw_info.ver); 1031 1032 /* PFP */ 1033 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1034 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1035 if (ret) 1036 return ret; 1037 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1038 fw_info.feature, fw_info.ver); 1039 1040 /* CE */ 1041 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1042 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1043 if (ret) 1044 return ret; 1045 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1046 fw_info.feature, fw_info.ver); 1047 1048 /* RLC */ 1049 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1050 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1051 if (ret) 1052 return ret; 1053 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1054 fw_info.feature, fw_info.ver); 1055 1056 /* MEC */ 1057 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1058 query_fw.index = 0; 1059 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1060 if (ret) 1061 return ret; 1062 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1063 fw_info.feature, fw_info.ver); 1064 1065 /* MEC2 */ 1066 if (adev->asic_type == CHIP_KAVERI || 1067 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1068 query_fw.index = 1; 1069 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1070 if (ret) 1071 return ret; 1072 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1073 fw_info.feature, fw_info.ver); 1074 } 1075 1076 /* PSP SOS */ 1077 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1078 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1079 if (ret) 1080 return ret; 1081 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1082 fw_info.feature, fw_info.ver); 1083 1084 1085 /* PSP ASD */ 1086 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1087 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1088 if (ret) 1089 return ret; 1090 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1091 fw_info.feature, fw_info.ver); 1092 1093 /* SMC */ 1094 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1095 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1096 if (ret) 1097 return ret; 1098 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1099 fw_info.feature, fw_info.ver); 1100 1101 /* SDMA */ 1102 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1103 for (i = 0; i < adev->sdma.num_instances; i++) { 1104 query_fw.index = i; 1105 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1106 if (ret) 1107 return ret; 1108 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1109 i, fw_info.feature, fw_info.ver); 1110 } 1111 1112 return 0; 1113 } 1114 1115 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1116 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1117 }; 1118 #endif 1119 1120 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1121 { 1122 #if defined(CONFIG_DEBUG_FS) 1123 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1124 ARRAY_SIZE(amdgpu_firmware_info_list)); 1125 #else 1126 return 0; 1127 #endif 1128 } 1129