1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = drm_to_adev(dev); 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 return; 90 91 if (adev->runpm) { 92 pm_runtime_get_sync(dev->dev); 93 pm_runtime_forbid(dev->dev); 94 } 95 96 amdgpu_acpi_fini(adev); 97 amdgpu_device_fini(adev); 98 } 99 100 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 101 { 102 struct amdgpu_gpu_instance *gpu_instance; 103 104 mutex_lock(&mgpu_info.mutex); 105 106 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 107 DRM_ERROR("Cannot register more gpu instance\n"); 108 mutex_unlock(&mgpu_info.mutex); 109 return; 110 } 111 112 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 113 gpu_instance->adev = adev; 114 gpu_instance->mgpu_fan_enabled = 0; 115 116 mgpu_info.num_gpu++; 117 if (adev->flags & AMD_IS_APU) 118 mgpu_info.num_apu++; 119 else 120 mgpu_info.num_dgpu++; 121 122 mutex_unlock(&mgpu_info.mutex); 123 } 124 125 /** 126 * amdgpu_driver_load_kms - Main load function for KMS. 127 * 128 * @adev: pointer to struct amdgpu_device 129 * @flags: device flags 130 * 131 * This is the main load function for KMS (all asics). 132 * Returns 0 on success, error on failure. 133 */ 134 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 135 { 136 struct drm_device *dev; 137 int r, acpi_status; 138 139 dev = adev_to_drm(adev); 140 141 if (amdgpu_has_atpx() && 142 (amdgpu_is_atpx_hybrid() || 143 amdgpu_has_atpx_dgpu_power_cntl()) && 144 ((flags & AMD_IS_APU) == 0) && 145 !pci_is_thunderbolt_attached(dev->pdev)) 146 flags |= AMD_IS_PX; 147 148 /* amdgpu_device_init should report only fatal error 149 * like memory allocation failure or iomapping failure, 150 * or memory manager initialization failure, it must 151 * properly initialize the GPU MC controller and permit 152 * VRAM allocation 153 */ 154 r = amdgpu_device_init(adev, flags); 155 if (r) { 156 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 157 goto out; 158 } 159 160 if (amdgpu_device_supports_boco(dev) && 161 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 162 adev->runpm = true; 163 } else if (amdgpu_device_supports_baco(dev) && 164 (amdgpu_runtime_pm != 0)) { 165 switch (adev->asic_type) { 166 #ifdef CONFIG_DRM_AMDGPU_CIK 167 case CHIP_BONAIRE: 168 case CHIP_HAWAII: 169 #endif 170 case CHIP_VEGA20: 171 case CHIP_ARCTURUS: 172 case CHIP_SIENNA_CICHLID: 173 case CHIP_NAVY_FLOUNDER: 174 /* enable runpm if runpm=1 */ 175 if (amdgpu_runtime_pm > 0) 176 adev->runpm = true; 177 break; 178 case CHIP_VEGA10: 179 /* turn runpm on if noretry=0 */ 180 if (!adev->gmc.noretry) 181 adev->runpm = true; 182 break; 183 default: 184 /* enable runpm on VI+ */ 185 adev->runpm = true; 186 break; 187 } 188 } 189 190 /* Call ACPI methods: require modeset init 191 * but failure is not fatal 192 */ 193 194 acpi_status = amdgpu_acpi_init(adev); 195 if (acpi_status) 196 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 197 198 if (adev->runpm) { 199 /* only need to skip on ATPX */ 200 if (amdgpu_device_supports_boco(dev) && 201 !amdgpu_is_atpx_hybrid()) 202 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 203 pm_runtime_use_autosuspend(dev->dev); 204 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 205 pm_runtime_allow(dev->dev); 206 pm_runtime_mark_last_busy(dev->dev); 207 pm_runtime_put_autosuspend(dev->dev); 208 } 209 210 out: 211 if (r) { 212 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 213 if (adev->rmmio && adev->runpm) 214 pm_runtime_put_noidle(dev->dev); 215 amdgpu_driver_unload_kms(dev); 216 } 217 218 return r; 219 } 220 221 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 222 struct drm_amdgpu_query_fw *query_fw, 223 struct amdgpu_device *adev) 224 { 225 switch (query_fw->fw_type) { 226 case AMDGPU_INFO_FW_VCE: 227 fw_info->ver = adev->vce.fw_version; 228 fw_info->feature = adev->vce.fb_version; 229 break; 230 case AMDGPU_INFO_FW_UVD: 231 fw_info->ver = adev->uvd.fw_version; 232 fw_info->feature = 0; 233 break; 234 case AMDGPU_INFO_FW_VCN: 235 fw_info->ver = adev->vcn.fw_version; 236 fw_info->feature = 0; 237 break; 238 case AMDGPU_INFO_FW_GMC: 239 fw_info->ver = adev->gmc.fw_version; 240 fw_info->feature = 0; 241 break; 242 case AMDGPU_INFO_FW_GFX_ME: 243 fw_info->ver = adev->gfx.me_fw_version; 244 fw_info->feature = adev->gfx.me_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_PFP: 247 fw_info->ver = adev->gfx.pfp_fw_version; 248 fw_info->feature = adev->gfx.pfp_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_CE: 251 fw_info->ver = adev->gfx.ce_fw_version; 252 fw_info->feature = adev->gfx.ce_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLC: 255 fw_info->ver = adev->gfx.rlc_fw_version; 256 fw_info->feature = adev->gfx.rlc_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 259 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 260 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 261 break; 262 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 263 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 264 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 265 break; 266 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 267 fw_info->ver = adev->gfx.rlc_srls_fw_version; 268 fw_info->feature = adev->gfx.rlc_srls_feature_version; 269 break; 270 case AMDGPU_INFO_FW_GFX_MEC: 271 if (query_fw->index == 0) { 272 fw_info->ver = adev->gfx.mec_fw_version; 273 fw_info->feature = adev->gfx.mec_feature_version; 274 } else if (query_fw->index == 1) { 275 fw_info->ver = adev->gfx.mec2_fw_version; 276 fw_info->feature = adev->gfx.mec2_feature_version; 277 } else 278 return -EINVAL; 279 break; 280 case AMDGPU_INFO_FW_SMC: 281 fw_info->ver = adev->pm.fw_version; 282 fw_info->feature = 0; 283 break; 284 case AMDGPU_INFO_FW_TA: 285 switch (query_fw->index) { 286 case 0: 287 fw_info->ver = adev->psp.ta_fw_version; 288 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 289 break; 290 case 1: 291 fw_info->ver = adev->psp.ta_fw_version; 292 fw_info->feature = adev->psp.ta_ras_ucode_version; 293 break; 294 case 2: 295 fw_info->ver = adev->psp.ta_fw_version; 296 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 297 break; 298 case 3: 299 fw_info->ver = adev->psp.ta_fw_version; 300 fw_info->feature = adev->psp.ta_dtm_ucode_version; 301 break; 302 default: 303 return -EINVAL; 304 } 305 break; 306 case AMDGPU_INFO_FW_SDMA: 307 if (query_fw->index >= adev->sdma.num_instances) 308 return -EINVAL; 309 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 310 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 311 break; 312 case AMDGPU_INFO_FW_SOS: 313 fw_info->ver = adev->psp.sos_fw_version; 314 fw_info->feature = adev->psp.sos_feature_version; 315 break; 316 case AMDGPU_INFO_FW_ASD: 317 fw_info->ver = adev->psp.asd_fw_version; 318 fw_info->feature = adev->psp.asd_feature_version; 319 break; 320 case AMDGPU_INFO_FW_DMCU: 321 fw_info->ver = adev->dm.dmcu_fw_version; 322 fw_info->feature = 0; 323 break; 324 case AMDGPU_INFO_FW_DMCUB: 325 fw_info->ver = adev->dm.dmcub_fw_version; 326 fw_info->feature = 0; 327 break; 328 case AMDGPU_INFO_FW_TOC: 329 fw_info->ver = adev->psp.toc_fw_version; 330 fw_info->feature = adev->psp.toc_feature_version; 331 break; 332 default: 333 return -EINVAL; 334 } 335 return 0; 336 } 337 338 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 339 struct drm_amdgpu_info *info, 340 struct drm_amdgpu_info_hw_ip *result) 341 { 342 uint32_t ib_start_alignment = 0; 343 uint32_t ib_size_alignment = 0; 344 enum amd_ip_block_type type; 345 unsigned int num_rings = 0; 346 unsigned int i, j; 347 348 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 349 return -EINVAL; 350 351 switch (info->query_hw_ip.type) { 352 case AMDGPU_HW_IP_GFX: 353 type = AMD_IP_BLOCK_TYPE_GFX; 354 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 355 if (adev->gfx.gfx_ring[i].sched.ready) 356 ++num_rings; 357 ib_start_alignment = 32; 358 ib_size_alignment = 32; 359 break; 360 case AMDGPU_HW_IP_COMPUTE: 361 type = AMD_IP_BLOCK_TYPE_GFX; 362 for (i = 0; i < adev->gfx.num_compute_rings; i++) 363 if (adev->gfx.compute_ring[i].sched.ready) 364 ++num_rings; 365 ib_start_alignment = 32; 366 ib_size_alignment = 32; 367 break; 368 case AMDGPU_HW_IP_DMA: 369 type = AMD_IP_BLOCK_TYPE_SDMA; 370 for (i = 0; i < adev->sdma.num_instances; i++) 371 if (adev->sdma.instance[i].ring.sched.ready) 372 ++num_rings; 373 ib_start_alignment = 256; 374 ib_size_alignment = 4; 375 break; 376 case AMDGPU_HW_IP_UVD: 377 type = AMD_IP_BLOCK_TYPE_UVD; 378 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 379 if (adev->uvd.harvest_config & (1 << i)) 380 continue; 381 382 if (adev->uvd.inst[i].ring.sched.ready) 383 ++num_rings; 384 } 385 ib_start_alignment = 64; 386 ib_size_alignment = 64; 387 break; 388 case AMDGPU_HW_IP_VCE: 389 type = AMD_IP_BLOCK_TYPE_VCE; 390 for (i = 0; i < adev->vce.num_rings; i++) 391 if (adev->vce.ring[i].sched.ready) 392 ++num_rings; 393 ib_start_alignment = 4; 394 ib_size_alignment = 1; 395 break; 396 case AMDGPU_HW_IP_UVD_ENC: 397 type = AMD_IP_BLOCK_TYPE_UVD; 398 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 399 if (adev->uvd.harvest_config & (1 << i)) 400 continue; 401 402 for (j = 0; j < adev->uvd.num_enc_rings; j++) 403 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 404 ++num_rings; 405 } 406 ib_start_alignment = 64; 407 ib_size_alignment = 64; 408 break; 409 case AMDGPU_HW_IP_VCN_DEC: 410 type = AMD_IP_BLOCK_TYPE_VCN; 411 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 412 if (adev->uvd.harvest_config & (1 << i)) 413 continue; 414 415 if (adev->vcn.inst[i].ring_dec.sched.ready) 416 ++num_rings; 417 } 418 ib_start_alignment = 16; 419 ib_size_alignment = 16; 420 break; 421 case AMDGPU_HW_IP_VCN_ENC: 422 type = AMD_IP_BLOCK_TYPE_VCN; 423 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 424 if (adev->uvd.harvest_config & (1 << i)) 425 continue; 426 427 for (j = 0; j < adev->vcn.num_enc_rings; j++) 428 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 429 ++num_rings; 430 } 431 ib_start_alignment = 64; 432 ib_size_alignment = 1; 433 break; 434 case AMDGPU_HW_IP_VCN_JPEG: 435 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 436 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 437 438 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 439 if (adev->jpeg.harvest_config & (1 << i)) 440 continue; 441 442 if (adev->jpeg.inst[i].ring_dec.sched.ready) 443 ++num_rings; 444 } 445 ib_start_alignment = 16; 446 ib_size_alignment = 16; 447 break; 448 default: 449 return -EINVAL; 450 } 451 452 for (i = 0; i < adev->num_ip_blocks; i++) 453 if (adev->ip_blocks[i].version->type == type && 454 adev->ip_blocks[i].status.valid) 455 break; 456 457 if (i == adev->num_ip_blocks) 458 return 0; 459 460 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 461 num_rings); 462 463 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 464 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 465 result->capabilities_flags = 0; 466 result->available_rings = (1 << num_rings) - 1; 467 result->ib_start_alignment = ib_start_alignment; 468 result->ib_size_alignment = ib_size_alignment; 469 return 0; 470 } 471 472 /* 473 * Userspace get information ioctl 474 */ 475 /** 476 * amdgpu_info_ioctl - answer a device specific request. 477 * 478 * @adev: amdgpu device pointer 479 * @data: request object 480 * @filp: drm filp 481 * 482 * This function is used to pass device specific parameters to the userspace 483 * drivers. Examples include: pci device id, pipeline parms, tiling params, 484 * etc. (all asics). 485 * Returns 0 on success, -EINVAL on failure. 486 */ 487 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 488 { 489 struct amdgpu_device *adev = drm_to_adev(dev); 490 struct drm_amdgpu_info *info = data; 491 struct amdgpu_mode_info *minfo = &adev->mode_info; 492 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 493 uint32_t size = info->return_size; 494 struct drm_crtc *crtc; 495 uint32_t ui32 = 0; 496 uint64_t ui64 = 0; 497 int i, found; 498 int ui32_size = sizeof(ui32); 499 500 if (!info->return_size || !info->return_pointer) 501 return -EINVAL; 502 503 switch (info->query) { 504 case AMDGPU_INFO_ACCEL_WORKING: 505 ui32 = adev->accel_working; 506 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 507 case AMDGPU_INFO_CRTC_FROM_ID: 508 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 509 crtc = (struct drm_crtc *)minfo->crtcs[i]; 510 if (crtc && crtc->base.id == info->mode_crtc.id) { 511 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 512 ui32 = amdgpu_crtc->crtc_id; 513 found = 1; 514 break; 515 } 516 } 517 if (!found) { 518 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 519 return -EINVAL; 520 } 521 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 522 case AMDGPU_INFO_HW_IP_INFO: { 523 struct drm_amdgpu_info_hw_ip ip = {}; 524 int ret; 525 526 ret = amdgpu_hw_ip_info(adev, info, &ip); 527 if (ret) 528 return ret; 529 530 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 531 return ret ? -EFAULT : 0; 532 } 533 case AMDGPU_INFO_HW_IP_COUNT: { 534 enum amd_ip_block_type type; 535 uint32_t count = 0; 536 537 switch (info->query_hw_ip.type) { 538 case AMDGPU_HW_IP_GFX: 539 type = AMD_IP_BLOCK_TYPE_GFX; 540 break; 541 case AMDGPU_HW_IP_COMPUTE: 542 type = AMD_IP_BLOCK_TYPE_GFX; 543 break; 544 case AMDGPU_HW_IP_DMA: 545 type = AMD_IP_BLOCK_TYPE_SDMA; 546 break; 547 case AMDGPU_HW_IP_UVD: 548 type = AMD_IP_BLOCK_TYPE_UVD; 549 break; 550 case AMDGPU_HW_IP_VCE: 551 type = AMD_IP_BLOCK_TYPE_VCE; 552 break; 553 case AMDGPU_HW_IP_UVD_ENC: 554 type = AMD_IP_BLOCK_TYPE_UVD; 555 break; 556 case AMDGPU_HW_IP_VCN_DEC: 557 case AMDGPU_HW_IP_VCN_ENC: 558 type = AMD_IP_BLOCK_TYPE_VCN; 559 break; 560 case AMDGPU_HW_IP_VCN_JPEG: 561 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 562 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 563 break; 564 default: 565 return -EINVAL; 566 } 567 568 for (i = 0; i < adev->num_ip_blocks; i++) 569 if (adev->ip_blocks[i].version->type == type && 570 adev->ip_blocks[i].status.valid && 571 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 572 count++; 573 574 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 575 } 576 case AMDGPU_INFO_TIMESTAMP: 577 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 578 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 579 case AMDGPU_INFO_FW_VERSION: { 580 struct drm_amdgpu_info_firmware fw_info; 581 int ret; 582 583 /* We only support one instance of each IP block right now. */ 584 if (info->query_fw.ip_instance != 0) 585 return -EINVAL; 586 587 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 588 if (ret) 589 return ret; 590 591 return copy_to_user(out, &fw_info, 592 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 593 } 594 case AMDGPU_INFO_NUM_BYTES_MOVED: 595 ui64 = atomic64_read(&adev->num_bytes_moved); 596 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 597 case AMDGPU_INFO_NUM_EVICTIONS: 598 ui64 = atomic64_read(&adev->num_evictions); 599 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 600 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 601 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 603 case AMDGPU_INFO_VRAM_USAGE: 604 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 606 case AMDGPU_INFO_VIS_VRAM_USAGE: 607 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 609 case AMDGPU_INFO_GTT_USAGE: 610 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 611 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 612 case AMDGPU_INFO_GDS_CONFIG: { 613 struct drm_amdgpu_info_gds gds_info; 614 615 memset(&gds_info, 0, sizeof(gds_info)); 616 gds_info.compute_partition_size = adev->gds.gds_size; 617 gds_info.gds_total_size = adev->gds.gds_size; 618 gds_info.gws_per_compute_partition = adev->gds.gws_size; 619 gds_info.oa_per_compute_partition = adev->gds.oa_size; 620 return copy_to_user(out, &gds_info, 621 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 622 } 623 case AMDGPU_INFO_VRAM_GTT: { 624 struct drm_amdgpu_info_vram_gtt vram_gtt; 625 626 vram_gtt.vram_size = adev->gmc.real_vram_size - 627 atomic64_read(&adev->vram_pin_size) - 628 AMDGPU_VM_RESERVED_VRAM; 629 vram_gtt.vram_cpu_accessible_size = 630 min(adev->gmc.visible_vram_size - 631 atomic64_read(&adev->visible_pin_size), 632 vram_gtt.vram_size); 633 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 634 vram_gtt.gtt_size *= PAGE_SIZE; 635 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 636 return copy_to_user(out, &vram_gtt, 637 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 638 } 639 case AMDGPU_INFO_MEMORY: { 640 struct drm_amdgpu_memory_info mem; 641 struct ttm_resource_manager *vram_man = 642 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 643 struct ttm_resource_manager *gtt_man = 644 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 645 memset(&mem, 0, sizeof(mem)); 646 mem.vram.total_heap_size = adev->gmc.real_vram_size; 647 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 648 atomic64_read(&adev->vram_pin_size) - 649 AMDGPU_VM_RESERVED_VRAM; 650 mem.vram.heap_usage = 651 amdgpu_vram_mgr_usage(vram_man); 652 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 653 654 mem.cpu_accessible_vram.total_heap_size = 655 adev->gmc.visible_vram_size; 656 mem.cpu_accessible_vram.usable_heap_size = 657 min(adev->gmc.visible_vram_size - 658 atomic64_read(&adev->visible_pin_size), 659 mem.vram.usable_heap_size); 660 mem.cpu_accessible_vram.heap_usage = 661 amdgpu_vram_mgr_vis_usage(vram_man); 662 mem.cpu_accessible_vram.max_allocation = 663 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 664 665 mem.gtt.total_heap_size = gtt_man->size; 666 mem.gtt.total_heap_size *= PAGE_SIZE; 667 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 668 atomic64_read(&adev->gart_pin_size); 669 mem.gtt.heap_usage = 670 amdgpu_gtt_mgr_usage(gtt_man); 671 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 672 673 return copy_to_user(out, &mem, 674 min((size_t)size, sizeof(mem))) 675 ? -EFAULT : 0; 676 } 677 case AMDGPU_INFO_READ_MMR_REG: { 678 unsigned n, alloc_size; 679 uint32_t *regs; 680 unsigned se_num = (info->read_mmr_reg.instance >> 681 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 682 AMDGPU_INFO_MMR_SE_INDEX_MASK; 683 unsigned sh_num = (info->read_mmr_reg.instance >> 684 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 685 AMDGPU_INFO_MMR_SH_INDEX_MASK; 686 687 /* set full masks if the userspace set all bits 688 * in the bitfields */ 689 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 690 se_num = 0xffffffff; 691 else if (se_num >= AMDGPU_GFX_MAX_SE) 692 return -EINVAL; 693 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 694 sh_num = 0xffffffff; 695 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 696 return -EINVAL; 697 698 if (info->read_mmr_reg.count > 128) 699 return -EINVAL; 700 701 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 702 if (!regs) 703 return -ENOMEM; 704 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 705 706 amdgpu_gfx_off_ctrl(adev, false); 707 for (i = 0; i < info->read_mmr_reg.count; i++) { 708 if (amdgpu_asic_read_register(adev, se_num, sh_num, 709 info->read_mmr_reg.dword_offset + i, 710 ®s[i])) { 711 DRM_DEBUG_KMS("unallowed offset %#x\n", 712 info->read_mmr_reg.dword_offset + i); 713 kfree(regs); 714 amdgpu_gfx_off_ctrl(adev, true); 715 return -EFAULT; 716 } 717 } 718 amdgpu_gfx_off_ctrl(adev, true); 719 n = copy_to_user(out, regs, min(size, alloc_size)); 720 kfree(regs); 721 return n ? -EFAULT : 0; 722 } 723 case AMDGPU_INFO_DEV_INFO: { 724 struct drm_amdgpu_info_device dev_info; 725 uint64_t vm_size; 726 727 memset(&dev_info, 0, sizeof(dev_info)); 728 dev_info.device_id = dev->pdev->device; 729 dev_info.chip_rev = adev->rev_id; 730 dev_info.external_rev = adev->external_rev_id; 731 dev_info.pci_rev = dev->pdev->revision; 732 dev_info.family = adev->family; 733 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 734 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 735 /* return all clocks in KHz */ 736 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 737 if (adev->pm.dpm_enabled) { 738 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 739 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 740 } else { 741 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 742 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 743 } 744 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 745 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 746 adev->gfx.config.max_shader_engines; 747 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 748 dev_info._pad = 0; 749 dev_info.ids_flags = 0; 750 if (adev->flags & AMD_IS_APU) 751 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 752 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 753 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 754 if (amdgpu_is_tmz(adev)) 755 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 756 757 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 758 vm_size -= AMDGPU_VA_RESERVED_SIZE; 759 760 /* Older VCE FW versions are buggy and can handle only 40bits */ 761 if (adev->vce.fw_version && 762 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 763 vm_size = min(vm_size, 1ULL << 40); 764 765 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 766 dev_info.virtual_address_max = 767 min(vm_size, AMDGPU_GMC_HOLE_START); 768 769 if (vm_size > AMDGPU_GMC_HOLE_START) { 770 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 771 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 772 } 773 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 774 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 775 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 776 dev_info.cu_active_number = adev->gfx.cu_info.number; 777 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 778 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 779 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 780 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 781 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 782 sizeof(adev->gfx.cu_info.bitmap)); 783 dev_info.vram_type = adev->gmc.vram_type; 784 dev_info.vram_bit_width = adev->gmc.vram_width; 785 dev_info.vce_harvest_config = adev->vce.harvest_config; 786 dev_info.gc_double_offchip_lds_buf = 787 adev->gfx.config.double_offchip_lds_buf; 788 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 789 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 790 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 791 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 792 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 793 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 794 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 795 796 if (adev->family >= AMDGPU_FAMILY_NV) 797 dev_info.pa_sc_tile_steering_override = 798 adev->gfx.config.pa_sc_tile_steering_override; 799 800 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 801 802 return copy_to_user(out, &dev_info, 803 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 804 } 805 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 806 unsigned i; 807 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 808 struct amd_vce_state *vce_state; 809 810 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 811 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 812 if (vce_state) { 813 vce_clk_table.entries[i].sclk = vce_state->sclk; 814 vce_clk_table.entries[i].mclk = vce_state->mclk; 815 vce_clk_table.entries[i].eclk = vce_state->evclk; 816 vce_clk_table.num_valid_entries++; 817 } 818 } 819 820 return copy_to_user(out, &vce_clk_table, 821 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 822 } 823 case AMDGPU_INFO_VBIOS: { 824 uint32_t bios_size = adev->bios_size; 825 826 switch (info->vbios_info.type) { 827 case AMDGPU_INFO_VBIOS_SIZE: 828 return copy_to_user(out, &bios_size, 829 min((size_t)size, sizeof(bios_size))) 830 ? -EFAULT : 0; 831 case AMDGPU_INFO_VBIOS_IMAGE: { 832 uint8_t *bios; 833 uint32_t bios_offset = info->vbios_info.offset; 834 835 if (bios_offset >= bios_size) 836 return -EINVAL; 837 838 bios = adev->bios + bios_offset; 839 return copy_to_user(out, bios, 840 min((size_t)size, (size_t)(bios_size - bios_offset))) 841 ? -EFAULT : 0; 842 } 843 default: 844 DRM_DEBUG_KMS("Invalid request %d\n", 845 info->vbios_info.type); 846 return -EINVAL; 847 } 848 } 849 case AMDGPU_INFO_NUM_HANDLES: { 850 struct drm_amdgpu_info_num_handles handle; 851 852 switch (info->query_hw_ip.type) { 853 case AMDGPU_HW_IP_UVD: 854 /* Starting Polaris, we support unlimited UVD handles */ 855 if (adev->asic_type < CHIP_POLARIS10) { 856 handle.uvd_max_handles = adev->uvd.max_handles; 857 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 858 859 return copy_to_user(out, &handle, 860 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 861 } else { 862 return -ENODATA; 863 } 864 865 break; 866 default: 867 return -EINVAL; 868 } 869 } 870 case AMDGPU_INFO_SENSOR: { 871 if (!adev->pm.dpm_enabled) 872 return -ENOENT; 873 874 switch (info->sensor_info.type) { 875 case AMDGPU_INFO_SENSOR_GFX_SCLK: 876 /* get sclk in Mhz */ 877 if (amdgpu_dpm_read_sensor(adev, 878 AMDGPU_PP_SENSOR_GFX_SCLK, 879 (void *)&ui32, &ui32_size)) { 880 return -EINVAL; 881 } 882 ui32 /= 100; 883 break; 884 case AMDGPU_INFO_SENSOR_GFX_MCLK: 885 /* get mclk in Mhz */ 886 if (amdgpu_dpm_read_sensor(adev, 887 AMDGPU_PP_SENSOR_GFX_MCLK, 888 (void *)&ui32, &ui32_size)) { 889 return -EINVAL; 890 } 891 ui32 /= 100; 892 break; 893 case AMDGPU_INFO_SENSOR_GPU_TEMP: 894 /* get temperature in millidegrees C */ 895 if (amdgpu_dpm_read_sensor(adev, 896 AMDGPU_PP_SENSOR_GPU_TEMP, 897 (void *)&ui32, &ui32_size)) { 898 return -EINVAL; 899 } 900 break; 901 case AMDGPU_INFO_SENSOR_GPU_LOAD: 902 /* get GPU load */ 903 if (amdgpu_dpm_read_sensor(adev, 904 AMDGPU_PP_SENSOR_GPU_LOAD, 905 (void *)&ui32, &ui32_size)) { 906 return -EINVAL; 907 } 908 break; 909 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 910 /* get average GPU power */ 911 if (amdgpu_dpm_read_sensor(adev, 912 AMDGPU_PP_SENSOR_GPU_POWER, 913 (void *)&ui32, &ui32_size)) { 914 return -EINVAL; 915 } 916 ui32 >>= 8; 917 break; 918 case AMDGPU_INFO_SENSOR_VDDNB: 919 /* get VDDNB in millivolts */ 920 if (amdgpu_dpm_read_sensor(adev, 921 AMDGPU_PP_SENSOR_VDDNB, 922 (void *)&ui32, &ui32_size)) { 923 return -EINVAL; 924 } 925 break; 926 case AMDGPU_INFO_SENSOR_VDDGFX: 927 /* get VDDGFX in millivolts */ 928 if (amdgpu_dpm_read_sensor(adev, 929 AMDGPU_PP_SENSOR_VDDGFX, 930 (void *)&ui32, &ui32_size)) { 931 return -EINVAL; 932 } 933 break; 934 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 935 /* get stable pstate sclk in Mhz */ 936 if (amdgpu_dpm_read_sensor(adev, 937 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 938 (void *)&ui32, &ui32_size)) { 939 return -EINVAL; 940 } 941 ui32 /= 100; 942 break; 943 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 944 /* get stable pstate mclk in Mhz */ 945 if (amdgpu_dpm_read_sensor(adev, 946 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 947 (void *)&ui32, &ui32_size)) { 948 return -EINVAL; 949 } 950 ui32 /= 100; 951 break; 952 default: 953 DRM_DEBUG_KMS("Invalid request %d\n", 954 info->sensor_info.type); 955 return -EINVAL; 956 } 957 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 958 } 959 case AMDGPU_INFO_VRAM_LOST_COUNTER: 960 ui32 = atomic_read(&adev->vram_lost_counter); 961 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 962 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 963 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 964 uint64_t ras_mask; 965 966 if (!ras) 967 return -EINVAL; 968 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 969 970 return copy_to_user(out, &ras_mask, 971 min_t(u64, size, sizeof(ras_mask))) ? 972 -EFAULT : 0; 973 } 974 default: 975 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 976 return -EINVAL; 977 } 978 return 0; 979 } 980 981 982 /* 983 * Outdated mess for old drm with Xorg being in charge (void function now). 984 */ 985 /** 986 * amdgpu_driver_lastclose_kms - drm callback for last close 987 * 988 * @dev: drm dev pointer 989 * 990 * Switch vga_switcheroo state after last close (all asics). 991 */ 992 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 993 { 994 drm_fb_helper_lastclose(dev); 995 vga_switcheroo_process_delayed_switch(); 996 } 997 998 /** 999 * amdgpu_driver_open_kms - drm callback for open 1000 * 1001 * @dev: drm dev pointer 1002 * @file_priv: drm file 1003 * 1004 * On device open, init vm on cayman+ (all asics). 1005 * Returns 0 on success, error on failure. 1006 */ 1007 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1008 { 1009 struct amdgpu_device *adev = drm_to_adev(dev); 1010 struct amdgpu_fpriv *fpriv; 1011 int r, pasid; 1012 1013 /* Ensure IB tests are run on ring */ 1014 flush_delayed_work(&adev->delayed_init_work); 1015 1016 1017 if (amdgpu_ras_intr_triggered()) { 1018 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1019 return -EHWPOISON; 1020 } 1021 1022 file_priv->driver_priv = NULL; 1023 1024 r = pm_runtime_get_sync(dev->dev); 1025 if (r < 0) 1026 goto pm_put; 1027 1028 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1029 if (unlikely(!fpriv)) { 1030 r = -ENOMEM; 1031 goto out_suspend; 1032 } 1033 1034 pasid = amdgpu_pasid_alloc(16); 1035 if (pasid < 0) { 1036 dev_warn(adev->dev, "No more PASIDs available!"); 1037 pasid = 0; 1038 } 1039 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1040 if (r) 1041 goto error_pasid; 1042 1043 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1044 if (!fpriv->prt_va) { 1045 r = -ENOMEM; 1046 goto error_vm; 1047 } 1048 1049 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1050 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1051 1052 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1053 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1054 if (r) 1055 goto error_vm; 1056 } 1057 1058 mutex_init(&fpriv->bo_list_lock); 1059 idr_init(&fpriv->bo_list_handles); 1060 1061 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1062 1063 file_priv->driver_priv = fpriv; 1064 goto out_suspend; 1065 1066 error_vm: 1067 amdgpu_vm_fini(adev, &fpriv->vm); 1068 1069 error_pasid: 1070 if (pasid) 1071 amdgpu_pasid_free(pasid); 1072 1073 kfree(fpriv); 1074 1075 out_suspend: 1076 pm_runtime_mark_last_busy(dev->dev); 1077 pm_put: 1078 pm_runtime_put_autosuspend(dev->dev); 1079 1080 return r; 1081 } 1082 1083 /** 1084 * amdgpu_driver_postclose_kms - drm callback for post close 1085 * 1086 * @dev: drm dev pointer 1087 * @file_priv: drm file 1088 * 1089 * On device post close, tear down vm on cayman+ (all asics). 1090 */ 1091 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1092 struct drm_file *file_priv) 1093 { 1094 struct amdgpu_device *adev = drm_to_adev(dev); 1095 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1096 struct amdgpu_bo_list *list; 1097 struct amdgpu_bo *pd; 1098 unsigned int pasid; 1099 int handle; 1100 1101 if (!fpriv) 1102 return; 1103 1104 pm_runtime_get_sync(dev->dev); 1105 1106 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1107 amdgpu_uvd_free_handles(adev, file_priv); 1108 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1109 amdgpu_vce_free_handles(adev, file_priv); 1110 1111 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1112 1113 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1114 /* TODO: how to handle reserve failure */ 1115 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1116 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1117 fpriv->csa_va = NULL; 1118 amdgpu_bo_unreserve(adev->virt.csa_obj); 1119 } 1120 1121 pasid = fpriv->vm.pasid; 1122 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1123 1124 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1125 amdgpu_vm_fini(adev, &fpriv->vm); 1126 1127 if (pasid) 1128 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1129 amdgpu_bo_unref(&pd); 1130 1131 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1132 amdgpu_bo_list_put(list); 1133 1134 idr_destroy(&fpriv->bo_list_handles); 1135 mutex_destroy(&fpriv->bo_list_lock); 1136 1137 kfree(fpriv); 1138 file_priv->driver_priv = NULL; 1139 1140 pm_runtime_mark_last_busy(dev->dev); 1141 pm_runtime_put_autosuspend(dev->dev); 1142 } 1143 1144 /* 1145 * VBlank related functions. 1146 */ 1147 /** 1148 * amdgpu_get_vblank_counter_kms - get frame count 1149 * 1150 * @crtc: crtc to get the frame count from 1151 * 1152 * Gets the frame count on the requested crtc (all asics). 1153 * Returns frame count on success, -EINVAL on failure. 1154 */ 1155 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1156 { 1157 struct drm_device *dev = crtc->dev; 1158 unsigned int pipe = crtc->index; 1159 struct amdgpu_device *adev = drm_to_adev(dev); 1160 int vpos, hpos, stat; 1161 u32 count; 1162 1163 if (pipe >= adev->mode_info.num_crtc) { 1164 DRM_ERROR("Invalid crtc %u\n", pipe); 1165 return -EINVAL; 1166 } 1167 1168 /* The hw increments its frame counter at start of vsync, not at start 1169 * of vblank, as is required by DRM core vblank counter handling. 1170 * Cook the hw count here to make it appear to the caller as if it 1171 * incremented at start of vblank. We measure distance to start of 1172 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1173 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1174 * result by 1 to give the proper appearance to caller. 1175 */ 1176 if (adev->mode_info.crtcs[pipe]) { 1177 /* Repeat readout if needed to provide stable result if 1178 * we cross start of vsync during the queries. 1179 */ 1180 do { 1181 count = amdgpu_display_vblank_get_counter(adev, pipe); 1182 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1183 * vpos as distance to start of vblank, instead of 1184 * regular vertical scanout pos. 1185 */ 1186 stat = amdgpu_display_get_crtc_scanoutpos( 1187 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1188 &vpos, &hpos, NULL, NULL, 1189 &adev->mode_info.crtcs[pipe]->base.hwmode); 1190 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1191 1192 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1193 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1194 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1195 } else { 1196 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1197 pipe, vpos); 1198 1199 /* Bump counter if we are at >= leading edge of vblank, 1200 * but before vsync where vpos would turn negative and 1201 * the hw counter really increments. 1202 */ 1203 if (vpos >= 0) 1204 count++; 1205 } 1206 } else { 1207 /* Fallback to use value as is. */ 1208 count = amdgpu_display_vblank_get_counter(adev, pipe); 1209 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1210 } 1211 1212 return count; 1213 } 1214 1215 /** 1216 * amdgpu_enable_vblank_kms - enable vblank interrupt 1217 * 1218 * @crtc: crtc to enable vblank interrupt for 1219 * 1220 * Enable the interrupt on the requested crtc (all asics). 1221 * Returns 0 on success, -EINVAL on failure. 1222 */ 1223 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1224 { 1225 struct drm_device *dev = crtc->dev; 1226 unsigned int pipe = crtc->index; 1227 struct amdgpu_device *adev = drm_to_adev(dev); 1228 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1229 1230 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1231 } 1232 1233 /** 1234 * amdgpu_disable_vblank_kms - disable vblank interrupt 1235 * 1236 * @crtc: crtc to disable vblank interrupt for 1237 * 1238 * Disable the interrupt on the requested crtc (all asics). 1239 */ 1240 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1241 { 1242 struct drm_device *dev = crtc->dev; 1243 unsigned int pipe = crtc->index; 1244 struct amdgpu_device *adev = drm_to_adev(dev); 1245 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1246 1247 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1248 } 1249 1250 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1251 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1252 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1253 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1254 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1255 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1256 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1257 /* KMS */ 1258 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1259 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1260 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1261 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1262 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1263 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1264 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1265 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1266 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1267 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1268 }; 1269 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1270 1271 /* 1272 * Debugfs info 1273 */ 1274 #if defined(CONFIG_DEBUG_FS) 1275 1276 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1277 { 1278 struct drm_info_node *node = (struct drm_info_node *) m->private; 1279 struct drm_device *dev = node->minor->dev; 1280 struct amdgpu_device *adev = drm_to_adev(dev); 1281 struct drm_amdgpu_info_firmware fw_info; 1282 struct drm_amdgpu_query_fw query_fw; 1283 struct atom_context *ctx = adev->mode_info.atom_context; 1284 int ret, i; 1285 1286 /* VCE */ 1287 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1288 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1289 if (ret) 1290 return ret; 1291 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1292 fw_info.feature, fw_info.ver); 1293 1294 /* UVD */ 1295 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1296 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1297 if (ret) 1298 return ret; 1299 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1300 fw_info.feature, fw_info.ver); 1301 1302 /* GMC */ 1303 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1304 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1305 if (ret) 1306 return ret; 1307 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1308 fw_info.feature, fw_info.ver); 1309 1310 /* ME */ 1311 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1312 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1313 if (ret) 1314 return ret; 1315 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1316 fw_info.feature, fw_info.ver); 1317 1318 /* PFP */ 1319 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1320 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1321 if (ret) 1322 return ret; 1323 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1324 fw_info.feature, fw_info.ver); 1325 1326 /* CE */ 1327 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1328 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1329 if (ret) 1330 return ret; 1331 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1332 fw_info.feature, fw_info.ver); 1333 1334 /* RLC */ 1335 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1336 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1337 if (ret) 1338 return ret; 1339 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1340 fw_info.feature, fw_info.ver); 1341 1342 /* RLC SAVE RESTORE LIST CNTL */ 1343 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1344 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1345 if (ret) 1346 return ret; 1347 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1348 fw_info.feature, fw_info.ver); 1349 1350 /* RLC SAVE RESTORE LIST GPM MEM */ 1351 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1352 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1353 if (ret) 1354 return ret; 1355 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1356 fw_info.feature, fw_info.ver); 1357 1358 /* RLC SAVE RESTORE LIST SRM MEM */ 1359 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1360 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1361 if (ret) 1362 return ret; 1363 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1364 fw_info.feature, fw_info.ver); 1365 1366 /* MEC */ 1367 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1368 query_fw.index = 0; 1369 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1370 if (ret) 1371 return ret; 1372 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1373 fw_info.feature, fw_info.ver); 1374 1375 /* MEC2 */ 1376 if (adev->gfx.mec2_fw) { 1377 query_fw.index = 1; 1378 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1379 if (ret) 1380 return ret; 1381 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1382 fw_info.feature, fw_info.ver); 1383 } 1384 1385 /* PSP SOS */ 1386 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1387 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1388 if (ret) 1389 return ret; 1390 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1391 fw_info.feature, fw_info.ver); 1392 1393 1394 /* PSP ASD */ 1395 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1396 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1397 if (ret) 1398 return ret; 1399 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1400 fw_info.feature, fw_info.ver); 1401 1402 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1403 for (i = 0; i < 4; i++) { 1404 query_fw.index = i; 1405 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1406 if (ret) 1407 continue; 1408 switch (query_fw.index) { 1409 case 0: 1410 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1411 "RAS", fw_info.feature, fw_info.ver); 1412 break; 1413 case 1: 1414 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1415 "XGMI", fw_info.feature, fw_info.ver); 1416 break; 1417 case 2: 1418 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1419 "HDCP", fw_info.feature, fw_info.ver); 1420 break; 1421 case 3: 1422 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1423 "DTM", fw_info.feature, fw_info.ver); 1424 break; 1425 default: 1426 return -EINVAL; 1427 } 1428 } 1429 1430 /* SMC */ 1431 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1432 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1433 if (ret) 1434 return ret; 1435 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1436 fw_info.feature, fw_info.ver); 1437 1438 /* SDMA */ 1439 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1440 for (i = 0; i < adev->sdma.num_instances; i++) { 1441 query_fw.index = i; 1442 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1443 if (ret) 1444 return ret; 1445 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1446 i, fw_info.feature, fw_info.ver); 1447 } 1448 1449 /* VCN */ 1450 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1451 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1452 if (ret) 1453 return ret; 1454 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1455 fw_info.feature, fw_info.ver); 1456 1457 /* DMCU */ 1458 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1459 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1460 if (ret) 1461 return ret; 1462 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1463 fw_info.feature, fw_info.ver); 1464 1465 /* DMCUB */ 1466 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1467 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1468 if (ret) 1469 return ret; 1470 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1471 fw_info.feature, fw_info.ver); 1472 1473 /* TOC */ 1474 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1475 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1476 if (ret) 1477 return ret; 1478 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1479 fw_info.feature, fw_info.ver); 1480 1481 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1482 1483 return 0; 1484 } 1485 1486 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1487 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1488 }; 1489 #endif 1490 1491 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1492 { 1493 #if defined(CONFIG_DEBUG_FS) 1494 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1495 ARRAY_SIZE(amdgpu_firmware_info_list)); 1496 #else 1497 return 0; 1498 #endif 1499 } 1500