1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (adev->runpm) { 91 pm_runtime_get_sync(dev->dev); 92 pm_runtime_forbid(dev->dev); 93 } 94 95 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 96 DRM_WARN("smart shift update failed\n"); 97 98 amdgpu_acpi_fini(adev); 99 amdgpu_device_fini_hw(adev); 100 } 101 102 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 103 { 104 struct amdgpu_gpu_instance *gpu_instance; 105 106 mutex_lock(&mgpu_info.mutex); 107 108 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 109 DRM_ERROR("Cannot register more gpu instance\n"); 110 mutex_unlock(&mgpu_info.mutex); 111 return; 112 } 113 114 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 115 gpu_instance->adev = adev; 116 gpu_instance->mgpu_fan_enabled = 0; 117 118 mgpu_info.num_gpu++; 119 if (adev->flags & AMD_IS_APU) 120 mgpu_info.num_apu++; 121 else 122 mgpu_info.num_dgpu++; 123 124 mutex_unlock(&mgpu_info.mutex); 125 } 126 127 static void amdgpu_get_audio_func(struct amdgpu_device *adev) 128 { 129 struct pci_dev *p = NULL; 130 131 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 132 adev->pdev->bus->number, 1); 133 if (p) { 134 pm_runtime_get_sync(&p->dev); 135 136 pm_runtime_mark_last_busy(&p->dev); 137 pm_runtime_put_autosuspend(&p->dev); 138 139 pci_dev_put(p); 140 } 141 } 142 143 /** 144 * amdgpu_driver_load_kms - Main load function for KMS. 145 * 146 * @adev: pointer to struct amdgpu_device 147 * @flags: device flags 148 * 149 * This is the main load function for KMS (all asics). 150 * Returns 0 on success, error on failure. 151 */ 152 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 153 { 154 struct drm_device *dev; 155 struct pci_dev *parent; 156 int r, acpi_status; 157 158 dev = adev_to_drm(adev); 159 160 if (amdgpu_has_atpx() && 161 (amdgpu_is_atpx_hybrid() || 162 amdgpu_has_atpx_dgpu_power_cntl()) && 163 ((flags & AMD_IS_APU) == 0) && 164 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) 165 flags |= AMD_IS_PX; 166 167 parent = pci_upstream_bridge(adev->pdev); 168 adev->has_pr3 = parent ? pci_pr3_present(parent) : false; 169 170 /* amdgpu_device_init should report only fatal error 171 * like memory allocation failure or iomapping failure, 172 * or memory manager initialization failure, it must 173 * properly initialize the GPU MC controller and permit 174 * VRAM allocation 175 */ 176 r = amdgpu_device_init(adev, flags); 177 if (r) { 178 dev_err(dev->dev, "Fatal error during GPU init\n"); 179 goto out; 180 } 181 182 if (amdgpu_device_supports_px(dev) && 183 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 184 adev->runpm = true; 185 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 186 } else if (amdgpu_device_supports_boco(dev) && 187 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 188 adev->runpm = true; 189 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 190 } else if (amdgpu_device_supports_baco(dev) && 191 (amdgpu_runtime_pm != 0)) { 192 switch (adev->asic_type) { 193 case CHIP_VEGA20: 194 case CHIP_ARCTURUS: 195 /* enable runpm if runpm=1 */ 196 if (amdgpu_runtime_pm > 0) 197 adev->runpm = true; 198 break; 199 case CHIP_VEGA10: 200 /* turn runpm on if noretry=0 */ 201 if (!adev->gmc.noretry) 202 adev->runpm = true; 203 break; 204 default: 205 /* enable runpm on CI+ */ 206 adev->runpm = true; 207 break; 208 } 209 if (adev->runpm) 210 dev_info(adev->dev, "Using BACO for runtime pm\n"); 211 } 212 213 /* Call ACPI methods: require modeset init 214 * but failure is not fatal 215 */ 216 217 acpi_status = amdgpu_acpi_init(adev); 218 if (acpi_status) 219 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 220 221 if (adev->runpm) { 222 /* only need to skip on ATPX */ 223 if (amdgpu_device_supports_px(dev)) 224 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 225 /* we want direct complete for BOCO */ 226 if (amdgpu_device_supports_boco(dev)) 227 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE | 228 DPM_FLAG_SMART_SUSPEND | 229 DPM_FLAG_MAY_SKIP_RESUME); 230 pm_runtime_use_autosuspend(dev->dev); 231 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 232 233 pm_runtime_allow(dev->dev); 234 235 pm_runtime_mark_last_busy(dev->dev); 236 pm_runtime_put_autosuspend(dev->dev); 237 238 /* 239 * For runpm implemented via BACO, PMFW will handle the 240 * timing for BACO in and out: 241 * - put ASIC into BACO state only when both video and 242 * audio functions are in D3 state. 243 * - pull ASIC out of BACO state when either video or 244 * audio function is in D0 state. 245 * Also, at startup, PMFW assumes both functions are in 246 * D0 state. 247 * 248 * So if snd driver was loaded prior to amdgpu driver 249 * and audio function was put into D3 state, there will 250 * be no PMFW-aware D-state transition(D0->D3) on runpm 251 * suspend. Thus the BACO will be not correctly kicked in. 252 * 253 * Via amdgpu_get_audio_func(), the audio dev is put 254 * into D0 state. Then there will be a PMFW-aware D-state 255 * transition(D0->D3) on runpm suspend. 256 */ 257 if (amdgpu_device_supports_baco(dev) && 258 !(adev->flags & AMD_IS_APU) && 259 (adev->asic_type >= CHIP_NAVI10)) 260 amdgpu_get_audio_func(adev); 261 } 262 263 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 264 DRM_WARN("smart shift update failed\n"); 265 266 out: 267 if (r) { 268 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 269 if (adev->rmmio && adev->runpm) 270 pm_runtime_put_noidle(dev->dev); 271 amdgpu_driver_unload_kms(dev); 272 } 273 274 return r; 275 } 276 277 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 278 struct drm_amdgpu_query_fw *query_fw, 279 struct amdgpu_device *adev) 280 { 281 switch (query_fw->fw_type) { 282 case AMDGPU_INFO_FW_VCE: 283 fw_info->ver = adev->vce.fw_version; 284 fw_info->feature = adev->vce.fb_version; 285 break; 286 case AMDGPU_INFO_FW_UVD: 287 fw_info->ver = adev->uvd.fw_version; 288 fw_info->feature = 0; 289 break; 290 case AMDGPU_INFO_FW_VCN: 291 fw_info->ver = adev->vcn.fw_version; 292 fw_info->feature = 0; 293 break; 294 case AMDGPU_INFO_FW_GMC: 295 fw_info->ver = adev->gmc.fw_version; 296 fw_info->feature = 0; 297 break; 298 case AMDGPU_INFO_FW_GFX_ME: 299 fw_info->ver = adev->gfx.me_fw_version; 300 fw_info->feature = adev->gfx.me_feature_version; 301 break; 302 case AMDGPU_INFO_FW_GFX_PFP: 303 fw_info->ver = adev->gfx.pfp_fw_version; 304 fw_info->feature = adev->gfx.pfp_feature_version; 305 break; 306 case AMDGPU_INFO_FW_GFX_CE: 307 fw_info->ver = adev->gfx.ce_fw_version; 308 fw_info->feature = adev->gfx.ce_feature_version; 309 break; 310 case AMDGPU_INFO_FW_GFX_RLC: 311 fw_info->ver = adev->gfx.rlc_fw_version; 312 fw_info->feature = adev->gfx.rlc_feature_version; 313 break; 314 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 315 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 316 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 317 break; 318 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 319 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 320 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 321 break; 322 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 323 fw_info->ver = adev->gfx.rlc_srls_fw_version; 324 fw_info->feature = adev->gfx.rlc_srls_feature_version; 325 break; 326 case AMDGPU_INFO_FW_GFX_MEC: 327 if (query_fw->index == 0) { 328 fw_info->ver = adev->gfx.mec_fw_version; 329 fw_info->feature = adev->gfx.mec_feature_version; 330 } else if (query_fw->index == 1) { 331 fw_info->ver = adev->gfx.mec2_fw_version; 332 fw_info->feature = adev->gfx.mec2_feature_version; 333 } else 334 return -EINVAL; 335 break; 336 case AMDGPU_INFO_FW_SMC: 337 fw_info->ver = adev->pm.fw_version; 338 fw_info->feature = 0; 339 break; 340 case AMDGPU_INFO_FW_TA: 341 switch (query_fw->index) { 342 case TA_FW_TYPE_PSP_XGMI: 343 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 344 fw_info->feature = adev->psp.xgmi_context.context 345 .bin_desc.feature_version; 346 break; 347 case TA_FW_TYPE_PSP_RAS: 348 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 349 fw_info->feature = adev->psp.ras_context.context 350 .bin_desc.feature_version; 351 break; 352 case TA_FW_TYPE_PSP_HDCP: 353 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 354 fw_info->feature = adev->psp.hdcp_context.context 355 .bin_desc.feature_version; 356 break; 357 case TA_FW_TYPE_PSP_DTM: 358 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 359 fw_info->feature = adev->psp.dtm_context.context 360 .bin_desc.feature_version; 361 break; 362 case TA_FW_TYPE_PSP_RAP: 363 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 364 fw_info->feature = adev->psp.rap_context.context 365 .bin_desc.feature_version; 366 break; 367 case TA_FW_TYPE_PSP_SECUREDISPLAY: 368 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 369 fw_info->feature = 370 adev->psp.securedisplay_context.context.bin_desc 371 .feature_version; 372 break; 373 default: 374 return -EINVAL; 375 } 376 break; 377 case AMDGPU_INFO_FW_SDMA: 378 if (query_fw->index >= adev->sdma.num_instances) 379 return -EINVAL; 380 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 381 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 382 break; 383 case AMDGPU_INFO_FW_SOS: 384 fw_info->ver = adev->psp.sos.fw_version; 385 fw_info->feature = adev->psp.sos.feature_version; 386 break; 387 case AMDGPU_INFO_FW_ASD: 388 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 389 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 390 break; 391 case AMDGPU_INFO_FW_DMCU: 392 fw_info->ver = adev->dm.dmcu_fw_version; 393 fw_info->feature = 0; 394 break; 395 case AMDGPU_INFO_FW_DMCUB: 396 fw_info->ver = adev->dm.dmcub_fw_version; 397 fw_info->feature = 0; 398 break; 399 case AMDGPU_INFO_FW_TOC: 400 fw_info->ver = adev->psp.toc.fw_version; 401 fw_info->feature = adev->psp.toc.feature_version; 402 break; 403 default: 404 return -EINVAL; 405 } 406 return 0; 407 } 408 409 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 410 struct drm_amdgpu_info *info, 411 struct drm_amdgpu_info_hw_ip *result) 412 { 413 uint32_t ib_start_alignment = 0; 414 uint32_t ib_size_alignment = 0; 415 enum amd_ip_block_type type; 416 unsigned int num_rings = 0; 417 unsigned int i, j; 418 419 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 420 return -EINVAL; 421 422 switch (info->query_hw_ip.type) { 423 case AMDGPU_HW_IP_GFX: 424 type = AMD_IP_BLOCK_TYPE_GFX; 425 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 426 if (adev->gfx.gfx_ring[i].sched.ready) 427 ++num_rings; 428 ib_start_alignment = 32; 429 ib_size_alignment = 32; 430 break; 431 case AMDGPU_HW_IP_COMPUTE: 432 type = AMD_IP_BLOCK_TYPE_GFX; 433 for (i = 0; i < adev->gfx.num_compute_rings; i++) 434 if (adev->gfx.compute_ring[i].sched.ready) 435 ++num_rings; 436 ib_start_alignment = 32; 437 ib_size_alignment = 32; 438 break; 439 case AMDGPU_HW_IP_DMA: 440 type = AMD_IP_BLOCK_TYPE_SDMA; 441 for (i = 0; i < adev->sdma.num_instances; i++) 442 if (adev->sdma.instance[i].ring.sched.ready) 443 ++num_rings; 444 ib_start_alignment = 256; 445 ib_size_alignment = 4; 446 break; 447 case AMDGPU_HW_IP_UVD: 448 type = AMD_IP_BLOCK_TYPE_UVD; 449 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 450 if (adev->uvd.harvest_config & (1 << i)) 451 continue; 452 453 if (adev->uvd.inst[i].ring.sched.ready) 454 ++num_rings; 455 } 456 ib_start_alignment = 64; 457 ib_size_alignment = 64; 458 break; 459 case AMDGPU_HW_IP_VCE: 460 type = AMD_IP_BLOCK_TYPE_VCE; 461 for (i = 0; i < adev->vce.num_rings; i++) 462 if (adev->vce.ring[i].sched.ready) 463 ++num_rings; 464 ib_start_alignment = 4; 465 ib_size_alignment = 1; 466 break; 467 case AMDGPU_HW_IP_UVD_ENC: 468 type = AMD_IP_BLOCK_TYPE_UVD; 469 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 470 if (adev->uvd.harvest_config & (1 << i)) 471 continue; 472 473 for (j = 0; j < adev->uvd.num_enc_rings; j++) 474 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 475 ++num_rings; 476 } 477 ib_start_alignment = 64; 478 ib_size_alignment = 64; 479 break; 480 case AMDGPU_HW_IP_VCN_DEC: 481 type = AMD_IP_BLOCK_TYPE_VCN; 482 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 483 if (adev->uvd.harvest_config & (1 << i)) 484 continue; 485 486 if (adev->vcn.inst[i].ring_dec.sched.ready) 487 ++num_rings; 488 } 489 ib_start_alignment = 16; 490 ib_size_alignment = 16; 491 break; 492 case AMDGPU_HW_IP_VCN_ENC: 493 type = AMD_IP_BLOCK_TYPE_VCN; 494 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 495 if (adev->uvd.harvest_config & (1 << i)) 496 continue; 497 498 for (j = 0; j < adev->vcn.num_enc_rings; j++) 499 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 500 ++num_rings; 501 } 502 ib_start_alignment = 64; 503 ib_size_alignment = 1; 504 break; 505 case AMDGPU_HW_IP_VCN_JPEG: 506 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 507 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 508 509 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 510 if (adev->jpeg.harvest_config & (1 << i)) 511 continue; 512 513 if (adev->jpeg.inst[i].ring_dec.sched.ready) 514 ++num_rings; 515 } 516 ib_start_alignment = 16; 517 ib_size_alignment = 16; 518 break; 519 default: 520 return -EINVAL; 521 } 522 523 for (i = 0; i < adev->num_ip_blocks; i++) 524 if (adev->ip_blocks[i].version->type == type && 525 adev->ip_blocks[i].status.valid) 526 break; 527 528 if (i == adev->num_ip_blocks) 529 return 0; 530 531 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 532 num_rings); 533 534 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 535 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 536 result->capabilities_flags = 0; 537 result->available_rings = (1 << num_rings) - 1; 538 result->ib_start_alignment = ib_start_alignment; 539 result->ib_size_alignment = ib_size_alignment; 540 return 0; 541 } 542 543 /* 544 * Userspace get information ioctl 545 */ 546 /** 547 * amdgpu_info_ioctl - answer a device specific request. 548 * 549 * @dev: drm device pointer 550 * @data: request object 551 * @filp: drm filp 552 * 553 * This function is used to pass device specific parameters to the userspace 554 * drivers. Examples include: pci device id, pipeline parms, tiling params, 555 * etc. (all asics). 556 * Returns 0 on success, -EINVAL on failure. 557 */ 558 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 559 { 560 struct amdgpu_device *adev = drm_to_adev(dev); 561 struct drm_amdgpu_info *info = data; 562 struct amdgpu_mode_info *minfo = &adev->mode_info; 563 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 564 uint32_t size = info->return_size; 565 struct drm_crtc *crtc; 566 uint32_t ui32 = 0; 567 uint64_t ui64 = 0; 568 int i, found; 569 int ui32_size = sizeof(ui32); 570 571 if (!info->return_size || !info->return_pointer) 572 return -EINVAL; 573 574 switch (info->query) { 575 case AMDGPU_INFO_ACCEL_WORKING: 576 ui32 = adev->accel_working; 577 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 578 case AMDGPU_INFO_CRTC_FROM_ID: 579 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 580 crtc = (struct drm_crtc *)minfo->crtcs[i]; 581 if (crtc && crtc->base.id == info->mode_crtc.id) { 582 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 583 ui32 = amdgpu_crtc->crtc_id; 584 found = 1; 585 break; 586 } 587 } 588 if (!found) { 589 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 590 return -EINVAL; 591 } 592 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 593 case AMDGPU_INFO_HW_IP_INFO: { 594 struct drm_amdgpu_info_hw_ip ip = {}; 595 int ret; 596 597 ret = amdgpu_hw_ip_info(adev, info, &ip); 598 if (ret) 599 return ret; 600 601 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 602 return ret ? -EFAULT : 0; 603 } 604 case AMDGPU_INFO_HW_IP_COUNT: { 605 enum amd_ip_block_type type; 606 uint32_t count = 0; 607 608 switch (info->query_hw_ip.type) { 609 case AMDGPU_HW_IP_GFX: 610 type = AMD_IP_BLOCK_TYPE_GFX; 611 break; 612 case AMDGPU_HW_IP_COMPUTE: 613 type = AMD_IP_BLOCK_TYPE_GFX; 614 break; 615 case AMDGPU_HW_IP_DMA: 616 type = AMD_IP_BLOCK_TYPE_SDMA; 617 break; 618 case AMDGPU_HW_IP_UVD: 619 type = AMD_IP_BLOCK_TYPE_UVD; 620 break; 621 case AMDGPU_HW_IP_VCE: 622 type = AMD_IP_BLOCK_TYPE_VCE; 623 break; 624 case AMDGPU_HW_IP_UVD_ENC: 625 type = AMD_IP_BLOCK_TYPE_UVD; 626 break; 627 case AMDGPU_HW_IP_VCN_DEC: 628 case AMDGPU_HW_IP_VCN_ENC: 629 type = AMD_IP_BLOCK_TYPE_VCN; 630 break; 631 case AMDGPU_HW_IP_VCN_JPEG: 632 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 633 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 634 break; 635 default: 636 return -EINVAL; 637 } 638 639 for (i = 0; i < adev->num_ip_blocks; i++) 640 if (adev->ip_blocks[i].version->type == type && 641 adev->ip_blocks[i].status.valid && 642 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 643 count++; 644 645 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 646 } 647 case AMDGPU_INFO_TIMESTAMP: 648 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 649 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 650 case AMDGPU_INFO_FW_VERSION: { 651 struct drm_amdgpu_info_firmware fw_info; 652 int ret; 653 654 /* We only support one instance of each IP block right now. */ 655 if (info->query_fw.ip_instance != 0) 656 return -EINVAL; 657 658 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 659 if (ret) 660 return ret; 661 662 return copy_to_user(out, &fw_info, 663 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 664 } 665 case AMDGPU_INFO_NUM_BYTES_MOVED: 666 ui64 = atomic64_read(&adev->num_bytes_moved); 667 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 668 case AMDGPU_INFO_NUM_EVICTIONS: 669 ui64 = atomic64_read(&adev->num_evictions); 670 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 671 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 672 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 673 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 674 case AMDGPU_INFO_VRAM_USAGE: 675 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 676 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 677 case AMDGPU_INFO_VIS_VRAM_USAGE: 678 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 679 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 680 case AMDGPU_INFO_GTT_USAGE: 681 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 682 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 683 case AMDGPU_INFO_GDS_CONFIG: { 684 struct drm_amdgpu_info_gds gds_info; 685 686 memset(&gds_info, 0, sizeof(gds_info)); 687 gds_info.compute_partition_size = adev->gds.gds_size; 688 gds_info.gds_total_size = adev->gds.gds_size; 689 gds_info.gws_per_compute_partition = adev->gds.gws_size; 690 gds_info.oa_per_compute_partition = adev->gds.oa_size; 691 return copy_to_user(out, &gds_info, 692 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 693 } 694 case AMDGPU_INFO_VRAM_GTT: { 695 struct drm_amdgpu_info_vram_gtt vram_gtt; 696 697 vram_gtt.vram_size = adev->gmc.real_vram_size - 698 atomic64_read(&adev->vram_pin_size) - 699 AMDGPU_VM_RESERVED_VRAM; 700 vram_gtt.vram_cpu_accessible_size = 701 min(adev->gmc.visible_vram_size - 702 atomic64_read(&adev->visible_pin_size), 703 vram_gtt.vram_size); 704 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 705 vram_gtt.gtt_size *= PAGE_SIZE; 706 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 707 return copy_to_user(out, &vram_gtt, 708 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 709 } 710 case AMDGPU_INFO_MEMORY: { 711 struct drm_amdgpu_memory_info mem; 712 struct ttm_resource_manager *vram_man = 713 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 714 struct ttm_resource_manager *gtt_man = 715 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 716 memset(&mem, 0, sizeof(mem)); 717 mem.vram.total_heap_size = adev->gmc.real_vram_size; 718 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 719 atomic64_read(&adev->vram_pin_size) - 720 AMDGPU_VM_RESERVED_VRAM; 721 mem.vram.heap_usage = 722 amdgpu_vram_mgr_usage(vram_man); 723 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 724 725 mem.cpu_accessible_vram.total_heap_size = 726 adev->gmc.visible_vram_size; 727 mem.cpu_accessible_vram.usable_heap_size = 728 min(adev->gmc.visible_vram_size - 729 atomic64_read(&adev->visible_pin_size), 730 mem.vram.usable_heap_size); 731 mem.cpu_accessible_vram.heap_usage = 732 amdgpu_vram_mgr_vis_usage(vram_man); 733 mem.cpu_accessible_vram.max_allocation = 734 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 735 736 mem.gtt.total_heap_size = gtt_man->size; 737 mem.gtt.total_heap_size *= PAGE_SIZE; 738 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 739 atomic64_read(&adev->gart_pin_size); 740 mem.gtt.heap_usage = 741 amdgpu_gtt_mgr_usage(gtt_man); 742 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 743 744 return copy_to_user(out, &mem, 745 min((size_t)size, sizeof(mem))) 746 ? -EFAULT : 0; 747 } 748 case AMDGPU_INFO_READ_MMR_REG: { 749 unsigned n, alloc_size; 750 uint32_t *regs; 751 unsigned se_num = (info->read_mmr_reg.instance >> 752 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 753 AMDGPU_INFO_MMR_SE_INDEX_MASK; 754 unsigned sh_num = (info->read_mmr_reg.instance >> 755 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 756 AMDGPU_INFO_MMR_SH_INDEX_MASK; 757 758 /* set full masks if the userspace set all bits 759 * in the bitfields */ 760 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 761 se_num = 0xffffffff; 762 else if (se_num >= AMDGPU_GFX_MAX_SE) 763 return -EINVAL; 764 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 765 sh_num = 0xffffffff; 766 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 767 return -EINVAL; 768 769 if (info->read_mmr_reg.count > 128) 770 return -EINVAL; 771 772 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 773 if (!regs) 774 return -ENOMEM; 775 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 776 777 amdgpu_gfx_off_ctrl(adev, false); 778 for (i = 0; i < info->read_mmr_reg.count; i++) { 779 if (amdgpu_asic_read_register(adev, se_num, sh_num, 780 info->read_mmr_reg.dword_offset + i, 781 ®s[i])) { 782 DRM_DEBUG_KMS("unallowed offset %#x\n", 783 info->read_mmr_reg.dword_offset + i); 784 kfree(regs); 785 amdgpu_gfx_off_ctrl(adev, true); 786 return -EFAULT; 787 } 788 } 789 amdgpu_gfx_off_ctrl(adev, true); 790 n = copy_to_user(out, regs, min(size, alloc_size)); 791 kfree(regs); 792 return n ? -EFAULT : 0; 793 } 794 case AMDGPU_INFO_DEV_INFO: { 795 struct drm_amdgpu_info_device *dev_info; 796 uint64_t vm_size; 797 int ret; 798 799 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 800 if (!dev_info) 801 return -ENOMEM; 802 803 dev_info->device_id = adev->pdev->device; 804 dev_info->chip_rev = adev->rev_id; 805 dev_info->external_rev = adev->external_rev_id; 806 dev_info->pci_rev = adev->pdev->revision; 807 dev_info->family = adev->family; 808 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 809 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 810 /* return all clocks in KHz */ 811 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 812 if (adev->pm.dpm_enabled) { 813 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 814 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 815 } else { 816 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 817 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 818 } 819 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 820 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 821 adev->gfx.config.max_shader_engines; 822 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 823 dev_info->_pad = 0; 824 dev_info->ids_flags = 0; 825 if (adev->flags & AMD_IS_APU) 826 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 827 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 828 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 829 if (amdgpu_is_tmz(adev)) 830 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 831 832 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 833 vm_size -= AMDGPU_VA_RESERVED_SIZE; 834 835 /* Older VCE FW versions are buggy and can handle only 40bits */ 836 if (adev->vce.fw_version && 837 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 838 vm_size = min(vm_size, 1ULL << 40); 839 840 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 841 dev_info->virtual_address_max = 842 min(vm_size, AMDGPU_GMC_HOLE_START); 843 844 if (vm_size > AMDGPU_GMC_HOLE_START) { 845 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 846 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 847 } 848 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 849 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 850 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 851 dev_info->cu_active_number = adev->gfx.cu_info.number; 852 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 853 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 854 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 855 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 856 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 857 sizeof(adev->gfx.cu_info.bitmap)); 858 dev_info->vram_type = adev->gmc.vram_type; 859 dev_info->vram_bit_width = adev->gmc.vram_width; 860 dev_info->vce_harvest_config = adev->vce.harvest_config; 861 dev_info->gc_double_offchip_lds_buf = 862 adev->gfx.config.double_offchip_lds_buf; 863 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 864 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 865 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 866 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 867 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 868 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 869 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 870 871 if (adev->family >= AMDGPU_FAMILY_NV) 872 dev_info->pa_sc_tile_steering_override = 873 adev->gfx.config.pa_sc_tile_steering_override; 874 875 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 876 877 ret = copy_to_user(out, dev_info, 878 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 879 kfree(dev_info); 880 return ret; 881 } 882 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 883 unsigned i; 884 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 885 struct amd_vce_state *vce_state; 886 887 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 888 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 889 if (vce_state) { 890 vce_clk_table.entries[i].sclk = vce_state->sclk; 891 vce_clk_table.entries[i].mclk = vce_state->mclk; 892 vce_clk_table.entries[i].eclk = vce_state->evclk; 893 vce_clk_table.num_valid_entries++; 894 } 895 } 896 897 return copy_to_user(out, &vce_clk_table, 898 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 899 } 900 case AMDGPU_INFO_VBIOS: { 901 uint32_t bios_size = adev->bios_size; 902 903 switch (info->vbios_info.type) { 904 case AMDGPU_INFO_VBIOS_SIZE: 905 return copy_to_user(out, &bios_size, 906 min((size_t)size, sizeof(bios_size))) 907 ? -EFAULT : 0; 908 case AMDGPU_INFO_VBIOS_IMAGE: { 909 uint8_t *bios; 910 uint32_t bios_offset = info->vbios_info.offset; 911 912 if (bios_offset >= bios_size) 913 return -EINVAL; 914 915 bios = adev->bios + bios_offset; 916 return copy_to_user(out, bios, 917 min((size_t)size, (size_t)(bios_size - bios_offset))) 918 ? -EFAULT : 0; 919 } 920 case AMDGPU_INFO_VBIOS_INFO: { 921 struct drm_amdgpu_info_vbios vbios_info = {}; 922 struct atom_context *atom_context; 923 924 atom_context = adev->mode_info.atom_context; 925 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 926 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 927 vbios_info.version = atom_context->version; 928 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 929 sizeof(atom_context->vbios_ver_str)); 930 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 931 932 return copy_to_user(out, &vbios_info, 933 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 934 } 935 default: 936 DRM_DEBUG_KMS("Invalid request %d\n", 937 info->vbios_info.type); 938 return -EINVAL; 939 } 940 } 941 case AMDGPU_INFO_NUM_HANDLES: { 942 struct drm_amdgpu_info_num_handles handle; 943 944 switch (info->query_hw_ip.type) { 945 case AMDGPU_HW_IP_UVD: 946 /* Starting Polaris, we support unlimited UVD handles */ 947 if (adev->asic_type < CHIP_POLARIS10) { 948 handle.uvd_max_handles = adev->uvd.max_handles; 949 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 950 951 return copy_to_user(out, &handle, 952 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 953 } else { 954 return -ENODATA; 955 } 956 957 break; 958 default: 959 return -EINVAL; 960 } 961 } 962 case AMDGPU_INFO_SENSOR: { 963 if (!adev->pm.dpm_enabled) 964 return -ENOENT; 965 966 switch (info->sensor_info.type) { 967 case AMDGPU_INFO_SENSOR_GFX_SCLK: 968 /* get sclk in Mhz */ 969 if (amdgpu_dpm_read_sensor(adev, 970 AMDGPU_PP_SENSOR_GFX_SCLK, 971 (void *)&ui32, &ui32_size)) { 972 return -EINVAL; 973 } 974 ui32 /= 100; 975 break; 976 case AMDGPU_INFO_SENSOR_GFX_MCLK: 977 /* get mclk in Mhz */ 978 if (amdgpu_dpm_read_sensor(adev, 979 AMDGPU_PP_SENSOR_GFX_MCLK, 980 (void *)&ui32, &ui32_size)) { 981 return -EINVAL; 982 } 983 ui32 /= 100; 984 break; 985 case AMDGPU_INFO_SENSOR_GPU_TEMP: 986 /* get temperature in millidegrees C */ 987 if (amdgpu_dpm_read_sensor(adev, 988 AMDGPU_PP_SENSOR_GPU_TEMP, 989 (void *)&ui32, &ui32_size)) { 990 return -EINVAL; 991 } 992 break; 993 case AMDGPU_INFO_SENSOR_GPU_LOAD: 994 /* get GPU load */ 995 if (amdgpu_dpm_read_sensor(adev, 996 AMDGPU_PP_SENSOR_GPU_LOAD, 997 (void *)&ui32, &ui32_size)) { 998 return -EINVAL; 999 } 1000 break; 1001 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1002 /* get average GPU power */ 1003 if (amdgpu_dpm_read_sensor(adev, 1004 AMDGPU_PP_SENSOR_GPU_POWER, 1005 (void *)&ui32, &ui32_size)) { 1006 return -EINVAL; 1007 } 1008 ui32 >>= 8; 1009 break; 1010 case AMDGPU_INFO_SENSOR_VDDNB: 1011 /* get VDDNB in millivolts */ 1012 if (amdgpu_dpm_read_sensor(adev, 1013 AMDGPU_PP_SENSOR_VDDNB, 1014 (void *)&ui32, &ui32_size)) { 1015 return -EINVAL; 1016 } 1017 break; 1018 case AMDGPU_INFO_SENSOR_VDDGFX: 1019 /* get VDDGFX in millivolts */ 1020 if (amdgpu_dpm_read_sensor(adev, 1021 AMDGPU_PP_SENSOR_VDDGFX, 1022 (void *)&ui32, &ui32_size)) { 1023 return -EINVAL; 1024 } 1025 break; 1026 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1027 /* get stable pstate sclk in Mhz */ 1028 if (amdgpu_dpm_read_sensor(adev, 1029 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1030 (void *)&ui32, &ui32_size)) { 1031 return -EINVAL; 1032 } 1033 ui32 /= 100; 1034 break; 1035 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1036 /* get stable pstate mclk in Mhz */ 1037 if (amdgpu_dpm_read_sensor(adev, 1038 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1039 (void *)&ui32, &ui32_size)) { 1040 return -EINVAL; 1041 } 1042 ui32 /= 100; 1043 break; 1044 default: 1045 DRM_DEBUG_KMS("Invalid request %d\n", 1046 info->sensor_info.type); 1047 return -EINVAL; 1048 } 1049 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1050 } 1051 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1052 ui32 = atomic_read(&adev->vram_lost_counter); 1053 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1054 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1055 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1056 uint64_t ras_mask; 1057 1058 if (!ras) 1059 return -EINVAL; 1060 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1061 1062 return copy_to_user(out, &ras_mask, 1063 min_t(u64, size, sizeof(ras_mask))) ? 1064 -EFAULT : 0; 1065 } 1066 case AMDGPU_INFO_VIDEO_CAPS: { 1067 const struct amdgpu_video_codecs *codecs; 1068 struct drm_amdgpu_info_video_caps *caps; 1069 int r; 1070 1071 switch (info->video_cap.type) { 1072 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1073 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1074 if (r) 1075 return -EINVAL; 1076 break; 1077 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1078 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1079 if (r) 1080 return -EINVAL; 1081 break; 1082 default: 1083 DRM_DEBUG_KMS("Invalid request %d\n", 1084 info->video_cap.type); 1085 return -EINVAL; 1086 } 1087 1088 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1089 if (!caps) 1090 return -ENOMEM; 1091 1092 for (i = 0; i < codecs->codec_count; i++) { 1093 int idx = codecs->codec_array[i].codec_type; 1094 1095 switch (idx) { 1096 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1097 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1098 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1099 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1100 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1101 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1102 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1103 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1104 caps->codec_info[idx].valid = 1; 1105 caps->codec_info[idx].max_width = 1106 codecs->codec_array[i].max_width; 1107 caps->codec_info[idx].max_height = 1108 codecs->codec_array[i].max_height; 1109 caps->codec_info[idx].max_pixels_per_frame = 1110 codecs->codec_array[i].max_pixels_per_frame; 1111 caps->codec_info[idx].max_level = 1112 codecs->codec_array[i].max_level; 1113 break; 1114 default: 1115 break; 1116 } 1117 } 1118 r = copy_to_user(out, caps, 1119 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1120 kfree(caps); 1121 return r; 1122 } 1123 default: 1124 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1125 return -EINVAL; 1126 } 1127 return 0; 1128 } 1129 1130 1131 /* 1132 * Outdated mess for old drm with Xorg being in charge (void function now). 1133 */ 1134 /** 1135 * amdgpu_driver_lastclose_kms - drm callback for last close 1136 * 1137 * @dev: drm dev pointer 1138 * 1139 * Switch vga_switcheroo state after last close (all asics). 1140 */ 1141 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1142 { 1143 drm_fb_helper_lastclose(dev); 1144 vga_switcheroo_process_delayed_switch(); 1145 } 1146 1147 /** 1148 * amdgpu_driver_open_kms - drm callback for open 1149 * 1150 * @dev: drm dev pointer 1151 * @file_priv: drm file 1152 * 1153 * On device open, init vm on cayman+ (all asics). 1154 * Returns 0 on success, error on failure. 1155 */ 1156 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1157 { 1158 struct amdgpu_device *adev = drm_to_adev(dev); 1159 struct amdgpu_fpriv *fpriv; 1160 int r, pasid; 1161 1162 /* Ensure IB tests are run on ring */ 1163 flush_delayed_work(&adev->delayed_init_work); 1164 1165 1166 if (amdgpu_ras_intr_triggered()) { 1167 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1168 return -EHWPOISON; 1169 } 1170 1171 file_priv->driver_priv = NULL; 1172 1173 r = pm_runtime_get_sync(dev->dev); 1174 if (r < 0) 1175 goto pm_put; 1176 1177 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1178 if (unlikely(!fpriv)) { 1179 r = -ENOMEM; 1180 goto out_suspend; 1181 } 1182 1183 pasid = amdgpu_pasid_alloc(16); 1184 if (pasid < 0) { 1185 dev_warn(adev->dev, "No more PASIDs available!"); 1186 pasid = 0; 1187 } 1188 1189 r = amdgpu_vm_init(adev, &fpriv->vm); 1190 if (r) 1191 goto error_pasid; 1192 1193 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1194 if (r) 1195 goto error_vm; 1196 1197 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1198 if (!fpriv->prt_va) { 1199 r = -ENOMEM; 1200 goto error_vm; 1201 } 1202 1203 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1204 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1205 1206 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1207 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1208 if (r) 1209 goto error_vm; 1210 } 1211 1212 mutex_init(&fpriv->bo_list_lock); 1213 idr_init(&fpriv->bo_list_handles); 1214 1215 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1216 1217 file_priv->driver_priv = fpriv; 1218 goto out_suspend; 1219 1220 error_vm: 1221 amdgpu_vm_fini(adev, &fpriv->vm); 1222 1223 error_pasid: 1224 if (pasid) { 1225 amdgpu_pasid_free(pasid); 1226 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1227 } 1228 1229 kfree(fpriv); 1230 1231 out_suspend: 1232 pm_runtime_mark_last_busy(dev->dev); 1233 pm_put: 1234 pm_runtime_put_autosuspend(dev->dev); 1235 1236 return r; 1237 } 1238 1239 /** 1240 * amdgpu_driver_postclose_kms - drm callback for post close 1241 * 1242 * @dev: drm dev pointer 1243 * @file_priv: drm file 1244 * 1245 * On device post close, tear down vm on cayman+ (all asics). 1246 */ 1247 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1248 struct drm_file *file_priv) 1249 { 1250 struct amdgpu_device *adev = drm_to_adev(dev); 1251 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1252 struct amdgpu_bo_list *list; 1253 struct amdgpu_bo *pd; 1254 u32 pasid; 1255 int handle; 1256 1257 if (!fpriv) 1258 return; 1259 1260 pm_runtime_get_sync(dev->dev); 1261 1262 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1263 amdgpu_uvd_free_handles(adev, file_priv); 1264 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1265 amdgpu_vce_free_handles(adev, file_priv); 1266 1267 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1268 1269 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1270 /* TODO: how to handle reserve failure */ 1271 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1272 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1273 fpriv->csa_va = NULL; 1274 amdgpu_bo_unreserve(adev->virt.csa_obj); 1275 } 1276 1277 pasid = fpriv->vm.pasid; 1278 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1279 1280 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1281 amdgpu_vm_fini(adev, &fpriv->vm); 1282 1283 if (pasid) 1284 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1285 amdgpu_bo_unref(&pd); 1286 1287 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1288 amdgpu_bo_list_put(list); 1289 1290 idr_destroy(&fpriv->bo_list_handles); 1291 mutex_destroy(&fpriv->bo_list_lock); 1292 1293 kfree(fpriv); 1294 file_priv->driver_priv = NULL; 1295 1296 pm_runtime_mark_last_busy(dev->dev); 1297 pm_runtime_put_autosuspend(dev->dev); 1298 } 1299 1300 1301 void amdgpu_driver_release_kms(struct drm_device *dev) 1302 { 1303 struct amdgpu_device *adev = drm_to_adev(dev); 1304 1305 amdgpu_device_fini_sw(adev); 1306 pci_set_drvdata(adev->pdev, NULL); 1307 } 1308 1309 /* 1310 * VBlank related functions. 1311 */ 1312 /** 1313 * amdgpu_get_vblank_counter_kms - get frame count 1314 * 1315 * @crtc: crtc to get the frame count from 1316 * 1317 * Gets the frame count on the requested crtc (all asics). 1318 * Returns frame count on success, -EINVAL on failure. 1319 */ 1320 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1321 { 1322 struct drm_device *dev = crtc->dev; 1323 unsigned int pipe = crtc->index; 1324 struct amdgpu_device *adev = drm_to_adev(dev); 1325 int vpos, hpos, stat; 1326 u32 count; 1327 1328 if (pipe >= adev->mode_info.num_crtc) { 1329 DRM_ERROR("Invalid crtc %u\n", pipe); 1330 return -EINVAL; 1331 } 1332 1333 /* The hw increments its frame counter at start of vsync, not at start 1334 * of vblank, as is required by DRM core vblank counter handling. 1335 * Cook the hw count here to make it appear to the caller as if it 1336 * incremented at start of vblank. We measure distance to start of 1337 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1338 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1339 * result by 1 to give the proper appearance to caller. 1340 */ 1341 if (adev->mode_info.crtcs[pipe]) { 1342 /* Repeat readout if needed to provide stable result if 1343 * we cross start of vsync during the queries. 1344 */ 1345 do { 1346 count = amdgpu_display_vblank_get_counter(adev, pipe); 1347 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1348 * vpos as distance to start of vblank, instead of 1349 * regular vertical scanout pos. 1350 */ 1351 stat = amdgpu_display_get_crtc_scanoutpos( 1352 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1353 &vpos, &hpos, NULL, NULL, 1354 &adev->mode_info.crtcs[pipe]->base.hwmode); 1355 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1356 1357 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1358 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1359 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1360 } else { 1361 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1362 pipe, vpos); 1363 1364 /* Bump counter if we are at >= leading edge of vblank, 1365 * but before vsync where vpos would turn negative and 1366 * the hw counter really increments. 1367 */ 1368 if (vpos >= 0) 1369 count++; 1370 } 1371 } else { 1372 /* Fallback to use value as is. */ 1373 count = amdgpu_display_vblank_get_counter(adev, pipe); 1374 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1375 } 1376 1377 return count; 1378 } 1379 1380 /** 1381 * amdgpu_enable_vblank_kms - enable vblank interrupt 1382 * 1383 * @crtc: crtc to enable vblank interrupt for 1384 * 1385 * Enable the interrupt on the requested crtc (all asics). 1386 * Returns 0 on success, -EINVAL on failure. 1387 */ 1388 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1389 { 1390 struct drm_device *dev = crtc->dev; 1391 unsigned int pipe = crtc->index; 1392 struct amdgpu_device *adev = drm_to_adev(dev); 1393 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1394 1395 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1396 } 1397 1398 /** 1399 * amdgpu_disable_vblank_kms - disable vblank interrupt 1400 * 1401 * @crtc: crtc to disable vblank interrupt for 1402 * 1403 * Disable the interrupt on the requested crtc (all asics). 1404 */ 1405 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1406 { 1407 struct drm_device *dev = crtc->dev; 1408 unsigned int pipe = crtc->index; 1409 struct amdgpu_device *adev = drm_to_adev(dev); 1410 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1411 1412 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1413 } 1414 1415 /* 1416 * Debugfs info 1417 */ 1418 #if defined(CONFIG_DEBUG_FS) 1419 1420 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1421 { 1422 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1423 struct drm_amdgpu_info_firmware fw_info; 1424 struct drm_amdgpu_query_fw query_fw; 1425 struct atom_context *ctx = adev->mode_info.atom_context; 1426 uint8_t smu_minor, smu_debug; 1427 uint16_t smu_major; 1428 int ret, i; 1429 1430 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1431 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1432 TA_FW_NAME(XGMI), 1433 TA_FW_NAME(RAS), 1434 TA_FW_NAME(HDCP), 1435 TA_FW_NAME(DTM), 1436 TA_FW_NAME(RAP), 1437 TA_FW_NAME(SECUREDISPLAY), 1438 #undef TA_FW_NAME 1439 }; 1440 1441 /* VCE */ 1442 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1443 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1444 if (ret) 1445 return ret; 1446 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1447 fw_info.feature, fw_info.ver); 1448 1449 /* UVD */ 1450 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1451 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1452 if (ret) 1453 return ret; 1454 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1455 fw_info.feature, fw_info.ver); 1456 1457 /* GMC */ 1458 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1459 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1460 if (ret) 1461 return ret; 1462 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1463 fw_info.feature, fw_info.ver); 1464 1465 /* ME */ 1466 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1467 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1468 if (ret) 1469 return ret; 1470 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1471 fw_info.feature, fw_info.ver); 1472 1473 /* PFP */ 1474 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1475 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1476 if (ret) 1477 return ret; 1478 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1479 fw_info.feature, fw_info.ver); 1480 1481 /* CE */ 1482 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1483 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1484 if (ret) 1485 return ret; 1486 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1487 fw_info.feature, fw_info.ver); 1488 1489 /* RLC */ 1490 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1491 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1492 if (ret) 1493 return ret; 1494 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1495 fw_info.feature, fw_info.ver); 1496 1497 /* RLC SAVE RESTORE LIST CNTL */ 1498 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1499 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1500 if (ret) 1501 return ret; 1502 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1503 fw_info.feature, fw_info.ver); 1504 1505 /* RLC SAVE RESTORE LIST GPM MEM */ 1506 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1507 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1508 if (ret) 1509 return ret; 1510 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1511 fw_info.feature, fw_info.ver); 1512 1513 /* RLC SAVE RESTORE LIST SRM MEM */ 1514 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1515 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1516 if (ret) 1517 return ret; 1518 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1519 fw_info.feature, fw_info.ver); 1520 1521 /* MEC */ 1522 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1523 query_fw.index = 0; 1524 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1525 if (ret) 1526 return ret; 1527 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1528 fw_info.feature, fw_info.ver); 1529 1530 /* MEC2 */ 1531 if (adev->gfx.mec2_fw) { 1532 query_fw.index = 1; 1533 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1534 if (ret) 1535 return ret; 1536 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1537 fw_info.feature, fw_info.ver); 1538 } 1539 1540 /* PSP SOS */ 1541 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1542 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1543 if (ret) 1544 return ret; 1545 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1546 fw_info.feature, fw_info.ver); 1547 1548 1549 /* PSP ASD */ 1550 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1551 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1552 if (ret) 1553 return ret; 1554 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1555 fw_info.feature, fw_info.ver); 1556 1557 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1558 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1559 query_fw.index = i; 1560 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1561 if (ret) 1562 continue; 1563 1564 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1565 ta_fw_name[i], fw_info.feature, fw_info.ver); 1566 } 1567 1568 /* SMC */ 1569 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1570 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1571 if (ret) 1572 return ret; 1573 smu_major = (fw_info.ver >> 16) & 0xffff; 1574 smu_minor = (fw_info.ver >> 8) & 0xff; 1575 smu_debug = (fw_info.ver >> 0) & 0xff; 1576 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x (%d.%d.%d)\n", 1577 fw_info.feature, fw_info.ver, smu_major, smu_minor, smu_debug); 1578 1579 /* SDMA */ 1580 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1581 for (i = 0; i < adev->sdma.num_instances; i++) { 1582 query_fw.index = i; 1583 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1584 if (ret) 1585 return ret; 1586 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1587 i, fw_info.feature, fw_info.ver); 1588 } 1589 1590 /* VCN */ 1591 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1592 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1593 if (ret) 1594 return ret; 1595 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1596 fw_info.feature, fw_info.ver); 1597 1598 /* DMCU */ 1599 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1600 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1601 if (ret) 1602 return ret; 1603 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1604 fw_info.feature, fw_info.ver); 1605 1606 /* DMCUB */ 1607 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1608 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1609 if (ret) 1610 return ret; 1611 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1612 fw_info.feature, fw_info.ver); 1613 1614 /* TOC */ 1615 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1616 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1617 if (ret) 1618 return ret; 1619 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1620 fw_info.feature, fw_info.ver); 1621 1622 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1623 1624 return 0; 1625 } 1626 1627 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1628 1629 #endif 1630 1631 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1632 { 1633 #if defined(CONFIG_DEBUG_FS) 1634 struct drm_minor *minor = adev_to_drm(adev)->primary; 1635 struct dentry *root = minor->debugfs_root; 1636 1637 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1638 adev, &amdgpu_debugfs_firmware_info_fops); 1639 1640 #endif 1641 } 1642